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Revision tags: v10.1.2, v10.1.1, v10.1.0 |
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| #
1943dd38
|
| 19-Aug-2025 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/pci-host/aspeed: Add MSI support and per-RC IOMMU address space
Add MSI support to the ASPEED PCIe RC/Config model and introduce a per-RC "IOMMU root" address space to correctly route MSI writes.
hw/pci-host/aspeed: Add MSI support and per-RC IOMMU address space
Add MSI support to the ASPEED PCIe RC/Config model and introduce a per-RC "IOMMU root" address space to correctly route MSI writes.
On AST2700 all RCs use the same MSI address, and the MSI target is PCI system memory (not normal DRAM). If the MSI window were mapped into real system RAM, an endpoint's write could be observed by other RCs and spuriously trigger their interrupts. To avoid this, each RC now owns an isolated IOMMU root AddressSpace that contains a small MSI window and a DRAM alias region for normal DMA.
The MSI window captures writes and asserts the RC IRQ. MSI status bits are tracked in new H2X RC_H registers (R_H2X_RC_H_MSI_EN{0,1} and R_H2X_RC_H_MSI_STS{0,1}). Clearing all status bits drops the IRQ. The default MSI address is set to 0x1e77005c and can be overridden via the msi-addr property.
This keeps MSI traffic contained within each RC while preserving normal DMA to system DRAM. It enables correct MSI/MSI-X interrupt delivery when multiple RCs use the same MSI target address.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Link: https://lore.kernel.org/qemu-devel/20250819090141.3949136-5-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
show more ...
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| #
829c97b0
|
| 19-Aug-2025 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/pci-host/aspeed: Add AST2600 PCIe config and host bridge
Introduce PCIe config and host bridge model for the AST2600 platform.
This patch adds support for the H2X (AHB to PCIe Bus Bridge) contro
hw/pci-host/aspeed: Add AST2600 PCIe config and host bridge
Introduce PCIe config and host bridge model for the AST2600 platform.
This patch adds support for the H2X (AHB to PCIe Bus Bridge) controller with a 0x100 byte register space. The register layout is shared between two root complexes: 0x00–0x7f is common, 0x80–0xbf for RC_L, and 0xc0–0xff for RC_H. Only RC_H is modeled in this implementation.
The RC_H bus uses bus numbers in the 0x80–0xff range instead of the standard root port 0x00. To allow the PCI subsystem to discover devices, the host bridge logic remaps the root bus number back to 0x00 whenever the configured bus number matches the "bus-nr" property.
New MMIO callbacks are added for the H2X config space: - aspeed_pcie_cfg_read() and aspeed_pcie_cfg_write() handle register accesses. - aspeed_pcie_cfg_readwrite() provides configuration read/write support. - aspeed_pcie_cfg_translate_write() handles PCIe byte-enable semantics for write operations.
The reset handler initializes the H2X register block with default values as defined in the AST2600 datasheet.
Additional changes: - Implement ASPEED PCIe root device (TYPE_ASPEED_PCIE_ROOT). - Implement ASPEED PCIe root complex (TYPE_ASPEED_PCIE_RC). - Wire up interrupt propagation via aspeed_pcie_rc_set_irq(). - Add tracepoints for config read/write and INTx handling.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Link: https://lore.kernel.org/qemu-devel/20250819090141.3949136-4-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
show more ...
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| #
4aee1ac7
|
| 19-Aug-2025 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/pci-host/aspeed: Add AST2600 PCIe PHY model
This patch introduces an initial ASPEED PCIe PHY/host controller model to support the AST2600 SoC. It provides a simple register block with MMIO read/w
hw/pci-host/aspeed: Add AST2600 PCIe PHY model
This patch introduces an initial ASPEED PCIe PHY/host controller model to support the AST2600 SoC. It provides a simple register block with MMIO read/write callbacks, integration into the build system, and trace events for debugging.
Key changes:
1. PCIe PHY MMIO read/write callbacks Implemented aspeed_pcie_phy_read() and aspeed_pcie_phy_write() to handle 32-bit register accesses.
2. Build system and Kconfig integration Added CONFIG_PCI_EXPRESS_ASPEED in hw/pci-host/Kconfig and meson rules. Updated ASPEED_SOC in hw/arm/Kconfig to imply PCI_DEVICES and select PCI_EXPRESS_ASPEED.
3. Trace events for debug New tracepoints aspeed_pcie_phy_read and aspeed_pcie_phy_write allow monitoring MMIO accesses.
4. Register space and defaults (AST2600 reference) Expose a 0x100 register space, as documented in the AST2600 datasheet. On reset, set default values: PEHR_ID: Vendor ID = ASPEED, Device ID = 0x1150 PEHR_CLASS_CODE = 0x06040006 PEHR_DATALINK = 0xD7040022 PEHR_LINK: bit[5] set to 1 to indicate link up.
This provides a skeleton device for the AST2600 platform. It enables firmware to detect the PCIe link as up by default and allows future extension.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Link: https://lore.kernel.org/qemu-devel/20250819090141.3949136-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
show more ...
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| #
d3920d9f
|
| 19-Aug-2025 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/pci-host/aspeed: Add MSI support and per-RC IOMMU address space
Add MSI support to the ASPEED PCIe RC/Config model and introduce a per-RC "IOMMU root" address space to correctly route MSI writes.
hw/pci-host/aspeed: Add MSI support and per-RC IOMMU address space
Add MSI support to the ASPEED PCIe RC/Config model and introduce a per-RC "IOMMU root" address space to correctly route MSI writes.
On AST2700 all RCs use the same MSI address, and the MSI target is PCI system memory (not normal DRAM). If the MSI window were mapped into real system RAM, an endpoint's write could be observed by other RCs and spuriously trigger their interrupts. To avoid this, each RC now owns an isolated IOMMU root AddressSpace that contains a small MSI window and a DRAM alias region for normal DMA.
The MSI window captures writes and asserts the RC IRQ. MSI status bits are tracked in new H2X RC_H registers (R_H2X_RC_H_MSI_EN{0,1} and R_H2X_RC_H_MSI_STS{0,1}). Clearing all status bits drops the IRQ. The default MSI address is set to 0x1e77005c and can be overridden via the msi-addr property.
This keeps MSI traffic contained within each RC while preserving normal DMA to system DRAM. It enables correct MSI/MSI-X interrupt delivery when multiple RCs use the same MSI target address.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Link: https://lore.kernel.org/qemu-devel/20250819090141.3949136-5-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
show more ...
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| #
2252b45b
|
| 19-Aug-2025 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/pci-host/aspeed: Add AST2600 PCIe config and host bridge
Introduce PCIe config and host bridge model for the AST2600 platform.
This patch adds support for the H2X (AHB to PCIe Bus Bridge) contro
hw/pci-host/aspeed: Add AST2600 PCIe config and host bridge
Introduce PCIe config and host bridge model for the AST2600 platform.
This patch adds support for the H2X (AHB to PCIe Bus Bridge) controller with a 0x100 byte register space. The register layout is shared between two root complexes: 0x00–0x7f is common, 0x80–0xbf for RC_L, and 0xc0–0xff for RC_H. Only RC_H is modeled in this implementation.
The RC_H bus uses bus numbers in the 0x80–0xff range instead of the standard root port 0x00. To allow the PCI subsystem to discover devices, the host bridge logic remaps the root bus number back to 0x00 whenever the configured bus number matches the "bus-nr" property.
New MMIO callbacks are added for the H2X config space: - aspeed_pcie_cfg_read() and aspeed_pcie_cfg_write() handle register accesses. - aspeed_pcie_cfg_readwrite() provides configuration read/write support. - aspeed_pcie_cfg_translate_write() handles PCIe byte-enable semantics for write operations.
The reset handler initializes the H2X register block with default values as defined in the AST2600 datasheet.
Additional changes: - Implement ASPEED PCIe root device (TYPE_ASPEED_PCIE_ROOT). - Implement ASPEED PCIe root complex (TYPE_ASPEED_PCIE_RC). - Wire up interrupt propagation via aspeed_pcie_rc_set_irq(). - Add tracepoints for config read/write and INTx handling.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Link: https://lore.kernel.org/qemu-devel/20250819090141.3949136-4-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
show more ...
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| #
361b056f
|
| 19-Aug-2025 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/pci-host/aspeed: Add AST2600 PCIe PHY model
This patch introduces an initial ASPEED PCIe PHY/host controller model to support the AST2600 SoC. It provides a simple register block with MMIO read/w
hw/pci-host/aspeed: Add AST2600 PCIe PHY model
This patch introduces an initial ASPEED PCIe PHY/host controller model to support the AST2600 SoC. It provides a simple register block with MMIO read/write callbacks, integration into the build system, and trace events for debugging.
Key changes:
1. PCIe PHY MMIO read/write callbacks Implemented aspeed_pcie_phy_read() and aspeed_pcie_phy_write() to handle 32-bit register accesses.
2. Build system and Kconfig integration Added CONFIG_PCI_EXPRESS_ASPEED in hw/pci-host/Kconfig and meson rules. Updated ASPEED_SOC in hw/arm/Kconfig to imply PCI_DEVICES and select PCI_EXPRESS_ASPEED.
3. Trace events for debug New tracepoints aspeed_pcie_phy_read and aspeed_pcie_phy_write allow monitoring MMIO accesses.
4. Register space and defaults (AST2600 reference) Expose a 0x100 register space, as documented in the AST2600 datasheet. On reset, set default values: PEHR_ID: Vendor ID = ASPEED, Device ID = 0x1150 PEHR_CLASS_CODE = 0x06040006 PEHR_DATALINK = 0xD7040022 PEHR_LINK: bit[5] set to 1 to indicate link up.
This provides a skeleton device for the AST2600 platform. It enables firmware to detect the PCIe link as up by default and allows future extension.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Link: https://lore.kernel.org/qemu-devel/20250819090141.3949136-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
show more ...
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| #
c1cc0922
|
| 19-Aug-2025 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/pci-host/aspeed: Add MSI support and per-RC IOMMU address space
Add MSI support to the ASPEED PCIe RC/Config model and introduce a per-RC "IOMMU root" address space to correctly route MSI writes.
hw/pci-host/aspeed: Add MSI support and per-RC IOMMU address space
Add MSI support to the ASPEED PCIe RC/Config model and introduce a per-RC "IOMMU root" address space to correctly route MSI writes.
On AST2700 all RCs use the same MSI address, and the MSI target is PCI system memory (not normal DRAM). If the MSI window were mapped into real system RAM, an endpoint's write could be observed by other RCs and spuriously trigger their interrupts. To avoid this, each RC now owns an isolated IOMMU root AddressSpace that contains a small MSI window and a DRAM alias region for normal DMA.
The MSI window captures writes and asserts the RC IRQ. MSI status bits are tracked in new H2X RC_H registers (R_H2X_RC_H_MSI_EN{0,1} and R_H2X_RC_H_MSI_STS{0,1}). Clearing all status bits drops the IRQ. The default MSI address is set to 0x1e77005c and can be overridden via the msi-addr property.
This keeps MSI traffic contained within each RC while preserving normal DMA to system DRAM. It enables correct MSI/MSI-X interrupt delivery when multiple RCs use the same MSI target address.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Link: https://lore.kernel.org/qemu-devel/20250819090141.3949136-5-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
show more ...
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| #
d4fa62cc
|
| 19-Aug-2025 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/pci-host/aspeed: Add AST2600 PCIe config and host bridge
Introduce PCIe config and host bridge model for the AST2600 platform.
This patch adds support for the H2X (AHB to PCIe Bus Bridge) contro
hw/pci-host/aspeed: Add AST2600 PCIe config and host bridge
Introduce PCIe config and host bridge model for the AST2600 platform.
This patch adds support for the H2X (AHB to PCIe Bus Bridge) controller with a 0x100 byte register space. The register layout is shared between two root complexes: 0x00–0x7f is common, 0x80–0xbf for RC_L, and 0xc0–0xff for RC_H. Only RC_H is modeled in this implementation.
The RC_H bus uses bus numbers in the 0x80–0xff range instead of the standard root port 0x00. To allow the PCI subsystem to discover devices, the host bridge logic remaps the root bus number back to 0x00 whenever the configured bus number matches the "bus-nr" property.
New MMIO callbacks are added for the H2X config space: - aspeed_pcie_cfg_read() and aspeed_pcie_cfg_write() handle register accesses. - aspeed_pcie_cfg_readwrite() provides configuration read/write support. - aspeed_pcie_cfg_translate_write() handles PCIe byte-enable semantics for write operations.
The reset handler initializes the H2X register block with default values as defined in the AST2600 datasheet.
Additional changes: - Implement ASPEED PCIe root device (TYPE_ASPEED_PCIE_ROOT). - Implement ASPEED PCIe root complex (TYPE_ASPEED_PCIE_RC). - Wire up interrupt propagation via aspeed_pcie_rc_set_irq(). - Add tracepoints for config read/write and INTx handling.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Link: https://lore.kernel.org/qemu-devel/20250819090141.3949136-4-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
show more ...
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| #
5af53aa5
|
| 19-Aug-2025 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/pci-host/aspeed: Add AST2600 PCIe PHY model
This patch introduces an initial ASPEED PCIe PHY/host controller model to support the AST2600 SoC. It provides a simple register block with MMIO read/w
hw/pci-host/aspeed: Add AST2600 PCIe PHY model
This patch introduces an initial ASPEED PCIe PHY/host controller model to support the AST2600 SoC. It provides a simple register block with MMIO read/write callbacks, integration into the build system, and trace events for debugging.
Key changes:
1. PCIe PHY MMIO read/write callbacks Implemented aspeed_pcie_phy_read() and aspeed_pcie_phy_write() to handle 32-bit register accesses.
2. Build system and Kconfig integration Added CONFIG_PCI_EXPRESS_ASPEED in hw/pci-host/Kconfig and meson rules. Updated ASPEED_SOC in hw/arm/Kconfig to imply PCI_DEVICES and select PCI_EXPRESS_ASPEED.
3. Trace events for debug New tracepoints aspeed_pcie_phy_read and aspeed_pcie_phy_write allow monitoring MMIO accesses.
4. Register space and defaults (AST2600 reference) Expose a 0x100 register space, as documented in the AST2600 datasheet. On reset, set default values: PEHR_ID: Vendor ID = ASPEED, Device ID = 0x1150 PEHR_CLASS_CODE = 0x06040006 PEHR_DATALINK = 0xD7040022 PEHR_LINK: bit[5] set to 1 to indicate link up.
This provides a skeleton device for the AST2600 platform. It enables firmware to detect the PCIe link as up by default and allows future extension.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Link: https://lore.kernel.org/qemu-devel/20250819090141.3949136-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
show more ...
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|
Revision tags: v10.0.3, v10.0.2, v10.0.1, v10.0.0, v9.2.3, v9.2.2, v9.2.1, v9.2.0, v9.1.2, v9.1.1, v9.1.0, v8.0.0, v7.2.0 |
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| #
adb76fbd
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| 11-Aug-2022 |
Cédric Le Goater <clg@kaod.org> |
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Co
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Controller (RC) 1E77:0000-1E77:0FFF AHB to PCIe RC bridge controller 6000:0000-7FFF:FFFF PCIe memory window.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
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| #
5edf56ab
|
| 11-Aug-2022 |
Cédric Le Goater <clg@kaod.org> |
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Co
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Controller (RC) 1E77:0000-1E77:0FFF AHB to PCIe RC bridge controller 6000:0000-7FFF:FFFF PCIe memory window.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
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| #
9a30aff6
|
| 11-Aug-2022 |
Cédric Le Goater <clg@kaod.org> |
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Co
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Controller (RC) 1E77:0000-1E77:0FFF AHB to PCIe RC bridge controller 6000:0000-7FFF:FFFF PCIe memory window.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
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| #
c0c20b21
|
| 11-Aug-2022 |
Cédric Le Goater <clg@kaod.org> |
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Co
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Controller (RC) 1E77:0000-1E77:0FFF AHB to PCIe RC bridge controller 6000:0000-7FFF:FFFF PCIe memory window.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
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| #
3b24d12a
|
| 11-Aug-2022 |
Cédric Le Goater <clg@kaod.org> |
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Co
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Controller (RC) 1E77:0000-1E77:0FFF AHB to PCIe RC bridge controller 6000:0000-7FFF:FFFF PCIe memory window.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
| #
249497cb
|
| 11-Aug-2022 |
Cédric Le Goater <clg@kaod.org> |
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Co
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Controller (RC) 1E77:0000-1E77:0FFF AHB to PCIe RC bridge controller 6000:0000-7FFF:FFFF PCIe memory window.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
| #
7e1e49d7
|
| 11-Aug-2022 |
Cédric Le Goater <clg@kaod.org> |
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Co
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Controller (RC) 1E77:0000-1E77:0FFF AHB to PCIe RC bridge controller 6000:0000-7FFF:FFFF PCIe memory window.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
| #
8d40a557
|
| 11-Aug-2022 |
Cédric Le Goater <clg@kaod.org> |
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Co
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Controller (RC) 1E77:0000-1E77:0FFF AHB to PCIe RC bridge controller 6000:0000-7FFF:FFFF PCIe memory window.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
| #
b017f8c7
|
| 11-Aug-2022 |
Cédric Le Goater <clg@kaod.org> |
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Co
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Controller (RC) 1E77:0000-1E77:0FFF AHB to PCIe RC bridge controller 6000:0000-7FFF:FFFF PCIe memory window.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
| #
3d54cbf2
|
| 22-Feb-2024 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'hw-misc-20240222' of https://github.com/philmd/qemu into staging
Misc HW patch queue
- Remove sysbus_add_io (Phil) - Build PPC 4xx PCI host bridges once (Phil) - Display QOM path while d
Merge tag 'hw-misc-20240222' of https://github.com/philmd/qemu into staging
Misc HW patch queue
- Remove sysbus_add_io (Phil) - Build PPC 4xx PCI host bridges once (Phil) - Display QOM path while debugging SMBus targets (Joe) - Simplify x86 PC code (Bernhard) - Remove qemu_[un]register_reset() calls in x86 PC CMOS (Peter) - Fix wiring of ICH9 LPC interrupts (Bernhard) - Split core IDE as device / bus / dma (Thomas) - Prefer QDev API over QOM for devices (Phil) - Fix invalid use of DO_UPCAST() in Leon3 (Thomas)
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* tag 'hw-misc-20240222' of https://github.com/philmd/qemu: (32 commits) hw/sparc/leon3: Fix wrong usage of DO_UPCAST macro hw/ide: Stop exposing internal.h to non-IDE files hw/ide: Remove the include/hw/ide.h legacy file hw/ide: Move IDE bus related definitions to a new header ide-bus.h hw/ide: Move IDE device related definitions to ide-dev.h hw/ide: Move IDE DMA related definitions to a separate header ide-dma.h hw/ide: Split qdev.c into ide-bus.c and ide-dev.c hw/ide: Add the possibility to disable the CompactFlash device in the build hw/acpi/ich9_tco: Include missing 'migration/vmstate.h' header hw/acpi/cpu: Use CPUState typedef hw/acpi: Include missing 'qapi/qapi-types-acpi.h' generated header hw/isa/meson.build: Sort alphabetically hw/i386/pc_q35: Populate interrupt handlers before realizing LPC PCI function hw/i386/pc_sysfw: Use qdev_is_realized() instead of QOM API hw/i386/pc_sysfw: Inline pc_system_flash_create() and remove it hw/i386/pc: Confine system flash handling to pc_sysfw hw/i386/pc: Defer smbios_set_defaults() to machine_done hw/i386/pc: Merge pc_guest_info_init() into pc_machine_initfn() hw/i386/x86: Turn apic_xrupt_override into class attribute hw/i386/pc: Do pc_cmos_init_late() from pc_machine_done() ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
# Conflicts: # include/hw/i386/pc.h
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22dc8a47
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| 10-Oct-2023 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
hw/ppc/ppc440_pcix: Move ppc440_pcix.c to hw/pci-host/
ppc440_pcix.c is moved from the target specific ppc_ss[] meson source set to pci_ss[] which is common to all targets: the object is built once.
hw/ppc/ppc440_pcix: Move ppc440_pcix.c to hw/pci-host/
ppc440_pcix.c is moved from the target specific ppc_ss[] meson source set to pci_ss[] which is common to all targets: the object is built once.
Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240215105017.57748-5-philmd@linaro.org>
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55abb29e
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| 10-Oct-2023 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
hw/ppc/ppc4xx_pci: Move ppc4xx_pci.c to hw/pci-host/
ppc4xx_pci.c is moved from the target specific ppc_ss[] meson source set to pci_ss[] which is common to all targets: the object is built once.
D
hw/ppc/ppc4xx_pci: Move ppc4xx_pci.c to hw/pci-host/
ppc4xx_pci.c is moved from the target specific ppc_ss[] meson source set to pci_ss[] which is common to all targets: the object is built once.
Declare PPC4XX_PCI selector in pci-host/Kconfig.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20240215105017.57748-4-philmd@linaro.org>
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749d14f7
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| 20-Oct-2023 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'C3700-pull-request' of https://github.com/hdeller/qemu-hppa into staging
target/hppa: Add emulation of a C3700 HP-PARISC workstation
This series adds a new PA-RISC machine emulation for
Merge tag 'C3700-pull-request' of https://github.com/hdeller/qemu-hppa into staging
target/hppa: Add emulation of a C3700 HP-PARISC workstation
This series adds a new PA-RISC machine emulation for the HP-PARISC C3700 workstation.
The physical HP C3700 machine has a PA2.0 (64-bit) CPU, in contrast to the existing emulation of a B160L workstation which is a 32-bit only machine and where it's Dino PCI controller isn't 64-bit capable.
With the HP C3700 machine emulation (together with the emulated Astro Memory controller and the Elroy PCI bridge) it's now possible to enhance the hppa CPU emulation to support the 64-bit instruction set in upcoming patches.
Helge
v4 changes: - Fix testsuite error in astro by adding a realize() implementation
v3 changes: based on feedback from BALATON Zoltan <balaton@eik.bme.hu>: - apply paches in different order to bring them logically closer to each other - update comments in lasips2 - rephrased title and commit message of MAINTAINERS patch
v2 changes: suggestions by BALATON Zoltan <balaton@eik.bme.hu>: - merged pci_ids and tulip patch - dropped comments in lasips2 - mention additional cleanups in patch "Require at least SeaBIOS-hppa version 10" suggestions by Philippe Mathieu-Daudé <philmd@linaro.org>: - dropped static pci_bus variable
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* tag 'C3700-pull-request' of https://github.com/hdeller/qemu-hppa: hw/hppa: Add new HP C3700 machine hw/hppa: Split out machine creation hw/hppa: Provide RTC and DebugOutputPort on CPU #0 hw/hppa: Export machine name, BTLBs, power-button address via fw_cfg MAINTAINERS: Update HP-PARISC entries pci-host: Wire up new Astro/Elroy PCI bridge hw/pci-host: Add Astro system bus adapter found on PA-RISC machines lasips2: LASI PS/2 devices are not user-createable pci_ids/tulip: Add PCI vendor ID for HP and use it in tulip hw/hppa: Require at least SeaBIOS-hppa version 10 target/hppa: Update to SeaBIOS-hppa version 10
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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e029bb00
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| 13-Oct-2023 |
Helge Deller <deller@gmx.de> |
hw/pci-host: Add Astro system bus adapter found on PA-RISC machines
The 64-bit PA-RISC machines use a Astro system bus adapter (SBA) with Elroy PCI host chips. Later generation Astro chips were name
hw/pci-host: Add Astro system bus adapter found on PA-RISC machines
The 64-bit PA-RISC machines use a Astro system bus adapter (SBA) with Elroy PCI host chips. Later generation Astro chips were named Pluto, Ike and REO.
Signed-off-by: Helge Deller <deller@gmx.de>
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cc9c5a77
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| 16-Aug-2023 |
Cédric Le Goater <clg@kaod.org> |
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Co
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Controller (RC) 1E77:0000-1E77:0FFF AHB to PCIe RC bridge controller 6000:0000-7FFF:FFFF PCIe memory window.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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f4d7517c
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| 13-Apr-2023 |
Cédric Le Goater <clg@kaod.org> |
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Co
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Controller (RC) 1E77:0000-1E77:0FFF AHB to PCIe RC bridge controller 6000:0000-7FFF:FFFF PCIe memory window.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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