Revision tags: v10.1.0 |
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#
c1cc0922
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| 19-Aug-2025 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/pci-host/aspeed: Add MSI support and per-RC IOMMU address space
Add MSI support to the ASPEED PCIe RC/Config model and introduce a per-RC "IOMMU root" address space to correctly route MSI writes.
hw/pci-host/aspeed: Add MSI support and per-RC IOMMU address space
Add MSI support to the ASPEED PCIe RC/Config model and introduce a per-RC "IOMMU root" address space to correctly route MSI writes.
On AST2700 all RCs use the same MSI address, and the MSI target is PCI system memory (not normal DRAM). If the MSI window were mapped into real system RAM, an endpoint's write could be observed by other RCs and spuriously trigger their interrupts. To avoid this, each RC now owns an isolated IOMMU root AddressSpace that contains a small MSI window and a DRAM alias region for normal DMA.
The MSI window captures writes and asserts the RC IRQ. MSI status bits are tracked in new H2X RC_H registers (R_H2X_RC_H_MSI_EN{0,1} and R_H2X_RC_H_MSI_STS{0,1}). Clearing all status bits drops the IRQ. The default MSI address is set to 0x1e77005c and can be overridden via the msi-addr property.
This keeps MSI traffic contained within each RC while preserving normal DMA to system DRAM. It enables correct MSI/MSI-X interrupt delivery when multiple RCs use the same MSI target address.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Link: https://lore.kernel.org/qemu-devel/20250819090141.3949136-5-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
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#
d4fa62cc
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| 19-Aug-2025 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/pci-host/aspeed: Add AST2600 PCIe config and host bridge
Introduce PCIe config and host bridge model for the AST2600 platform.
This patch adds support for the H2X (AHB to PCIe Bus Bridge) contro
hw/pci-host/aspeed: Add AST2600 PCIe config and host bridge
Introduce PCIe config and host bridge model for the AST2600 platform.
This patch adds support for the H2X (AHB to PCIe Bus Bridge) controller with a 0x100 byte register space. The register layout is shared between two root complexes: 0x00–0x7f is common, 0x80–0xbf for RC_L, and 0xc0–0xff for RC_H. Only RC_H is modeled in this implementation.
The RC_H bus uses bus numbers in the 0x80–0xff range instead of the standard root port 0x00. To allow the PCI subsystem to discover devices, the host bridge logic remaps the root bus number back to 0x00 whenever the configured bus number matches the "bus-nr" property.
New MMIO callbacks are added for the H2X config space: - aspeed_pcie_cfg_read() and aspeed_pcie_cfg_write() handle register accesses. - aspeed_pcie_cfg_readwrite() provides configuration read/write support. - aspeed_pcie_cfg_translate_write() handles PCIe byte-enable semantics for write operations.
The reset handler initializes the H2X register block with default values as defined in the AST2600 datasheet.
Additional changes: - Implement ASPEED PCIe root device (TYPE_ASPEED_PCIE_ROOT). - Implement ASPEED PCIe root complex (TYPE_ASPEED_PCIE_RC). - Wire up interrupt propagation via aspeed_pcie_rc_set_irq(). - Add tracepoints for config read/write and INTx handling.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Link: https://lore.kernel.org/qemu-devel/20250819090141.3949136-4-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
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#
5af53aa5
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| 19-Aug-2025 |
Jamin Lin <jamin_lin@aspeedtech.com> |
hw/pci-host/aspeed: Add AST2600 PCIe PHY model
This patch introduces an initial ASPEED PCIe PHY/host controller model to support the AST2600 SoC. It provides a simple register block with MMIO read/w
hw/pci-host/aspeed: Add AST2600 PCIe PHY model
This patch introduces an initial ASPEED PCIe PHY/host controller model to support the AST2600 SoC. It provides a simple register block with MMIO read/write callbacks, integration into the build system, and trace events for debugging.
Key changes:
1. PCIe PHY MMIO read/write callbacks Implemented aspeed_pcie_phy_read() and aspeed_pcie_phy_write() to handle 32-bit register accesses.
2. Build system and Kconfig integration Added CONFIG_PCI_EXPRESS_ASPEED in hw/pci-host/Kconfig and meson rules. Updated ASPEED_SOC in hw/arm/Kconfig to imply PCI_DEVICES and select PCI_EXPRESS_ASPEED.
3. Trace events for debug New tracepoints aspeed_pcie_phy_read and aspeed_pcie_phy_write allow monitoring MMIO accesses.
4. Register space and defaults (AST2600 reference) Expose a 0x100 register space, as documented in the AST2600 datasheet. On reset, set default values: PEHR_ID: Vendor ID = ASPEED, Device ID = 0x1150 PEHR_CLASS_CODE = 0x06040006 PEHR_DATALINK = 0xD7040022 PEHR_LINK: bit[5] set to 1 to indicate link up.
This provides a skeleton device for the AST2600 platform. It enables firmware to detect the PCIe link as up by default and allows future extension.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Link: https://lore.kernel.org/qemu-devel/20250819090141.3949136-3-jamin_lin@aspeedtech.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
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Revision tags: v10.0.3, v10.0.2, v10.0.1, v10.0.0, v9.2.3, v9.2.2, v9.2.1, v9.2.0, v9.1.2, v9.1.1, v9.1.0, v8.0.0, v7.2.0 |
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#
adb76fbd
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| 11-Aug-2022 |
Cédric Le Goater <clg@kaod.org> |
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Co
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Controller (RC) 1E77:0000-1E77:0FFF AHB to PCIe RC bridge controller 6000:0000-7FFF:FFFF PCIe memory window.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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5edf56ab
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| 11-Aug-2022 |
Cédric Le Goater <clg@kaod.org> |
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Co
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Controller (RC) 1E77:0000-1E77:0FFF AHB to PCIe RC bridge controller 6000:0000-7FFF:FFFF PCIe memory window.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
9a30aff6
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| 11-Aug-2022 |
Cédric Le Goater <clg@kaod.org> |
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Co
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Controller (RC) 1E77:0000-1E77:0FFF AHB to PCIe RC bridge controller 6000:0000-7FFF:FFFF PCIe memory window.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
c0c20b21
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| 11-Aug-2022 |
Cédric Le Goater <clg@kaod.org> |
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Co
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Controller (RC) 1E77:0000-1E77:0FFF AHB to PCIe RC bridge controller 6000:0000-7FFF:FFFF PCIe memory window.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
3b24d12a
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| 11-Aug-2022 |
Cédric Le Goater <clg@kaod.org> |
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Co
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Controller (RC) 1E77:0000-1E77:0FFF AHB to PCIe RC bridge controller 6000:0000-7FFF:FFFF PCIe memory window.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
249497cb
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| 11-Aug-2022 |
Cédric Le Goater <clg@kaod.org> |
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Co
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Controller (RC) 1E77:0000-1E77:0FFF AHB to PCIe RC bridge controller 6000:0000-7FFF:FFFF PCIe memory window.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
7e1e49d7
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| 11-Aug-2022 |
Cédric Le Goater <clg@kaod.org> |
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Co
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Controller (RC) 1E77:0000-1E77:0FFF AHB to PCIe RC bridge controller 6000:0000-7FFF:FFFF PCIe memory window.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
8d40a557
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| 11-Aug-2022 |
Cédric Le Goater <clg@kaod.org> |
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Co
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Controller (RC) 1E77:0000-1E77:0FFF AHB to PCIe RC bridge controller 6000:0000-7FFF:FFFF PCIe memory window.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
b017f8c7
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| 11-Aug-2022 |
Cédric Le Goater <clg@kaod.org> |
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Co
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Controller (RC) 1E77:0000-1E77:0FFF AHB to PCIe RC bridge controller 6000:0000-7FFF:FFFF PCIe memory window.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
3d54cbf2
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| 22-Feb-2024 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'hw-misc-20240222' of https://github.com/philmd/qemu into staging
Misc HW patch queue
- Remove sysbus_add_io (Phil) - Build PPC 4xx PCI host bridges once (Phil) - Display QOM path while d
Merge tag 'hw-misc-20240222' of https://github.com/philmd/qemu into staging
Misc HW patch queue
- Remove sysbus_add_io (Phil) - Build PPC 4xx PCI host bridges once (Phil) - Display QOM path while debugging SMBus targets (Joe) - Simplify x86 PC code (Bernhard) - Remove qemu_[un]register_reset() calls in x86 PC CMOS (Peter) - Fix wiring of ICH9 LPC interrupts (Bernhard) - Split core IDE as device / bus / dma (Thomas) - Prefer QDev API over QOM for devices (Phil) - Fix invalid use of DO_UPCAST() in Leon3 (Thomas)
# -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmXXQ1IACgkQ4+MsLN6t # wN4e2xAAig55EJh/JwpdGx55rFUab3Ay22jgXrExmBir8hzhyzssY+RUj2ALRa5e # T26kxCEqiuT549FtWm/ci6kVax0QD6bqz/6/j451XB9469Z/3BDOV5rhsqF6zlr5 # BMbyC8PKnMUluG8v1ZuRjC3m2lK3ZvkVnZtj7SZUR50ssEnR32fVIziN14/OYkts # 2B24sLrnLBfvyatMRsuFqGWrcbtMdnwNpjenGfDPOTF33W1sxTQ8GSvx1RV32l69 # Yr/iCVoCl+rGxbLLP1TwqtOwzk32p8RsbIt6rWMqVMv/p5F6ezFeiOk7VHnnEJRH # e7TPxt4XeLGPARMQLT3gQh0MGIIodanSHePRBkczuNmKYTJrz+5jMu2Qg4MmMUE/ # TV0fKgdjh/edhAOHzJgZqLmNV71icl8WBjfsw2qT4ZwgJzWq7YM2/XZKkeWhk2nQ # whLxfgiU4PNJ6vHhebJNjOovCYQTK2FbXR+PvVn5FEbH4CuFr8mqkYc+vNYM9dLA # b7uMk1H8kcb5+kqfPPU2lVd1wO7uqhxYOYU2O9nYq8aw7ioLoLeEdj2IicLtrA/H # GMtyA5cYeabeRzSXF30tM2AR1uQ/e4Z7oNxW6z3GVK1NrQtKilqPgMKut8uWYvva # crJLpRQhGiY3sDrIkkCcAHzv256dZaJNLR1KPViaHOyVPZV+x2s= # =+h2O # -----END PGP SIGNATURE----- # gpg: Signature made Thu 22 Feb 2024 12:51:30 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'hw-misc-20240222' of https://github.com/philmd/qemu: (32 commits) hw/sparc/leon3: Fix wrong usage of DO_UPCAST macro hw/ide: Stop exposing internal.h to non-IDE files hw/ide: Remove the include/hw/ide.h legacy file hw/ide: Move IDE bus related definitions to a new header ide-bus.h hw/ide: Move IDE device related definitions to ide-dev.h hw/ide: Move IDE DMA related definitions to a separate header ide-dma.h hw/ide: Split qdev.c into ide-bus.c and ide-dev.c hw/ide: Add the possibility to disable the CompactFlash device in the build hw/acpi/ich9_tco: Include missing 'migration/vmstate.h' header hw/acpi/cpu: Use CPUState typedef hw/acpi: Include missing 'qapi/qapi-types-acpi.h' generated header hw/isa/meson.build: Sort alphabetically hw/i386/pc_q35: Populate interrupt handlers before realizing LPC PCI function hw/i386/pc_sysfw: Use qdev_is_realized() instead of QOM API hw/i386/pc_sysfw: Inline pc_system_flash_create() and remove it hw/i386/pc: Confine system flash handling to pc_sysfw hw/i386/pc: Defer smbios_set_defaults() to machine_done hw/i386/pc: Merge pc_guest_info_init() into pc_machine_initfn() hw/i386/x86: Turn apic_xrupt_override into class attribute hw/i386/pc: Do pc_cmos_init_late() from pc_machine_done() ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
# Conflicts: # include/hw/i386/pc.h
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#
22dc8a47
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| 10-Oct-2023 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
hw/ppc/ppc440_pcix: Move ppc440_pcix.c to hw/pci-host/
ppc440_pcix.c is moved from the target specific ppc_ss[] meson source set to pci_ss[] which is common to all targets: the object is built once.
hw/ppc/ppc440_pcix: Move ppc440_pcix.c to hw/pci-host/
ppc440_pcix.c is moved from the target specific ppc_ss[] meson source set to pci_ss[] which is common to all targets: the object is built once.
Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240215105017.57748-5-philmd@linaro.org>
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#
55abb29e
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| 10-Oct-2023 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
hw/ppc/ppc4xx_pci: Move ppc4xx_pci.c to hw/pci-host/
ppc4xx_pci.c is moved from the target specific ppc_ss[] meson source set to pci_ss[] which is common to all targets: the object is built once.
D
hw/ppc/ppc4xx_pci: Move ppc4xx_pci.c to hw/pci-host/
ppc4xx_pci.c is moved from the target specific ppc_ss[] meson source set to pci_ss[] which is common to all targets: the object is built once.
Declare PPC4XX_PCI selector in pci-host/Kconfig.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20240215105017.57748-4-philmd@linaro.org>
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#
749d14f7
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| 20-Oct-2023 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'C3700-pull-request' of https://github.com/hdeller/qemu-hppa into staging
target/hppa: Add emulation of a C3700 HP-PARISC workstation
This series adds a new PA-RISC machine emulation for
Merge tag 'C3700-pull-request' of https://github.com/hdeller/qemu-hppa into staging
target/hppa: Add emulation of a C3700 HP-PARISC workstation
This series adds a new PA-RISC machine emulation for the HP-PARISC C3700 workstation.
The physical HP C3700 machine has a PA2.0 (64-bit) CPU, in contrast to the existing emulation of a B160L workstation which is a 32-bit only machine and where it's Dino PCI controller isn't 64-bit capable.
With the HP C3700 machine emulation (together with the emulated Astro Memory controller and the Elroy PCI bridge) it's now possible to enhance the hppa CPU emulation to support the 64-bit instruction set in upcoming patches.
Helge
v4 changes: - Fix testsuite error in astro by adding a realize() implementation
v3 changes: based on feedback from BALATON Zoltan <balaton@eik.bme.hu>: - apply paches in different order to bring them logically closer to each other - update comments in lasips2 - rephrased title and commit message of MAINTAINERS patch
v2 changes: suggestions by BALATON Zoltan <balaton@eik.bme.hu>: - merged pci_ids and tulip patch - dropped comments in lasips2 - mention additional cleanups in patch "Require at least SeaBIOS-hppa version 10" suggestions by Philippe Mathieu-Daudé <philmd@linaro.org>: - dropped static pci_bus variable
# -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQS86RI+GtKfB8BJu973ErUQojoPXwUCZTGzDQAKCRD3ErUQojoP # X9psAP0cHfTuJuXMiBWhrJhfp5VV0TURvaNXjCGyK8qvfbK+zgEArg3nvKhZPvnu # jVSq6b/Ppf3eCAZIYSVIsfLITbElTQ4= # =Esj+ # -----END PGP SIGNATURE----- # gpg: Signature made Thu 19 Oct 2023 15:51:57 PDT # gpg: using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F # gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown] # gpg: aka "Helge Deller <deller@kernel.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4544 8228 2CD9 10DB EF3D 25F8 3E5F 3D04 A7A2 4603 # Subkey fingerprint: BCE9 123E 1AD2 9F07 C049 BBDE F712 B510 A23A 0F5F
* tag 'C3700-pull-request' of https://github.com/hdeller/qemu-hppa: hw/hppa: Add new HP C3700 machine hw/hppa: Split out machine creation hw/hppa: Provide RTC and DebugOutputPort on CPU #0 hw/hppa: Export machine name, BTLBs, power-button address via fw_cfg MAINTAINERS: Update HP-PARISC entries pci-host: Wire up new Astro/Elroy PCI bridge hw/pci-host: Add Astro system bus adapter found on PA-RISC machines lasips2: LASI PS/2 devices are not user-createable pci_ids/tulip: Add PCI vendor ID for HP and use it in tulip hw/hppa: Require at least SeaBIOS-hppa version 10 target/hppa: Update to SeaBIOS-hppa version 10
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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#
e029bb00
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| 13-Oct-2023 |
Helge Deller <deller@gmx.de> |
hw/pci-host: Add Astro system bus adapter found on PA-RISC machines
The 64-bit PA-RISC machines use a Astro system bus adapter (SBA) with Elroy PCI host chips. Later generation Astro chips were name
hw/pci-host: Add Astro system bus adapter found on PA-RISC machines
The 64-bit PA-RISC machines use a Astro system bus adapter (SBA) with Elroy PCI host chips. Later generation Astro chips were named Pluto, Ike and REO.
Signed-off-by: Helge Deller <deller@gmx.de>
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#
cc9c5a77
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| 16-Aug-2023 |
Cédric Le Goater <clg@kaod.org> |
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Co
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Controller (RC) 1E77:0000-1E77:0FFF AHB to PCIe RC bridge controller 6000:0000-7FFF:FFFF PCIe memory window.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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#
f4d7517c
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| 13-Apr-2023 |
Cédric Le Goater <clg@kaod.org> |
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Co
pci: Add Aspeed host bridge (WIP)
IRQ:
167 AHB to PCIe Bus bridge L 168 AHB to PCIe Bus bridge H
MEM:
1E6E:D000-1E6E:D1FF PCIe Host Controller (RC/Bridge) 1E6E:D200-1E6E:D3FF PCIe Host Controller (RC) 1E77:0000-1E77:0FFF AHB to PCIe RC bridge controller 6000:0000-7FFF:FFFF PCIe memory window.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
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a8d6abe1
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| 16-Jan-2023 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'mips-20230113' of https://github.com/philmd/qemu into staging
MIPS patches queue
A bunch of cleanups from various people.
- Improved GT64120 on big-endian hosts - GT64120 north bridge a
Merge tag 'mips-20230113' of https://github.com/philmd/qemu into staging
MIPS patches queue
A bunch of cleanups from various people.
- Improved GT64120 on big-endian hosts - GT64120 north bridge and MC146818 RTC devices are now target independent - Bonito64 north bridge converted to 3-phase reset API - PCI refactors around PIIX devices - Support for nanoMIPS in bootloader generator API - New YAMON Malta Avocado test - Removal of 'trap and emulate' KVM support - System-specific QMP commands restricted to system emulation
# -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmPBekAACgkQ4+MsLN6t # wN4wjxAAtYxyt6WUBpiYfV/LnbQFpAsacues1Vhy9MPYEg5a/iuXWKvWtgRYvGww # qR0GVQH8rH7tgnCZK+ioq9jX+hvfBskP6CnKhxmb5zDGm7vP7jhhu8UFWY/EtBgq # 0zpNeLMXtnRJ6PBqo/nWFCVtcpDRZ6IkSbpGWkVkciRFc5n/2VCnlIj8k2I1oMvL # 11cp2xFQnaPReFXIpMjJHuHv1NObykdlvVg6wQo/A/4qIb8EvJQEPmePjG9Sf0i0 # v2dhnnxG9mze7+uq0dIC16x8Azko3N7dmtNlBU/aGb9OELwx35aux2M4dNDVogwn # DqL/Wsk54TFewECOfS48t/a/TqV8j/ISW1d/JvovBrN2KovmIAbtqHuMUqKVk5l0 # 23ZOIIPIYwmScZwIlkCIGUuIzFig1zhEmQcoEQaFe/B0oLB2eN/x0Bk9Yklo+i2A # WNiyiAj7k5492qEdndOySEEDVt6886F/+CdQ6QYF5Z1L/ELck7XHBH3mGDznWpPn # 6IURyVquPJx7ul62jSGI+Gc+qakNoahIhPo5O7hklOM9GwWNOWXHveyb7xjs7j+O # eWyVcet+o7hoHkCzmfbyTPySI4qCpF9fA42jqPhATwQPwmGXpbr+4BxUq3KtE43y # w9tEigwd4voN3dWLItVh6QE4in70osz3XHp93byvo8bHlS0huVY= # =oXX+ # -----END PGP SIGNATURE----- # gpg: Signature made Fri 13 Jan 2023 15:35:28 GMT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'mips-20230113' of https://github.com/philmd/qemu: (46 commits) scripts/git.orderfile: Display MAINTAINERS changes first target/mips: Restrict 'qapi-commands-machine.h' to system emulation hw/mips/boston: Rename MachineState 'mc' pointer to 'ms' hw/pci-host/bonito: Declare TYPE_BONITO_PCI_HOST_BRIDGE in header hw/pci-host/bonito: Use 'bonito_pci' for PCI function #0 code hw/pci-host/bonito: Use 'bonito_host' for PCI host bridge code hw/pci-host/bonito: Convert to 3-phase reset softmmu/rtc: Emit warning when using driftfix=slew on systems without mc146818 hw/rtc/mc146818rtc: Make the mc146818 RTC device target independent hw/core/qdev-properties-system: Allow the 'slew' policy only on x86 hw/intc: Extract the IRQ counting functions into a separate file hw/intc/i8259: Make using the isa_pic singleton more type-safe hw/usb/hcd-uhci: Introduce TYPE_ defines for device models hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specific hw/isa/piix3: Decouple INTx-to-LNKx routing which is board-specific hw/pci/pci: Factor out pci_bus_map_irqs() from pci_bus_irqs() hw/pci/pci_host: Trace config accesses on unexisting functions mips: Always include nanomips disassembler mips: Remove support for trap and emulate KVM ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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a7db759e
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| 13-Jan-2023 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
hw/mips/gt64xxx_pci: Move it to hw/pci-host/
The GT-64120 is a north-bridge, and it is not MIPS specific. Move it with the other north-bridge devices.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@a
hw/mips/gt64xxx_pci: Move it to hw/pci-host/
The GT-64120 is a north-bridge, and it is not MIPS specific. Move it with the other north-bridge devices.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20221209151533.69516-8-philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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#
55462322
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| 08-May-2022 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into staging
qemu-sparc queue
# -----BEGIN PGP SIGNATURE----- # # iQFSBAABCgA8FiEEzGIauY6CIA2RXMnEW8LFb64PMh8FAmJ4A6ceHG1hcmsuY2F
Merge tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu into staging
qemu-sparc queue
# -----BEGIN PGP SIGNATURE----- # # iQFSBAABCgA8FiEEzGIauY6CIA2RXMnEW8LFb64PMh8FAmJ4A6ceHG1hcmsuY2F2 # ZS1heWxhbmRAaWxhbmRlLmNvLnVrAAoJEFvCxW+uDzIf4SAH+weljMrdObceJ4vg # MedvVXUGmr0Uzk0iSkac1FGLCwEC/9bzBMrxMxNCsGHwVWjuX7S9Vikj/4mMi15U # 6iJ56QzVbsxZknr2+gGtB4QEAWHlQSuSrvcFVFc+Vc9enCBZNZoaehF0HzUSUFxU # nMnZQqDWrc4H9D2E+YK4OLgv3IMqOy3uKWMgIZ7JJX6YebLMXqZV1mq2G9LjKf9X # zM3HM6V9yd+1UEzb5biHkorBcdyt5F8P/V1VtiGZYFws27UwSBxW9EEDV3XcSGYD # kS9RpYka4qmC0saj5cBUR/AYQ/jwSbI9kEs4VsBzRQ/eX25F5TPEbyXp6bJZ75Gi # tsOhvvg= # =Qnnm # -----END PGP SIGNATURE----- # gpg: Signature made Sun 08 May 2022 12:53:43 PM CDT # gpg: using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F # gpg: issuer "mark.cave-ayland@ilande.co.uk" # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: CC62 1AB9 8E82 200D 915C C9C4 5BC2 C56F AE0F 321F
* tag 'qemu-sparc-20220508' of https://github.com/mcayland/qemu: (53 commits) artist: only render dirty scanlines on the display surface artist: remove unused ROP8OFF() macro artist: checkpatch and newline style fixes hppa: simplify machine function names in machine.c hppa: fold machine_hppa_machine_init() into machine_hppa_machine_init_class_init() hppa: use MACHINE QOM macros for defining the hppa machine hppa: remove the empty hppa_sys.h file hppa: move enable_lan() define from hppa_sys.h to machine.c hppa: remove unused trace-events from from hw/hppa hppa: remove hw/hppa/pci.c hppa: move hppa_pci_ignore_ops from pci.c to machine.c lasi: move from hw/hppa to hw/misc hppa: move device headers from hppa_sys.h into individual .c files lasi: use numerical constant for iar reset value lasi: use constants for device register offsets lasi: move lasi_initfn() to machine.c lasi: remove address space parameter from lasi_initfn() lasi: move PS2 initialisation to machine.c lasi: move second serial port initialisation to machine.c lasi: move parallel port initialisation to machine.c ...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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0db9350e
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| 04-May-2022 |
Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> |
dino: move from hw/hppa to hw/pci-host
Move the DINO device implementation from hw/hppa to hw/pci-host so that it is located with all the other PCI host bridges.
Signed-off-by: Mark Cave-Ayland <ma
dino: move from hw/hppa to hw/pci-host
Move the DINO device implementation from hw/hppa to hw/pci-host so that it is located with all the other PCI host bridges.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Acked-by: Helge Deller <deller@gmx.de> Message-Id: <20220504092600.10048-23-mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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Revision tags: v7.0.0 |
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64ada298
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| 02-Mar-2022 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220302' into staging
ppc-7.0 queue
* ppc/pnv fixes * PMU EBB support * target/ppc: PowerISA Vector/VSX instruction batch * ppc/pnv: Ex
Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220302' into staging
ppc-7.0 queue
* ppc/pnv fixes * PMU EBB support * target/ppc: PowerISA Vector/VSX instruction batch * ppc/pnv: Extension of the powernv10 machine with XIVE2 ans PHB5 models * spapr allocation cleanups
# gpg: Signature made Wed 02 Mar 2022 11:00:42 GMT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* remotes/legoater/tags/pull-ppc-20220302: (87 commits) hw/ppc/spapr_vio.c: use g_autofree in spapr_dt_vdevice() hw/ppc/spapr_rtas.c: use g_autofree in rtas_ibm_get_system_parameter() spapr_pci_nvlink2.c: use g_autofree in spapr_phb_nvgpu_ram_populate_dt() hw/ppc/spapr_numa.c: simplify spapr_numa_write_assoc_lookup_arrays() hw/ppc/spapr_drc.c: use g_autofree in spapr_drc_by_index() hw/ppc/spapr_drc.c: use g_autofree in spapr_dr_connector_new() hw/ppc/spapr_drc.c: use g_autofree in drc_unrealize() hw/ppc/spapr_drc.c: use g_autofree in drc_realize() hw/ppc/spapr_drc.c: use g_auto in spapr_dt_drc() hw/ppc/spapr_caps.c: use g_autofree in spapr_caps_add_properties() hw/ppc/spapr_caps.c: use g_autofree in spapr_cap_get_string() hw/ppc/spapr_caps.c: use g_autofree in spapr_cap_set_string() hw/ppc/spapr.c: fail early if no firmware found in machine_init() hw/ppc/spapr.c: use g_autofree in spapr_dt_chosen() pnv/xive2: Add support for 8bits thread id pnv/xive2: Add support for automatic save&restore xive2: Add a get_config() handler for the router configuration pnv/xive2: Add support XIVE2 P9-compat mode (or Gen1) ppc/pnv: add XIVE Gen2 TIMA support pnv/xive2: Introduce new capability bits ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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34b0696b
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| 01-Mar-2022 |
Cédric Le Goater <clg@kaod.org> |
ppc/pnv: Add support for PHB5 "Address-based trigger" mode
When the Address-Based Interrupt Trigger mode is activated, the PHB maps the interrupt source number into the interrupt command address. Th
ppc/pnv: Add support for PHB5 "Address-based trigger" mode
When the Address-Based Interrupt Trigger mode is activated, the PHB maps the interrupt source number into the interrupt command address. The PHB directly triggers the IC ESB page of the interrupt number and not the notify page of the IC anymore.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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