131 	union dcgu_reset_unit1 val;  in dcgu_set_reset_switch()  local
147 	val.reg = reg_read(DCGU_RESET_UNIT1(DCGU_BASE));  in dcgu_set_reset_switch()
150 		val.bits.swreset_clkmsmc = enable;  in dcgu_set_reset_switch()
153 		val.bits.swreset_clkssi_s = enable;  in dcgu_set_reset_switch()
156 		val.bits.swreset_clkssi_m = enable;  in dcgu_set_reset_switch()
159 		val.bits.swreset_clksmc = enable;  in dcgu_set_reset_switch()
162 		val.bits.swreset_clkebi = enable;  in dcgu_set_reset_switch()
165 		val.bits.swreset_clkusb60 = enable;  in dcgu_set_reset_switch()
168 		val.bits.swreset_clkusb24 = enable;  in dcgu_set_reset_switch()
171 		val.bits.swreset_clkuart2 = enable;  in dcgu_set_reset_switch()
174 		val.bits.swreset_clkuart1 = enable;  in dcgu_set_reset_switch()
177 		val.bits.swreset_pwm = enable;  in dcgu_set_reset_switch()
180 		val.bits.swreset_gpt = enable;  in dcgu_set_reset_switch()
183 		val.bits.swreset_i2c2 = enable;  in dcgu_set_reset_switch()
186 		val.bits.swreset_i2c1 = enable;  in dcgu_set_reset_switch()
189 		val.bits.swreset_gpio2 = enable;  in dcgu_set_reset_switch()
192 		val.bits.swreset_gpio1 = enable;  in dcgu_set_reset_switch()
195 		val.bits.swreset_clkcpu = enable;  in dcgu_set_reset_switch()
198 		val.bits.swreset_clk_i2s_dly = enable;  in dcgu_set_reset_switch()
201 		val.bits.swreset_clk_scc_abp = enable;  in dcgu_set_reset_switch()
204 		val.bits.swreset_clk_dtv_spdo = enable;  in dcgu_set_reset_switch()
207 		val.bits.swreset_clkad = enable;  in dcgu_set_reset_switch()
210 		val.bits.swreset_clkmvd = enable;  in dcgu_set_reset_switch()
213 		val.bits.swreset_clktsd = enable;  in dcgu_set_reset_switch()
216 		val.bits.swreset_clktsio = enable;  in dcgu_set_reset_switch()
219 		val.bits.swreset_clkga = enable;  in dcgu_set_reset_switch()
222 		val.bits.swreset_clkmpc = enable;  in dcgu_set_reset_switch()
225 		val.bits.swreset_clkcve = enable;  in dcgu_set_reset_switch()
228 		val.bits.swreset_clkdvp = enable;  in dcgu_set_reset_switch()
231 		val.bits.swreset_clkmr2 = enable;  in dcgu_set_reset_switch()
234 		val.bits.swreset_clkmr1 = enable;  in dcgu_set_reset_switch()
241 	reg_write(DCGU_RESET_UNIT1(DCGU_BASE), val.reg);  in dcgu_set_reset_switch()