Lines Matching full:val
134 uint64_t val; in helper_wrmsr() local
139 val = ((uint32_t)env->regs[R_EAX]) | in helper_wrmsr()
144 env->sysenter_cs = val & 0xffff; in helper_wrmsr()
147 env->sysenter_esp = val; in helper_wrmsr()
150 env->sysenter_eip = val; in helper_wrmsr()
155 if (val & MSR_IA32_APICBASE_RESERVED) { in helper_wrmsr()
159 ret = cpu_set_apic_base(env_archcpu(env)->apic_state, val); in helper_wrmsr()
189 (val & update_mask)); in helper_wrmsr()
193 env->star = val; in helper_wrmsr()
196 env->pat = val; in helper_wrmsr()
199 if (val & 0xFFFFFFFF00000000ull) { in helper_wrmsr()
202 env->pkrs = val; in helper_wrmsr()
206 if (val & (0xfff | ((~0ULL) << env_archcpu(env)->phys_bits))) { in helper_wrmsr()
209 env->vm_hsave = val; in helper_wrmsr()
213 env->lstar = val; in helper_wrmsr()
216 env->cstar = val; in helper_wrmsr()
219 env->fmask = val; in helper_wrmsr()
222 env->segs[R_FS].base = val; in helper_wrmsr()
225 env->segs[R_GS].base = val; in helper_wrmsr()
228 env->kernelgsbase = val; in helper_wrmsr()
240 MSR_MTRRphysBase(0)) / 2].base = val; in helper_wrmsr()
251 MSR_MTRRphysMask(0)) / 2].mask = val; in helper_wrmsr()
255 MSR_MTRRfix64K_00000] = val; in helper_wrmsr()
260 MSR_MTRRfix16K_80000 + 1] = val; in helper_wrmsr()
271 MSR_MTRRfix4K_C0000 + 3] = val; in helper_wrmsr()
274 env->mtrr_deftype = val; in helper_wrmsr()
277 env->mcg_status = val; in helper_wrmsr()
281 && (val == 0 || val == ~(uint64_t)0)) { in helper_wrmsr()
282 env->mcg_ctl = val; in helper_wrmsr()
286 env->tsc_aux = val; in helper_wrmsr()
289 env->msr_ia32_misc_enable = val; in helper_wrmsr()
294 env->msr_bndcfgs = val; in helper_wrmsr()
302 ret = apic_msr_write(index, val); in helper_wrmsr()
316 || (val == 0 || val == ~(uint64_t)0)) { in helper_wrmsr()
317 env->mce_banks[offset] = val; in helper_wrmsr()
332 uint64_t val; in helper_rdmsr() local
338 val = env->sysenter_cs; in helper_rdmsr()
341 val = env->sysenter_esp; in helper_rdmsr()
344 val = env->sysenter_eip; in helper_rdmsr()
347 val = cpu_get_apic_base(env_archcpu(env)->apic_state); in helper_rdmsr()
350 val = env->efer; in helper_rdmsr()
353 val = env->star; in helper_rdmsr()
356 val = env->pat; in helper_rdmsr()
359 val = env->pkrs; in helper_rdmsr()
362 val = env->vm_hsave; in helper_rdmsr()
366 val = 1000ULL; in helper_rdmsr()
368 val |= (((uint64_t)4ULL) << 40); in helper_rdmsr()
372 val = env->lstar; in helper_rdmsr()
375 val = env->cstar; in helper_rdmsr()
378 val = env->fmask; in helper_rdmsr()
381 val = env->segs[R_FS].base; in helper_rdmsr()
384 val = env->segs[R_GS].base; in helper_rdmsr()
387 val = env->kernelgsbase; in helper_rdmsr()
390 val = env->tsc_aux; in helper_rdmsr()
394 val = env->msr_smi_count; in helper_rdmsr()
404 val = env->mtrr_var[((uint32_t)env->regs[R_ECX] - in helper_rdmsr()
415 val = env->mtrr_var[((uint32_t)env->regs[R_ECX] - in helper_rdmsr()
419 val = env->mtrr_fixed[0]; in helper_rdmsr()
423 val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - in helper_rdmsr()
434 val = env->mtrr_fixed[(uint32_t)env->regs[R_ECX] - in helper_rdmsr()
438 val = env->mtrr_deftype; in helper_rdmsr()
442 val = MSR_MTRRcap_VCNT | MSR_MTRRcap_FIXRANGE_SUPPORT | in helper_rdmsr()
446 val = 0; in helper_rdmsr()
450 val = env->mcg_cap; in helper_rdmsr()
454 val = env->mcg_ctl; in helper_rdmsr()
456 val = 0; in helper_rdmsr()
460 val = env->mcg_status; in helper_rdmsr()
463 val = env->msr_ia32_misc_enable; in helper_rdmsr()
466 val = env->msr_bndcfgs; in helper_rdmsr()
469 val = x86_cpu->ucode_rev; in helper_rdmsr()
472 val = cpu_x86_get_msr_core_thread_count(x86_cpu); in helper_rdmsr()
480 ret = apic_msr_read(index, &val); in helper_rdmsr()
493 val = env->mce_banks[offset]; in helper_rdmsr()
497 val = 0; in helper_rdmsr()
500 env->regs[R_EAX] = (uint32_t)(val); in helper_rdmsr()
501 env->regs[R_EDX] = (uint32_t)(val >> 32); in helper_rdmsr()