/openbmc/linux/Documentation/devicetree/bindings/arm/tegra/ |
H A D | nvidia,tegra20-pmc.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Tegra Power Management Controller (PMC) 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jonathan Hunter <jonathanh@nvidia.com> 16 - nvidia,tegra20-pmc 17 - nvidia,tegra30-pmc 18 - nvidia,tegra114-pmc [all …]
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H A D | nvidia,tegra186-pmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NVIDIA Tegra Power Management Controller (PMC) 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 16 - nvidia,tegra186-pmc 17 - nvidia,tegra194-pmc 18 - nvidia,tegra234-pmc [all …]
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/openbmc/u-boot/arch/arm/mach-tegra/ |
H A D | ap.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * (C) Copyright 2010-2015 7 /* Tegra AP (Application Processor) code */ 14 #include <asm/arch-tegra/ap.h> 15 #include <asm/arch-tegra/clock.h> 16 #include <asm/arch-tegra/fuse.h> 17 #include <asm/arch-tegra/pmc.h> 18 #include <asm/arch-tegra/scu.h> 19 #include <asm/arch-tegra/tegra.h> 20 #include <asm/arch-tegra/warmboot.h> [all …]
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H A D | cmd_enterrcm.c | 1 // SPDX-License-Identifier: GPL-2.0+ 8 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 12 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 20 * http://www.dave-tech.it 28 #include <asm/arch/tegra.h> 29 #include <asm/arch-tegra/pmc.h> 34 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in do_enterrcm() local 39 pmc->pmc_scratch0 = 2; in do_enterrcm() 48 "reset Tegra and enter USB Recovery Mode",
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H A D | board2.c | 1 // SPDX-License-Identifier: GPL-2.0+ 14 #include <asm/arch-tegra/ap.h> 15 #include <asm/arch-tegra/board.h> 16 #include <asm/arch-tegra/clk_rst.h> 17 #include <asm/arch-tegra/pmc.h> 18 #include <asm/arch-tegra/sys_proto.h> 19 #include <asm/arch-tegra/uart.h> 20 #include <asm/arch-tegra/warmboot.h> 21 #include <asm/arch-tegra/gpu.h> 22 #include <asm/arch-tegra/usb.h> [all …]
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H A D | cpu.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved. 11 #include <asm/arch/tegra.h> 12 #include <asm/arch-tegra/clk_rst.h> 13 #include <asm/arch-tegra/pmc.h> 14 #include <asm/arch-tegra/scu.h> 24 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; in get_num_cpus() 48 * ------------------------------ 66 * ------------------------------ 84 * ------------------------------ [all …]
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H A D | board.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * (C) Copyright 2010-2015 15 #include <asm/arch/tegra.h> 16 #include <asm/arch-tegra/ap.h> 17 #include <asm/arch-tegra/board.h> 18 #include <asm/arch-tegra/pmc.h> 19 #include <asm/arch-tegra/sys_proto.h> 20 #include <asm/arch-tegra/warmboot.h> 58 * This register reads 0xffffffff in non-secure mode. This register in tegra_cpu_is_non_secure() 61 * non-secure mode. in tegra_cpu_is_non_secure() [all …]
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/openbmc/u-boot/arch/arm/mach-tegra/tegra20/ |
H A D | warmboot_avp.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * (C) Copyright 2010 - 2011 12 #include <asm/arch/tegra.h> 13 #include <asm/arch-tegra/ap.h> 14 #include <asm/arch-tegra/apb_misc.h> 15 #include <asm/arch-tegra/clk_rst.h> 16 #include <asm/arch-tegra/pmc.h> 17 #include <asm/arch-tegra/warmboot.h> 26 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in wb_start() local 37 writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &apb_misc->cfg_ctl); in wb_start() [all …]
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H A D | cpu.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. 8 #include <asm/arch/tegra.h> 9 #include <asm/arch-tegra/pmc.h> 14 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in enable_cpu_power_rail() local 17 reg = readl(&pmc->pmc_cntrl); in enable_cpu_power_rail() 19 writel(reg, &pmc->pmc_cntrl); in enable_cpu_power_rail() 46 * if it's a non-zero value. in start_cpu()
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H A D | warmboot.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * (C) Copyright 2010 - 2011 15 #include <asm/arch/tegra.h> 16 #include <asm/arch-tegra/ap.h> 17 #include <asm/arch-tegra/apb_misc.h> 18 #include <asm/arch-tegra/clk_rst.h> 19 #include <asm/arch-tegra/pmc.h> 20 #include <asm/arch-tegra/fuse.h> 21 #include <asm/arch-tegra/warmboot.h> 127 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in warmboot_save_sdram_params() local [all …]
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/openbmc/u-boot/arch/arm/mach-tegra/tegra124/ |
H A D | cpu.c | 1 // SPDX-License-Identifier: GPL-2.0+ 13 #include <asm/arch/tegra.h> 14 #include <asm/arch-tegra/clk_rst.h> 15 #include <asm/arch-tegra/pmc.h> 16 #include <asm/arch-tegra/ap.h> 19 /* Tegra124-specific CPU init code */ 23 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in enable_cpu_power_rail() local 27 /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */ in enable_cpu_power_rail() 34 * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz), in enable_cpu_power_rail() 37 writel(0x7C830, &pmc->pmc_cpupwrgood_timer); in enable_cpu_power_rail() [all …]
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H A D | psci.c | 1 // SPDX-License-Identifier: GPL-2.0+ 12 #include <asm/arch-tegra/ap.h> 13 #include <asm/arch-tegra/pmc.h> 33 * - configure the Flow Controller in psci_board_init() 34 * - power up the CPUs in psci_board_init() 35 * - wait for the CPUs to hit wfi and be powered down again in psci_board_init() 46 writel((2 << CSR_WAIT_WFI_SHIFT) | CSR_ENABLE, &flow->cpu1_csr); in psci_board_init() 47 writel((4 << CSR_WAIT_WFI_SHIFT) | CSR_ENABLE, &flow->cpu2_csr); in psci_board_init() 48 writel((8 << CSR_WAIT_WFI_SHIFT) | CSR_ENABLE, &flow->cpu3_csr); in psci_board_init() 50 writel(EVENT_MODE_STOP, &flow->halt_cpu1_events); in psci_board_init() [all …]
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/openbmc/u-boot/arch/arm/mach-tegra/tegra30/ |
H A D | cpu.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. 10 #include <asm/arch/tegra.h> 11 #include <asm/arch-tegra/clk_rst.h> 12 #include <asm/arch-tegra/pmc.h> 13 #include <asm/arch-tegra/tegra_i2c.h> 16 /* Tegra30-specific CPU init code */ 21 writel(addr, ®->cmd_addr0); in tegra_i2c_ll_write_addr() 22 writel(config, ®->cnfg); in tegra_i2c_ll_write_addr() 29 writel(data, ®->cmd_data1); in tegra_i2c_ll_write_data() [all …]
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/openbmc/u-boot/arch/arm/mach-tegra/tegra114/ |
H A D | cpu.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * (C) Copyright 2010-2014 12 #include <asm/arch/tegra.h> 13 #include <asm/arch-tegra/clk_rst.h> 14 #include <asm/arch-tegra/pmc.h> 17 /* Tegra114-specific CPU init code */ 20 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in enable_cpu_power_rail() local 26 /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */ in enable_cpu_power_rail() 31 * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz), in enable_cpu_power_rail() 35 writel(reg, &pmc->pmc_cpupwrgood_timer); in enable_cpu_power_rail() [all …]
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/openbmc/linux/drivers/soc/tegra/ |
H A D | pmc.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * drivers/soc/tegra/pmc.c 6 * Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved. 12 #define pr_fmt(fmt) "tegra-pmc: " fmt 14 #include <linux/arm-smccc.h> 16 #include <linux/clk-provider.h> 18 #include <linux/clk/clk-conf.h> 19 #include <linux/clk/tegra.h> 37 #include <linux/pinctrl/pinconf-generic.h> 52 #include <soc/tegra/common.h> [all …]
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H A D | regulators-tegra30.c | 1 // SPDX-License-Identifier: GPL-2.0+ 4 * Copyright (C) 2019 GRATE-DRIVER project 7 * Copyright (C) 2010-2011 NVIDIA Corporation 10 #define pr_fmt(fmt) "tegra voltage-coupler: " fmt 21 #include <soc/tegra/fuse.h> 22 #include <soc/tegra/pmc.h> 43 static int tegra30_core_limit(struct tegra_regulator_coupler *tegra, in tegra30_core_limit() argument 52 * Tegra30 SoC has critical DVFS-capable devices that are in tegra30_core_limit() 53 * permanently-active or active at a boot time, like EMC in tegra30_core_limit() 59 * the state of all DVFS-critical CORE devices is synced. in tegra30_core_limit() [all …]
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/openbmc/linux/arch/arm/mach-tegra/ |
H A D | platsmp.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * linux/arch/arm/mach-tegra/platsmp.c 12 #include <linux/clk/tegra.h> 21 #include <soc/tegra/flowctrl.h> 22 #include <soc/tegra/fuse.h> 23 #include <soc/tegra/pmc.h> 26 #include <asm/mach-types.h> 50 * power-gated via the flow controller). This will have no in tegra20_boot_secondary() 58 * power-gate the CPU this will cause the flow controller to in tegra20_boot_secondary() 84 * power will be resumed automatically after un-halting the in tegra30_boot_secondary() [all …]
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H A D | tegra.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * NVIDIA Tegra SoC device tree board support 11 #include <linux/clk/tegra.h> 12 #include <linux/dma-mapping.h> 30 #include <soc/tegra/fuse.h> 31 #include <soc/tegra/pmc.h> 34 #include <asm/hardware/cache-l2x0.h> 37 #include <asm/mach-types.h> 49 * Storage for debug-macro.S's state. 52 * kernel is loaded. The data is declared here rather than debug-macro.S so [all …]
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/openbmc/linux/Documentation/devicetree/bindings/sound/ |
H A D | nvidia,tegra-audio-max9808x.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-max9808x.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NVIDIA Tegra audio complex with MAX9808x CODEC 10 - Jon Hunter <jonathanh@nvidia.com> 11 - Thierry Reding <thierry.reding@gmail.com> 14 - $ref: nvidia,tegra-audio-common.yaml# 19 - items: 20 - pattern: '^[a-z0-9]+,tegra-audio-max98088(-[a-z0-9]+)+$' [all …]
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H A D | nvidia,tegra-audio-rt5631.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-rt5631.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NVIDIA Tegra audio complex with RT5631 CODEC 10 - Jon Hunter <jonathanh@nvidia.com> 11 - Thierry Reding <thierry.reding@gmail.com> 14 - $ref: nvidia,tegra-audio-common.yaml# 19 - pattern: '^[a-z0-9]+,tegra-audio-rt5631(-[a-z0-9]+)+$' 20 - const: nvidia,tegra-audio-rt5631 [all …]
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/openbmc/linux/drivers/cpuidle/ |
H A D | cpuidle-tegra.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * CPU idle driver for Tegra CPUs 5 * Copyright (c) 2010-2013, NVIDIA Corporation. 15 #define pr_fmt(fmt) "tegra-cpuidle: " fmt 26 #include <linux/clk/tegra.h> 29 #include <soc/tegra/cpuidle.h> 30 #include <soc/tegra/flowctrl.h> 31 #include <soc/tegra/fuse.h> 32 #include <soc/tegra/irq.h> 33 #include <soc/tegra/pm.h> [all …]
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/openbmc/linux/drivers/gpu/drm/nouveau/include/nvif/ |
H A D | os.h | 1 /* SPDX-License-Identifier: MIT */ 15 #include <linux/i2c-algo-bit.h> 17 #include <linux/io-mapping.h> 35 #include <soc/tegra/fuse.h> 36 #include <soc/tegra/pmc.h>
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/openbmc/linux/drivers/clk/tegra/ |
H A D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 9 #include <linux/clk-provider.h> 59 * Tegra CLK_OUT_ENB registers have some undefined bits which are not used and 73 * struct tegra_clk_sync_source - external clock source from codec 75 * @hw: handle between common and hardware-specific interfaces 95 * struct tegra_clk_frac_div - fractional divider clock 97 * @hw: handle between common and hardware-specific interfaces 99 * @flags: hardware-specific flags 106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value. 107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this [all …]
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/openbmc/linux/arch/arm/boot/dts/nvidia/ |
H A D | tegra20-ventana.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/input.h> 5 #include <dt-bindings/thermal/thermal.h> 7 #include "tegra20-cpu-opp.dtsi" 8 #include "tegra20-cpu-opp-microvolt.dtsi" 21 stdout-path = "serial0:115200n8"; 40 vdd-supply = <&hdmi_vdd_reg>; 41 pll-supply = <&hdmi_pll_reg>; 43 nvidia,ddc-i2c-bus = <&hdmi_ddc>; [all …]
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H A D | tegra20-paz00.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/input/input.h> 5 #include <dt-bindings/thermal/thermal.h> 8 #include "tegra20-cpu-opp.dtsi" 9 #include "tegra20-cpu-opp-microvolt.dtsi" 25 stdout-path = "serial0:115200n8"; 44 vdd-supply = <&hdmi_vdd_reg>; 45 pll-supply = <&hdmi_pll_reg>; 47 nvidia,ddc-i2c-bus = <&hdmi_ddc>; [all …]
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