139faeba7SSowjanya Komatineni# SPDX-License-Identifier: GPL-2.0 239faeba7SSowjanya Komatineni%YAML 1.2 339faeba7SSowjanya Komatineni--- 439faeba7SSowjanya Komatineni$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml# 539faeba7SSowjanya Komatineni$schema: http://devicetree.org/meta-schemas/core.yaml# 639faeba7SSowjanya Komatineni 739faeba7SSowjanya Komatinenititle: Tegra Power Management Controller (PMC) 839faeba7SSowjanya Komatineni 939faeba7SSowjanya Komatinenimaintainers: 1039faeba7SSowjanya Komatineni - Thierry Reding <thierry.reding@gmail.com> 1139faeba7SSowjanya Komatineni - Jonathan Hunter <jonathanh@nvidia.com> 1239faeba7SSowjanya Komatineni 1339faeba7SSowjanya Komatineniproperties: 1439faeba7SSowjanya Komatineni compatible: 1539faeba7SSowjanya Komatineni enum: 1639faeba7SSowjanya Komatineni - nvidia,tegra20-pmc 1739faeba7SSowjanya Komatineni - nvidia,tegra30-pmc 1839faeba7SSowjanya Komatineni - nvidia,tegra114-pmc 1939faeba7SSowjanya Komatineni - nvidia,tegra124-pmc 2039faeba7SSowjanya Komatineni - nvidia,tegra210-pmc 2139faeba7SSowjanya Komatineni 2239faeba7SSowjanya Komatineni reg: 2339faeba7SSowjanya Komatineni maxItems: 1 2439faeba7SSowjanya Komatineni description: 2539faeba7SSowjanya Komatineni Offset and length of the register set for the device. 2639faeba7SSowjanya Komatineni 2739faeba7SSowjanya Komatineni clock-names: 2839faeba7SSowjanya Komatineni items: 2939faeba7SSowjanya Komatineni - const: pclk 3039faeba7SSowjanya Komatineni - const: clk32k_in 3139faeba7SSowjanya Komatineni description: 3239faeba7SSowjanya Komatineni Must includes entries pclk and clk32k_in. 3339faeba7SSowjanya Komatineni pclk is the Tegra clock of that name and clk32k_in is 32KHz clock 3439faeba7SSowjanya Komatineni input to Tegra. 3539faeba7SSowjanya Komatineni 3639faeba7SSowjanya Komatineni clocks: 3739faeba7SSowjanya Komatineni maxItems: 2 3839faeba7SSowjanya Komatineni description: 3939faeba7SSowjanya Komatineni Must contain an entry for each entry in clock-names. 4039faeba7SSowjanya Komatineni See ../clocks/clocks-bindings.txt for details. 4139faeba7SSowjanya Komatineni 42f85fa319SSowjanya Komatineni '#clock-cells': 43f85fa319SSowjanya Komatineni const: 1 44f85fa319SSowjanya Komatineni description: 45f85fa319SSowjanya Komatineni Tegra PMC has clk_out_1, clk_out_2, and clk_out_3. 46cd88f167SSowjanya Komatineni PMC also has blink control which allows 32Khz clock output to 47cd88f167SSowjanya Komatineni Tegra blink pad. 48f85fa319SSowjanya Komatineni Consumer of PMC clock should specify the desired clock by having 49f85fa319SSowjanya Komatineni the clock ID in its "clocks" phandle cell with pmc clock provider. 50f85fa319SSowjanya Komatineni See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC 51f85fa319SSowjanya Komatineni clock IDs. 52f85fa319SSowjanya Komatineni 5339faeba7SSowjanya Komatineni '#interrupt-cells': 5439faeba7SSowjanya Komatineni const: 2 5539faeba7SSowjanya Komatineni description: 5639faeba7SSowjanya Komatineni Specifies number of cells needed to encode an interrupt source. 5739faeba7SSowjanya Komatineni The value must be 2. 5839faeba7SSowjanya Komatineni 5939faeba7SSowjanya Komatineni interrupt-controller: true 6039faeba7SSowjanya Komatineni 6139faeba7SSowjanya Komatineni nvidia,invert-interrupt: 6239faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/flag 6339faeba7SSowjanya Komatineni description: Inverts the PMU interrupt signal. 6439faeba7SSowjanya Komatineni The PMU is an external Power Management Unit, whose interrupt output 6539faeba7SSowjanya Komatineni signal is fed into the PMC. This signal is optionally inverted, and 6639faeba7SSowjanya Komatineni then fed into the ARM GIC. The PMC is not involved in the detection 6739faeba7SSowjanya Komatineni or handling of this interrupt signal, merely its inversion. 6839faeba7SSowjanya Komatineni 6939faeba7SSowjanya Komatineni nvidia,core-power-req-active-high: 7039faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/flag 7139faeba7SSowjanya Komatineni description: Core power request active-high. 7239faeba7SSowjanya Komatineni 7339faeba7SSowjanya Komatineni nvidia,sys-clock-req-active-high: 7439faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/flag 7539faeba7SSowjanya Komatineni description: System clock request active-high. 7639faeba7SSowjanya Komatineni 7739faeba7SSowjanya Komatineni nvidia,combined-power-req: 7839faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/flag 7939faeba7SSowjanya Komatineni description: combined power request for CPU and Core. 8039faeba7SSowjanya Komatineni 8139faeba7SSowjanya Komatineni nvidia,cpu-pwr-good-en: 8239faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/flag 8339faeba7SSowjanya Komatineni description: 8439faeba7SSowjanya Komatineni CPU power good signal from external PMIC to PMC is enabled. 8539faeba7SSowjanya Komatineni 8639faeba7SSowjanya Komatineni nvidia,suspend-mode: 87086e9074SRob Herring $ref: /schemas/types.yaml#/definitions/uint32 88086e9074SRob Herring enum: [0, 1, 2] 8939faeba7SSowjanya Komatineni description: 9039faeba7SSowjanya Komatineni The suspend mode that the platform should use. 9139faeba7SSowjanya Komatineni Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh 9239faeba7SSowjanya Komatineni Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh 9339faeba7SSowjanya Komatineni Mode 2 is for LP2, CPU voltage off 9439faeba7SSowjanya Komatineni 9539faeba7SSowjanya Komatineni nvidia,cpu-pwr-good-time: 9639faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/uint32 9739faeba7SSowjanya Komatineni description: CPU power good time in uSec. 9839faeba7SSowjanya Komatineni 9939faeba7SSowjanya Komatineni nvidia,cpu-pwr-off-time: 10039faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/uint32 10139faeba7SSowjanya Komatineni description: CPU power off time in uSec. 10239faeba7SSowjanya Komatineni 10339faeba7SSowjanya Komatineni nvidia,core-pwr-good-time: 10439faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/uint32-array 10539faeba7SSowjanya Komatineni description: 10639faeba7SSowjanya Komatineni <Oscillator-stable-time Power-stable-time> 10739faeba7SSowjanya Komatineni Core power good time in uSec. 10839faeba7SSowjanya Komatineni 10939faeba7SSowjanya Komatineni nvidia,core-pwr-off-time: 11039faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/uint32 11139faeba7SSowjanya Komatineni description: Core power off time in uSec. 11239faeba7SSowjanya Komatineni 11339faeba7SSowjanya Komatineni nvidia,lp0-vec: 11439faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/uint32-array 11539faeba7SSowjanya Komatineni description: 11639faeba7SSowjanya Komatineni <start length> Starting address and length of LP0 vector. 11739faeba7SSowjanya Komatineni The LP0 vector contains the warm boot code that is executed 11839faeba7SSowjanya Komatineni by AVP when resuming from the LP0 state. 11939faeba7SSowjanya Komatineni The AVP (Audio-Video Processor) is an ARM7 processor and 12039faeba7SSowjanya Komatineni always being the first boot processor when chip is power on 12139faeba7SSowjanya Komatineni or resume from deep sleep mode. When the system is resumed 12239faeba7SSowjanya Komatineni from the deep sleep mode, the warm boot code will restore 12339faeba7SSowjanya Komatineni some PLLs, clocks and then brings up CPU0 for resuming the 12439faeba7SSowjanya Komatineni system. 12539faeba7SSowjanya Komatineni 12643e6f457SRob Herring core-supply: 12743e6f457SRob Herring description: 12843e6f457SRob Herring Phandle to voltage regulator connected to the SoC Core power rail. 12943e6f457SRob Herring 13043e6f457SRob Herring core-domain: 13143e6f457SRob Herring type: object 13243e6f457SRob Herring description: | 13343e6f457SRob Herring The vast majority of hardware blocks of Tegra SoC belong to a 13443e6f457SRob Herring Core power domain, which has a dedicated voltage rail that powers 13543e6f457SRob Herring the blocks. 13643e6f457SRob Herring 13743e6f457SRob Herring properties: 13843e6f457SRob Herring operating-points-v2: 13943e6f457SRob Herring description: 14043e6f457SRob Herring Should contain level, voltages and opp-supported-hw property. 14143e6f457SRob Herring The supported-hw is a bitfield indicating SoC speedo or process 14243e6f457SRob Herring ID mask. 14343e6f457SRob Herring 14443e6f457SRob Herring "#power-domain-cells": 14543e6f457SRob Herring const: 0 14643e6f457SRob Herring 14743e6f457SRob Herring required: 14843e6f457SRob Herring - operating-points-v2 14943e6f457SRob Herring - "#power-domain-cells" 15043e6f457SRob Herring 15143e6f457SRob Herring additionalProperties: false 15243e6f457SRob Herring 15339faeba7SSowjanya Komatineni i2c-thermtrip: 15439faeba7SSowjanya Komatineni type: object 15539faeba7SSowjanya Komatineni description: 15639faeba7SSowjanya Komatineni On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists, 15739faeba7SSowjanya Komatineni hardware-triggered thermal reset will be enabled. 15839faeba7SSowjanya Komatineni 15939faeba7SSowjanya Komatineni properties: 16039faeba7SSowjanya Komatineni nvidia,i2c-controller-id: 16139faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/uint32 16239faeba7SSowjanya Komatineni description: 16339faeba7SSowjanya Komatineni ID of I2C controller to send poweroff command to PMU. 16439faeba7SSowjanya Komatineni Valid values are described in section 9.2.148 16539faeba7SSowjanya Komatineni "APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference 16639faeba7SSowjanya Komatineni Manual. 16739faeba7SSowjanya Komatineni 16839faeba7SSowjanya Komatineni nvidia,bus-addr: 16939faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/uint32 17039faeba7SSowjanya Komatineni description: Bus address of the PMU on the I2C bus. 17139faeba7SSowjanya Komatineni 17239faeba7SSowjanya Komatineni nvidia,reg-addr: 17339faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/uint32 17439faeba7SSowjanya Komatineni description: PMU I2C register address to issue poweroff command. 17539faeba7SSowjanya Komatineni 17639faeba7SSowjanya Komatineni nvidia,reg-data: 17739faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/uint32 17839faeba7SSowjanya Komatineni description: Poweroff command to write to PMU. 17939faeba7SSowjanya Komatineni 18039faeba7SSowjanya Komatineni nvidia,pinmux-id: 18139faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/uint32 18239faeba7SSowjanya Komatineni description: 18339faeba7SSowjanya Komatineni Pinmux used by the hardware when issuing Poweroff command. 18439faeba7SSowjanya Komatineni Defaults to 0. Valid values are described in section 12.5.2 18539faeba7SSowjanya Komatineni "Pinmux Support" of the Tegra4 Technical Reference Manual. 18639faeba7SSowjanya Komatineni 18739faeba7SSowjanya Komatineni required: 18839faeba7SSowjanya Komatineni - nvidia,i2c-controller-id 18939faeba7SSowjanya Komatineni - nvidia,bus-addr 19039faeba7SSowjanya Komatineni - nvidia,reg-addr 19139faeba7SSowjanya Komatineni - nvidia,reg-data 19239faeba7SSowjanya Komatineni 19339faeba7SSowjanya Komatineni additionalProperties: false 19439faeba7SSowjanya Komatineni 19539faeba7SSowjanya Komatineni powergates: 19639faeba7SSowjanya Komatineni type: object 19739faeba7SSowjanya Komatineni description: | 19839faeba7SSowjanya Komatineni This node contains a hierarchy of power domain nodes, which should 19939faeba7SSowjanya Komatineni match the powergates on the Tegra SoC. Each powergate node 20039faeba7SSowjanya Komatineni represents a power-domain on the Tegra SoC that can be power-gated 20139faeba7SSowjanya Komatineni by the Tegra PMC. 20239faeba7SSowjanya Komatineni Hardware blocks belonging to a power domain should contain 20339faeba7SSowjanya Komatineni "power-domains" property that is a phandle pointing to corresponding 20439faeba7SSowjanya Komatineni powergate node. 20539faeba7SSowjanya Komatineni The name of the powergate node should be one of the below. Note that 20639faeba7SSowjanya Komatineni not every powergate is applicable to all Tegra devices and the following 20739faeba7SSowjanya Komatineni list shows which powergates are applicable to which devices. 20839faeba7SSowjanya Komatineni Please refer to Tegra TRM for mode details on the powergate nodes to 20939faeba7SSowjanya Komatineni use for each power-gate block inside Tegra. 21039faeba7SSowjanya Komatineni Name Description Devices Applicable 21139faeba7SSowjanya Komatineni 3d 3D Graphics Tegra20/114/124/210 21239faeba7SSowjanya Komatineni 3d0 3D Graphics 0 Tegra30 21339faeba7SSowjanya Komatineni 3d1 3D Graphics 1 Tegra30 21439faeba7SSowjanya Komatineni aud Audio Tegra210 21539faeba7SSowjanya Komatineni dfd Debug Tegra210 21639faeba7SSowjanya Komatineni dis Display A Tegra114/124/210 21739faeba7SSowjanya Komatineni disb Display B Tegra114/124/210 21839faeba7SSowjanya Komatineni heg 2D Graphics Tegra30/114/124/210 21939faeba7SSowjanya Komatineni iram Internal RAM Tegra124/210 22039faeba7SSowjanya Komatineni mpe MPEG Encode All 22139faeba7SSowjanya Komatineni nvdec NVIDIA Video Decode Engine Tegra210 22239faeba7SSowjanya Komatineni nvjpg NVIDIA JPEG Engine Tegra210 22339faeba7SSowjanya Komatineni pcie PCIE Tegra20/30/124/210 22439faeba7SSowjanya Komatineni sata SATA Tegra30/124/210 22539faeba7SSowjanya Komatineni sor Display interfaces Tegra124/210 22639faeba7SSowjanya Komatineni ve2 Video Encode Engine 2 Tegra210 22739faeba7SSowjanya Komatineni venc Video Encode Engine All 22839faeba7SSowjanya Komatineni vdec Video Decode Engine Tegra20/30/114/124 22939faeba7SSowjanya Komatineni vic Video Imaging Compositor Tegra124/210 23039faeba7SSowjanya Komatineni xusba USB Partition A Tegra114/124/210 23139faeba7SSowjanya Komatineni xusbb USB Partition B Tegra114/124/210 23239faeba7SSowjanya Komatineni xusbc USB Partition C Tegra114/124/210 23339faeba7SSowjanya Komatineni 23439faeba7SSowjanya Komatineni patternProperties: 23539faeba7SSowjanya Komatineni "^[a-z0-9]+$": 23639faeba7SSowjanya Komatineni type: object 237*e62fc182SRob Herring additionalProperties: false 23839faeba7SSowjanya Komatineni 239a8dd214fSRob Herring properties: 24039faeba7SSowjanya Komatineni clocks: 24139faeba7SSowjanya Komatineni minItems: 1 24239faeba7SSowjanya Komatineni maxItems: 8 24339faeba7SSowjanya Komatineni description: 24439faeba7SSowjanya Komatineni Must contain an entry for each clock required by the PMC 24539faeba7SSowjanya Komatineni for controlling a power-gate. 24639faeba7SSowjanya Komatineni See ../clocks/clock-bindings.txt document for more details. 24739faeba7SSowjanya Komatineni 24839faeba7SSowjanya Komatineni resets: 24939faeba7SSowjanya Komatineni minItems: 1 25039faeba7SSowjanya Komatineni maxItems: 8 25139faeba7SSowjanya Komatineni description: 25239faeba7SSowjanya Komatineni Must contain an entry for each reset required by the PMC 25339faeba7SSowjanya Komatineni for controlling a power-gate. 25439faeba7SSowjanya Komatineni See ../reset/reset.txt for more details. 25539faeba7SSowjanya Komatineni 256*e62fc182SRob Herring power-domains: 257*e62fc182SRob Herring maxItems: 1 258*e62fc182SRob Herring 25939faeba7SSowjanya Komatineni '#power-domain-cells': 26039faeba7SSowjanya Komatineni const: 0 26139faeba7SSowjanya Komatineni description: Must be 0. 26239faeba7SSowjanya Komatineni 26339faeba7SSowjanya Komatineni required: 26439faeba7SSowjanya Komatineni - clocks 26539faeba7SSowjanya Komatineni - resets 26639faeba7SSowjanya Komatineni - '#power-domain-cells' 26739faeba7SSowjanya Komatineni 26839faeba7SSowjanya Komatineni additionalProperties: false 26939faeba7SSowjanya Komatineni 27039faeba7SSowjanya KomatinenipatternProperties: 27139faeba7SSowjanya Komatineni "^[a-f0-9]+-[a-f0-9]+$": 27239faeba7SSowjanya Komatineni type: object 27339faeba7SSowjanya Komatineni description: 27439faeba7SSowjanya Komatineni This is a Pad configuration node. On Tegra SOCs a pad is a set of 27539faeba7SSowjanya Komatineni pins which are configured as a group. The pin grouping is a fixed 27639faeba7SSowjanya Komatineni attribute of the hardware. The PMC can be used to set pad power state 27739faeba7SSowjanya Komatineni and signaling voltage. A pad can be either in active or power down mode. 27839faeba7SSowjanya Komatineni The support for power state and signaling voltage configuration varies 27939faeba7SSowjanya Komatineni depending on the pad in question. 3.3V and 1.8V signaling voltages 28039faeba7SSowjanya Komatineni are supported on pins where software controllable signaling voltage 28139faeba7SSowjanya Komatineni switching is available. 28239faeba7SSowjanya Komatineni 28339faeba7SSowjanya Komatineni The pad configuration state nodes are placed under the pmc node and they 28439faeba7SSowjanya Komatineni are referred to by the pinctrl client properties. For more information 28539faeba7SSowjanya Komatineni see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt. 28639faeba7SSowjanya Komatineni The pad name should be used as the value of the pins property in pin 28739faeba7SSowjanya Komatineni configuration nodes. 28839faeba7SSowjanya Komatineni 28939faeba7SSowjanya Komatineni The following pads are present on Tegra124 and Tegra132 29039faeba7SSowjanya Komatineni audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic, 29139faeba7SSowjanya Komatineni hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl, 29239faeba7SSowjanya Komatineni sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias. 29339faeba7SSowjanya Komatineni 29439faeba7SSowjanya Komatineni The following pads are present on Tegra210 29539faeba7SSowjanya Komatineni audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg, 29639faeba7SSowjanya Komatineni debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi, 29739faeba7SSowjanya Komatineni hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1, 29839faeba7SSowjanya Komatineni sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias. 29939faeba7SSowjanya Komatineni 30039faeba7SSowjanya Komatineni properties: 30139faeba7SSowjanya Komatineni pins: 30239faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/string 30339faeba7SSowjanya Komatineni description: Must contain name of the pad(s) to be configured. 30439faeba7SSowjanya Komatineni 30539faeba7SSowjanya Komatineni low-power-enable: 30639faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/flag 30739faeba7SSowjanya Komatineni description: Configure the pad into power down mode. 30839faeba7SSowjanya Komatineni 30939faeba7SSowjanya Komatineni low-power-disable: 31039faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/flag 31139faeba7SSowjanya Komatineni description: Configure the pad into active mode. 31239faeba7SSowjanya Komatineni 31339faeba7SSowjanya Komatineni power-source: 31439faeba7SSowjanya Komatineni $ref: /schemas/types.yaml#/definitions/uint32 31539faeba7SSowjanya Komatineni description: 31639faeba7SSowjanya Komatineni Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or 31739faeba7SSowjanya Komatineni TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. 31839faeba7SSowjanya Komatineni The values are defined in 31939faeba7SSowjanya Komatineni include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h. 32039faeba7SSowjanya Komatineni Power state can be configured on all Tegra124 and Tegra132 32139faeba7SSowjanya Komatineni pads. None of the Tegra124 or Tegra132 pads support signaling 32239faeba7SSowjanya Komatineni voltage switching. 32339faeba7SSowjanya Komatineni All of the listed Tegra210 pads except pex-cntrl support power 32439faeba7SSowjanya Komatineni state configuration. Signaling voltage switching is supported 32539faeba7SSowjanya Komatineni on below Tegra210 pads. 32639faeba7SSowjanya Komatineni audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1, 32739faeba7SSowjanya Komatineni sdmmc3, spi, spi-hv, and uart. 32839faeba7SSowjanya Komatineni 32939faeba7SSowjanya Komatineni required: 33039faeba7SSowjanya Komatineni - pins 33139faeba7SSowjanya Komatineni 33239faeba7SSowjanya Komatineni additionalProperties: false 33339faeba7SSowjanya Komatineni 33439faeba7SSowjanya Komatinenirequired: 33539faeba7SSowjanya Komatineni - compatible 33639faeba7SSowjanya Komatineni - reg 33739faeba7SSowjanya Komatineni - clock-names 33839faeba7SSowjanya Komatineni - clocks 339f85fa319SSowjanya Komatineni - '#clock-cells' 34039faeba7SSowjanya Komatineni 3415be478f9SRob HerringadditionalProperties: false 3425be478f9SRob Herring 34339faeba7SSowjanya Komatinenidependencies: 34439faeba7SSowjanya Komatineni "nvidia,suspend-mode": ["nvidia,core-pwr-off-time", "nvidia,cpu-pwr-off-time"] 34539faeba7SSowjanya Komatineni "nvidia,core-pwr-off-time": ["nvidia,core-pwr-good-time"] 34639faeba7SSowjanya Komatineni "nvidia,cpu-pwr-off-time": ["nvidia,cpu-pwr-good-time"] 34739faeba7SSowjanya Komatineni 34839faeba7SSowjanya Komatineniexamples: 34939faeba7SSowjanya Komatineni - | 35039faeba7SSowjanya Komatineni 35139faeba7SSowjanya Komatineni #include <dt-bindings/clock/tegra210-car.h> 35239faeba7SSowjanya Komatineni #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 353f85fa319SSowjanya Komatineni #include <dt-bindings/soc/tegra-pmc.h> 35439faeba7SSowjanya Komatineni 35539faeba7SSowjanya Komatineni tegra_pmc: pmc@7000e400 { 35639faeba7SSowjanya Komatineni compatible = "nvidia,tegra210-pmc"; 357fba56184SRob Herring reg = <0x7000e400 0x400>; 3585f459cb0SDmitry Osipenko core-supply = <®ulator>; 35939faeba7SSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 36039faeba7SSowjanya Komatineni clock-names = "pclk", "clk32k_in"; 361f85fa319SSowjanya Komatineni #clock-cells = <1>; 36239faeba7SSowjanya Komatineni 36339faeba7SSowjanya Komatineni nvidia,invert-interrupt; 36439faeba7SSowjanya Komatineni nvidia,suspend-mode = <0>; 36539faeba7SSowjanya Komatineni nvidia,cpu-pwr-good-time = <0>; 36639faeba7SSowjanya Komatineni nvidia,cpu-pwr-off-time = <0>; 36739faeba7SSowjanya Komatineni nvidia,core-pwr-good-time = <4587 3876>; 36839faeba7SSowjanya Komatineni nvidia,core-pwr-off-time = <39065>; 36939faeba7SSowjanya Komatineni nvidia,core-power-req-active-high; 37039faeba7SSowjanya Komatineni nvidia,sys-clock-req-active-high; 37139faeba7SSowjanya Komatineni 3725f459cb0SDmitry Osipenko pd_core: core-domain { 3735f459cb0SDmitry Osipenko operating-points-v2 = <&core_opp_table>; 3745f459cb0SDmitry Osipenko #power-domain-cells = <0>; 3755f459cb0SDmitry Osipenko }; 3765f459cb0SDmitry Osipenko 37739faeba7SSowjanya Komatineni powergates { 37839faeba7SSowjanya Komatineni pd_audio: aud { 37939faeba7SSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_APE>, 38039faeba7SSowjanya Komatineni <&tegra_car TEGRA210_CLK_APB2APE>; 38139faeba7SSowjanya Komatineni resets = <&tegra_car 198>; 3825f459cb0SDmitry Osipenko power-domains = <&pd_core>; 38339faeba7SSowjanya Komatineni #power-domain-cells = <0>; 38439faeba7SSowjanya Komatineni }; 38539faeba7SSowjanya Komatineni 38639faeba7SSowjanya Komatineni pd_xusbss: xusba { 38739faeba7SSowjanya Komatineni clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 38839faeba7SSowjanya Komatineni resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 3895f459cb0SDmitry Osipenko power-domains = <&pd_core>; 39039faeba7SSowjanya Komatineni #power-domain-cells = <0>; 39139faeba7SSowjanya Komatineni }; 39239faeba7SSowjanya Komatineni }; 39339faeba7SSowjanya Komatineni }; 394