arm/tegra/nvidia%2Ctegra186-pmc.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Power Management Controller (PMC)
10   - Thierry Reding <thierry.reding@gmail.com>
11   - Jon Hunter <jonathanh@nvidia.com>
16       - nvidia,tegra186-pmc
17       - nvidia,tegra194-pmc
18       - nvidia,tegra234-pmc
24   reg-names:
27       - const: pmc
28       - const: wake
29       - const: aotag
30       - const: scratch
31       - const: misc
33   interrupt-controller: true
35   "#interrupt-cells":
40   nvidia,invert-interrupt:
48         const: nvidia,tegra186-pmc
54     reg-names:
61     reg-names:
65   "^[a-z0-9]+-[a-z0-9]+$":
70         These are pad configuration nodes. On Tegra SoCs a pad is a set of
72         attribute of the hardware. The PMC can be used to set pad power
80         which are placed under the pmc node and they are referred to by
83           Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
87           csia, csib, dsi, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
88           pex-clk1, usb0, usb1, usb2, usb-bias, uart, audio, hsic, dbg,
89           hdmi-dp0, hdmi-dp1, pex-cntrl, sdmmc2-hv, sdmmc4, cam, dsib,
90           dsic, dsid, csic, csid, csie, dsif, spi, ufs, dmic-hv, edp,
91           sdmmc1-hv, sdmmc3-hv, conn, audio-hv, ao-hv
95           csia, csib, mipi-bias, pex-clk-bias, pex-clk3, pex-clk2,
96           pex-clk1, eqos, pex-clk-2-bias, pex-clk-2, dap3, dap5, uart,
97           pwr-ctl, soc-gpio53, audio, gp-pwm2, gp-pwm3, soc-gpio12,
98           soc-gpio13, soc-gpio10, uart4, uart5, dbg, hdmi-dp3, hdmi-dp2,
99           hdmi-dp0, hdmi-dp1, pex-cntrl, pex-ctl2, pex-l0-rst,
100           pex-l1-rst, sdmmc4, pex-l5-rst, cam, csic, csid, csie, csif,
101           spi, ufs, csig, csih, edp, sdmmc1-hv, sdmmc3-hv, conn,
102           audio-hv, ao-hv
110         low-power-enable:
114         low-power-disable:
118         power-source:
127               include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h
130             except for ao-hv. Following pads have software configurable
131             signaling voltages: sdmmc2-hv, dmic-hv, sdmmc1-hv, sdmmc3-hv,
132             audio-hv, ao-hv.
137         - pins
142   - compatible
143   - reg
144   - reg-names
149   interrupt-controller: ['#interrupt-cells']
150   "#interrupt-cells":
152       - interrupt-controller
155   - |
156     #include <dt-bindings/clock/tegra186-clock.h>
157     #include <dt-bindings/interrupt-controller/arm-gic.h>
158     #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
159     #include <dt-bindings/memory/tegra186-mc.h>
160     #include <dt-bindings/reset/tegra186-reset.h>
162     pmc@c3600000 {
163         compatible = "nvidia,tegra186-pmc";
168         reg-names = "pmc", "wake", "aotag", "scratch";
169         nvidia,invert-interrupt;
171         sdmmc1_3v3: sdmmc1-3v3 {
172             pins = "sdmmc1-hv";
173             power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
176         sdmmc1_1v8: sdmmc1-1v8 {
177             pins = "sdmmc1-hv";
178             power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
183         compatible = "nvidia,tegra186-sdhci";
188         clock-names = "sdhci", "tmclk";
190         reset-names = "sdhci";
193         interconnect-names = "dma-mem", "write";
195         pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
196         pinctrl-0 = <&sdmmc1_3v3>;
197         pinctrl-1 = <&sdmmc1_1v8>;