arm/mach-tegra/cpu.c

1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (c) 2010-2015, NVIDIA CORPORATION.  All rights reserved.
11 #include <asm/arch/tegra.h>
12 #include <asm/arch-tegra/clk_rst.h>
13 #include <asm/arch-tegra/pmc.h>
14 #include <asm/arch-tegra/scu.h>
24 	rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
48 	 * ------------------------------
66 	 * ------------------------------
84 	 * ------------------------------
102 	 * ------------------------------
120 	 * ------------------------------
138 	 * ------------------------------
161 	reg = readl(&clkrst->crc_pllx_misc3);
163 	writel(reg, &clkrst->crc_pllx_misc3);
166 	      readl(&clkrst->crc_pllx_misc3));
179 	if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
187 	reg = PLL_BYPASS_MASK | (divm << pllinfo->m_shift);
188 	reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift);
189 	writel(reg, &pll->pll_base);
193 		reg = (cpcon << pllinfo->kcp_shift);
204 	writel(reg, &pll->pll_misc);
207 	reg = readl(&pll->pll_base);
209 	writel(reg, &pll->pll_base);
212 	/* Set lock_enable to PLLX_MISC if lock_ena is valid (i.e. 0-31) */
213 	reg = readl(&pll->pll_misc);
214 	if (pllinfo->lock_ena < 32)
215 		reg |= (1 << pllinfo->lock_ena);
216 	writel(reg, &pll->pll_misc);
220 	reg = readl(&pll->pll_base);
222 	writel(reg, &pll->pll_base);
231 	struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
255 	pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
279 		writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
280 		writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
287 	clk = readl(&clkrst->crc_clk_cpu_cmplx);
295 	writel(clk, &clkrst->crc_clk_cpu_cmplx);
302 	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
304 	return (readl(&pmc->pmc_pwrgate_status) & CPU_PWRED) ? 1 : 0;
309 	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
314 	reg = readl(&pmc->pmc_remove_clamping);
316 	writel(reg, &pmc->pmc_remove_clamping);
324 	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
330 		/* Toggle the CPU power state (OFF -> ON) */
331 		reg = readl(&pmc->pmc_pwrgate_toggle);
334 		writel(reg, &pmc->pmc_pwrgate_toggle);
338 			if (timeout-- == 0)