1 // SPDX-License-Identifier: GPL-2.0+
3  * (C) Copyright 2010 - 2011
12 #include <asm/arch/tegra.h>
13 #include <asm/arch-tegra/ap.h>
14 #include <asm/arch-tegra/apb_misc.h>
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <asm/arch-tegra/pmc.h>
17 #include <asm/arch-tegra/warmboot.h>
26 	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;  in wb_start()  local
37 	writel(CONFIG_CTL_TBE | CONFIG_CTL_JTAG, &apb_misc->cfg_ctl);  in wb_start()
55 	reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]);  in wb_start()
57 	writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]);  in wb_start()
60 	/* TODO: Set the drive strength - maybe make this a board parameter? */  in wb_start()
61 	osc_ctrl.word = readl(&clkrst->crc_osc_ctrl);  in wb_start()
64 	writel(osc_ctrl.word, &clkrst->crc_osc_ctrl);  in wb_start()
67 	if (!(readl(&pmc->pmc_pwrgate_status) & PWRGATE_STATUS_CPU)) {  in wb_start()
69 		writel(reg, &pmc->pmc_pwrgate_toggle);  in wb_start()
70 		while (!(readl(&pmc->pmc_pwrgate_status) & PWRGATE_STATUS_CPU))  in wb_start()
75 	reg = readl(&pmc->pmc_remove_clamping);  in wb_start()
77 	writel(reg, &pmc->pmc_remove_clamping);  in wb_start()
80 	writel(reg, &flow->halt_cop_events);  in wb_start()
83 	reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_L]);  in wb_start()
85 	writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_L]);  in wb_start()
90 	writel(reg, &clkrst->crc_cpu_cmplx_set);  in wb_start()
92 	/* Halt CPU1 at the flow controller for uni-processor configurations */  in wb_start()
93 	writel(EVENT_MODE_STOP, &flow->halt_cpu1_events);  in wb_start()
97 	 * address of the CPU-side restoration code.  in wb_start()
99 	reg = readl(&pmc->pmc_scratch41);  in wb_start()
103 	writel(CCLK_PLLP_BURST_POLICY, &clkrst->crc_cclk_brst_pol);  in wb_start()
108 	writel(reg, &clkrst->crc_clk_cpu_cmplx);  in wb_start()
111 	reg = readl(&clkrst->crc_clk_out_enb[TEGRA_DEV_L]);  in wb_start()
113 	writel(reg, &clkrst->crc_clk_out_enb[TEGRA_DEV_L]);  in wb_start()
122 	 * De-assert CoreSight reset.  in wb_start()
125 	 *	when the CPU-side restoration code runs.  in wb_start()
127 	reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]);  in wb_start()
129 	writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]);  in wb_start()
142 	writel(reg, &pmc->pmc_scratch1);  in wb_start()
146 	scratch3.word = readl(&pmc->pmc_scratch3);  in wb_start()
187 	writel(pllx_misc.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_misc);  in wb_start()
188 	writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);  in wb_start()
191 	writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);  in wb_start()
193 	writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);  in wb_start()
195 	writel(0, flow->halt_cpu_events);  in wb_start()
198 	writel(reg, &clkrst->crc_cpu_cmplx_clr);  in wb_start()
202 	writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out[0]);  in wb_start()
207 	writel(reg, &clkrst->crc_sclk_brst_pol);  in wb_start()
210 	reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_L]);  in wb_start()
212 	writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_L]);  in wb_start()
217 	writel(reg, flow->halt_cop_events);  in wb_start()
225 	writel(SWR_TRIG_SYS_RST, &clkrst->crc_rst_dev[TEGRA_DEV_L]);  in wb_start()