Lines Matching +full:tegra +full:- +full:pmc

1 // SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch-tegra/ap.h>
15 #include <asm/arch-tegra/board.h>
16 #include <asm/arch-tegra/clk_rst.h>
17 #include <asm/arch-tegra/pmc.h>
18 #include <asm/arch-tegra/sys_proto.h>
19 #include <asm/arch-tegra/uart.h>
20 #include <asm/arch-tegra/warmboot.h>
21 #include <asm/arch-tegra/gpu.h>
22 #include <asm/arch-tegra/usb.h>
23 #include <asm/arch-tegra/xusb-padctl.h>
28 #include <asm/arch/tegra.h>
65 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; in power_det_init() local
68 writel(0, &pmc->pmc_pwr_det_latch); in power_det_init()
69 writel(0, &pmc->pmc_pwr_det); in power_det_init()
75 return -1; in tegra_board_id()
84 if (board_id != -1) in checkboard()
125 /* Init is handled automatically in the driver-model case */ in board_init()
130 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); in board_init()
166 /* save Sdram params to PMC 2, 4, and 24 for WB0 */ in board_init()
191 writel(USBCMD_FS2, &usbctlr->usb_cmd); in board_early_init_f()
215 if (gd->bd->bi_dram[1].start) { in board_late_init()
218 * bank 1 is not mapped by the U-Boot MMU configuration, and so in board_late_init()
221 efi_add_memory_map(gd->bd->bi_dram[1].start, in board_late_init()
222 gd->bd->bi_dram[1].size >> EFI_PAGE_SHIFT, in board_late_init()
241 * In some SW environments, a memory carve-out exists to house a secure
245 * 32-bit physical address space.
247 * This function returns the total size of this carve-out. At present, the
248 * returned value is hard-coded for simplicity. In the future, it may be
249 * possible to determine the carve-out size:
250 * - By querying some run-time information source, such as:
251 * - A structure passed to U-Boot by earlier boot software.
252 * - SoC registers.
253 * - A call into the secure monitor.
254 * - In the per-board U-Boot configuration header, based on knowledge of the
255 * SW environment that U-Boot is being built for.
257 * For now, we support two configurations in U-Boot:
258 * - 32-bit ports without any form of carve-out.
259 * - 64 bit ports which are assumed to use a carve-out of a conservatively
260 * hard-coded size.
269 return (0 - CONFIG_ARMV7_SECURE_BASE) & ~(SZ_2M - 1); in carveout_size()
277 * carve-out that may be assigned.
286 * (a) 2GiB itself (RAM starts at 2GiB, and 4GiB - 2GiB == 2GiB). in usable_ram_size_below_4g()
289 if (gd->ram_size < SZ_2G) in usable_ram_size_below_4g()
290 total_size_below_4g = gd->ram_size; in usable_ram_size_below_4g()
294 /* Calculate usable RAM by subtracting out any carve-out size */ in usable_ram_size_below_4g()
295 usable_size_below_4g = total_size_below_4g - carveout_size(); in usable_ram_size_below_4g()
307 * - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg
309 * DT property is directly driven by the entries in the U-Boot bank array.
310 * - The potential existence of a carve-out at the end of RAM below 4GiB can
313 * Explicitly removing the carve-out RAM from the bank entries makes the RAM
314 * layout a bit more obvious, e.g. when running "bdinfo" at the U-Boot
315 * command-line.
317 * This does mean that the DT U-Boot passes to the Linux kernel will not
319 * all RAM in the U-Boot banks (and hence DT), and add a /memreserve/ node
321 * Linux kernel will ever need to access any RAM in* the carve-out via a CPU
324 * On 32-bit systems, we never define a bank for RAM above 4GiB, since the
325 * start address of that bank cannot be represented in the 32-bit .size
330 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; in dram_init_banksize()
331 gd->bd->bi_dram[0].size = usable_ram_size_below_4g(); in dram_init_banksize()
334 gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; in dram_init_banksize()
338 if (gd->ram_size > SZ_2G) { in dram_init_banksize()
339 gd->bd->bi_dram[1].start = 0x100000000; in dram_init_banksize()
340 gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; in dram_init_banksize()
344 gd->bd->bi_dram[1].start = 0; in dram_init_banksize()
345 gd->bd->bi_dram[1].size = 0; in dram_init_banksize()
352 * Most hardware on 64-bit Tegra is still restricted to DMA to the lower
353 * 32-bits of the physical address space. Cap the maximum usable RAM area
354 * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit
355 * boundary that most devices can address. Also, don't let U-Boot use any
356 * carve-out, as mentioned above.
359 * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size.