1 // SPDX-License-Identifier: GPL-2.0+
3  * (C) Copyright 2010-2014
12 #include <asm/arch/tegra.h>
13 #include <asm/arch-tegra/clk_rst.h>
14 #include <asm/arch-tegra/pmc.h>
17 /* Tegra114-specific CPU init code */
20 	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;  in enable_cpu_power_rail()  local
26 	/* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */  in enable_cpu_power_rail()
31 	 * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),  in enable_cpu_power_rail()
35 	writel(reg, &pmc->pmc_cpupwrgood_timer);  in enable_cpu_power_rail()
38 	clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);  in enable_cpu_power_rail()
39 	setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);  in enable_cpu_power_rail()
47 	clrbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 0xFFF);  in enable_cpu_power_rail()
48 	setbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 408);  in enable_cpu_power_rail()
59 	/* Wait for PLL-X to lock */  in enable_cpu_clocks()
61 		reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);  in enable_cpu_clocks()
62 	} while ((reg & (1 << pllinfo->lock_det)) == 0);  in enable_cpu_clocks()
67 	writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);  in enable_cpu_clocks()
68 	writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);  in enable_cpu_clocks()
82 	/* Take the slow non-CPU partition out of reset */  in remove_cpu_resets()
83 	reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);  in remove_cpu_resets()
84 	writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpulp_cmplx_clr);  in remove_cpu_resets()
86 	/* Take the fast non-CPU partition out of reset */  in remove_cpu_resets()
87 	reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);  in remove_cpu_resets()
88 	writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpug_cmplx_clr);  in remove_cpu_resets()
90 	/* Clear the SW-controlled reset of the slow cluster */  in remove_cpu_resets()
91 	reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);  in remove_cpu_resets()
93 	writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);  in remove_cpu_resets()
95 	/* Clear the SW-controlled reset of the fast cluster */  in remove_cpu_resets()
96 	reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);  in remove_cpu_resets()
101 	writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);  in remove_cpu_resets()
118 	clrbits_le32(&flow->cluster_control, 1);  in t114_init_clocks()
120 	writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);  in t114_init_clocks()
126 	writel(val, &clkrst->crc_clk_sys_rate);  in t114_init_clocks()
128 	/* Enable clocks to required peripherals. TBD - minimize this list */  in t114_init_clocks()
188 	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;  in is_partition_powered()  local
192 	reg = readl(&pmc->pmc_pwrgate_status);  in is_partition_powered()
198 	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;  in is_clamp_enabled()  local
202 	reg = readl(&pmc->pmc_clamp_status);  in is_clamp_enabled()
208 	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;  in power_partition()  local
213 		/* No, toggle the partition power state (OFF -> ON) */  in power_partition()
215 		writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);  in power_partition()
238 	/* Power up the fast cluster non-CPU partition */  in powerup_cpus()
268 	 * A01P with patched boot ROM; vector hard-coded to 0x4003fffc.  in start_cpu()
289 	/* b -12 */  in start_cpu()
290 	imme = (u32)-20;  in start_cpu()