Searched +full:stm32 +full:- +full:timer (Results 1 – 24 of 24) sorted by relevance
2 * Copyright (C) 2015, STMicroelectronics - All Rights Reserved3 * Author(s): Maxime Coquelin <mcoquelin.stm32@gmail.com> for STMicroelectronics.5 * This file is dual-licensed: you can use it either under the terms45 #include "armv7-m.dtsi"46 #include <dt-bindings/clock/stm32fx-clock.h>47 #include <dt-bindings/mfd/stm32f4-rcc.h>51 clk_hse: clk-hse {52 #clock-cells = <0>;53 compatible = "fixed-clock";54 clock-frequency = <0>;[all …]
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved6 #include <dt-bindings/interrupt-controller/arm-gic.h>7 #include <dt-bindings/clock/stm32mp1-clks.h>8 #include <dt-bindings/reset/stm32mp1-resets.h>11 #address-cells = <1>;12 #size-cells = <1>;15 #address-cells = <1>;16 #size-cells = <0>;19 compatible = "arm,cortex-a7";[all …]
2 * Copyright 2016 - Michael Kurz <michi.kurz@gmail.com>3 * Copyright 2016 - Vikas MANOCHA <vikas.manocha@st.com>7 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>9 * This file is dual-licensed: you can use it either under the terms48 #include "armv7-m.dtsi"49 #include <dt-bindings/pinctrl/stm32f746-pinfunc.h>50 #include <dt-bindings/clock/stm32fx-clock.h>51 #include <dt-bindings/mfd/stm32f7-rcc.h>55 clk_hse: clk-hse {56 #clock-cells = <0>;[all …]
2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>4 * This file is dual-licensed: you can use it either under the terms44 #include "armv7-m.dtsi"45 #include <dt-bindings/clock/stm32h7-clks.h>46 #include <dt-bindings/mfd/stm32h7-rcc.h>50 clk_hse: clk-hse {51 #clock-cells = <0>;52 compatible = "fixed-clock";53 clock-frequency = <25000000>;56 clk_lse: clk-lse {[all …]
2 * Copyright 2016 - Lee Jones <lee.jones@linaro.org>4 * This file is dual-licensed: you can use it either under the terms43 /dts-v1/;45 #include "stm32f469-pinctrl.dtsi"48 model = "STMicroelectronics STM32F469i-DISCO board";49 compatible = "st,stm32f469i-disco", "st,stm32f469";53 stdout-path = "serial0:115200n8";65 compatible = "regulator-fixed";66 regulator-name = "mmc_vcard";67 regulator-min-microvolt = <3300000>;[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * Copyright (C) 2015, STMicroelectronics - All Rights Reserved4 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> for STMicroelectronics.7 /dts-v1/;9 #include "stm32f429-pinctrl.dtsi"10 #include <dt-bindings/input/input.h>11 #include <dt-bindings/gpio/gpio.h>14 model = "STMicroelectronics STM32429i-EVAL board";15 compatible = "st,stm32429i-eval", "st,stm32f429";19 stdout-path = "serial0:115200n8";[all …]
1 if STM3217 select TIMER54 select TIMER73 select TIMER75 source "arch/arm/mach-stm32/stm32f4/Kconfig"76 source "arch/arm/mach-stm32/stm32f7/Kconfig"77 source "arch/arm/mach-stm32/stm32h7/Kconfig"
1 STMicroelectronics STM32 boards (``netduino2``, ``netduinoplus2``, ``olimex-stm32-h405``, ``stm32vl…4 The `STM32`_ chips are a family of 32-bit ARM-based microcontroller by7 .. _STM32: https://www.st.com/en/microcontrollers-microprocessors/stm32-32-bit-arm-cortex-mcus.html9 The STM32F1 series is based on ARM Cortex-M3 core. The following machines are12 - ``stm32vldiscovery`` STM32VLDISCOVERY board with STM32F100RBT6 microcontroller14 The STM32F2 series is based on ARM Cortex-M3 core. The following machines are17 - ``netduino2`` Netduino 2 board with STM32F205RFT6 microcontroller19 The STM32F4 series is based on ARM Cortex-M4F core, as well as the STM32L420 ultra-low-power series. The STM32F4 series is pin-to-pin compatible with STM32F2 series.21 The following machines are based on this ARM Cortex-M4F chip :[all …]
1 B-L475E-IOT01A IoT Node (``b-l475e-iot01a``)4 The B-L475E-IOT01A IoT Node uses the STM32L475VG SoC which is based on5 ARM Cortex-M4F core. It is part of STMicroelectronics6 :doc:`STM32 boards </system/arm/stm32>` and more specifically the STM32L47 ultra-low power series. The STM32L4x5 chip runs at up to 80 MHz and8 integrates 128 KiB of SRAM and up to 1MiB of Flash. The B-L475E-IOT01A board15 Currently B-L475E-IOT01A machines support the following devices:17 - Cortex-M4F based STM32L4x5 SoC18 - STM32L4x5 EXTI (Extended interrupts and events controller)19 - STM32L4x5 SYSCFG (System configuration controller)[all …]
6 Please refer to clock-bindings.txt for common clock controller binding usage.10 - compatible: Should be:11 "st,stm32h743-rcc"13 - reg: should be register base and length as documented in the16 - #reset-cells: 1, see below18 - #clock-cells : from common clock binding; shall be set to 120 - clocks: External oscillator clock phandle21 - high speed external clock signal (HSE)22 - low speed external clock signal (LSE)23 - external I2S clock (I2S_CKIN)[all …]
1 menu "Timer Support"3 config TIMER config4 bool "Enable driver model for timer drivers"7 Enable driver model for timer access. It uses the same API as8 lib/time.c, but now implemented by the uclass. The first timer9 will be used. The timer is usually a 32 bits free-running up10 counter. There may be no real tick, and no timer interrupt.13 bool "Enable driver model for timer drivers in SPL"14 depends on TIMER && SPL16 Enable support for timer drivers in SPL. These can be used to get[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved11 #include <timer.h>15 /* Timer control1 register */56 struct stm32_timer_regs *regs = priv->base; in stm32_timer_get_count()58 *count = readl(®s->cnt); in stm32_timer_get_count()75 return -EINVAL; in stm32_timer_probe()77 priv->base = (struct stm32_timer_regs *)addr; in stm32_timer_probe()89 regs = priv->base; in stm32_timer_probe()91 /* Stop the timer */ in stm32_timer_probe()[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * ARM Cortex M3/M4/M7 SysTick timer driver6 * Based on arch/arm/mach-stm32/stm32f1/timer.c13 * The SysTick timer is a 24-bit count down timer. The clock can be either the14 * CPU clock or a reference clock. Since the timer will wrap around very quickly15 * when using the CPU clock, and we do not handle the timer interrupts, it is29 /* SysTick Base Address - fixed for all Cortex M3, M4 and M7 devices */47 /* read the 24-bit timer */52 /* The timer counts down, therefore convert to an incrementing timer */ in read_timer()53 return TIMER_MAX_VAL - readl(&systick->current_val); in read_timer()[all …]
50 bool "Rockchip e-fuse support"53 Enable (read-only) access for the e-fuse block found in Rockchip55 or through child-nodes that are generated based on the e-fuse map74 Enable command-line access to the Chrome OS EC (Embedded76 a number of sub-commands for performing EC tasks such as112 keyboard (use the -l flag to enable the LCD), verified boot context,121 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface129 integrated 64-byte EEPROM, four programmable non-volatile I/O pins130 and a configurable timer for the supervisor function. The device is163 bool "Enable power-sequencing drivers"[all …]
14 bool "Generate position-independent pre-relocation code"16 U-Boot expects to be linked to a specific hard-coded address, and to20 information that is embedded into the binary to support U-Boot21 relocating itself to the top-of-RAM later during execution.28 U-Boot typically uses a hard-coded value for the stack pointer30 initial SP at run-time. This is useful to avoid hard-coding addresses31 into U-Boot, so that can be loaded and executed at arbitrary41 Place a Linux kernel image header at the start of the U-Boot binary.45 U-Boot needs to use, but which isn't part of the binary.74 Do not enable instruction cache in U-Boot[all …]
8 W: Web-page with status/info24 N: [^a-z]tegra all files whose path contains the word tegra52 -----------------------------------57 L: uboot-snps-arc@synopsys.com58 T: git git://git.denx.de/u-boot-arc.git65 L: uboot-snps-arc@synopsys.com66 F: drivers/clk/clk-hsdk-cgu.c67 F: include/dt-bindings/clock/snps,hsdk-cgu.h68 F: doc/device-tree-bindings/clock/snps,hsdk-cgu.txt73 L: uboot-snps-arc@synopsys.com[all …]
1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved11 #include <asm/arch/stm32.h>48 * - boot instance = bit 31:1649 * - boot device = bit 15:0125 /* Freeze IWDG2 if Cortex-A7 is in debug mode */ in dbgmcu_init()165 /* early armv7 timer init: needed for polling */ in arch_cpu_init()178 gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; in arch_cpu_init()190 /* Enable D-cache. I-cache is already enabled in start.S */ in enable_caches()249 int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1; in setup_boot_mode()[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved21 u32 btr1; /* SRAM/NOR-Flash Chip select timing register 1 */23 u32 btr2; /* SRAM/NOR-Flash Chip select timing register 2 */25 u32 btr3; /* SRAM/NOR-Flash Chip select timing register 3 */27 u32 btr4; /* SRAM/NOR-Flash Chip select timing register 4 */40 u32 bwtr1; /* SRAM/NOR-Flash write timing register 1 */42 u32 bwtr2; /* SRAM/NOR-Flash write timing register 2 */44 u32 bwtr3; /* SRAM/NOR-Flash write timing register 3 */46 u32 bwtr4; /* SRAM/NOR-Flash write timing register 4 */[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved48 #define SDMMC_DTIMER 0x24 /* SDMMC data timer */201 data_ctrl = (__ilog2(data->blocksize) << in stm32_sdmmc2_start_data()205 if (data->flags & MMC_DATA_READ) { in stm32_sdmmc2_start_data()207 idmabase0 = (u32)data->dest; in stm32_sdmmc2_start_data()209 idmabase0 = (u32)data->src; in stm32_sdmmc2_start_data()213 writel(SDMMC_CMD_TIMEOUT, priv->base + SDMMC_DTIMER); in stm32_sdmmc2_start_data()216 writel(ctx->data_length, priv->base + SDMMC_DLEN); in stm32_sdmmc2_start_data()219 writel(data_ctrl, priv->base + SDMMC_DCTRL); in stm32_sdmmc2_start_data()[all …]
1 // SPDX-License-Identifier: GPL-2.0+3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved8 #include <clk-uclass.h>13 #include <asm/arch/stm32.h>16 #include <dt-bindings/mfd/stm32f7-rcc.h>147 struct stm32_rcc_regs *regs = priv->base; in configure_clocks()148 struct stm32_pwr_regs *pwr = priv->pwr_regs; in configure_clocks()149 struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc; in configure_clocks()152 setbits_le32(®s->cr, RCC_CR_HSION); in configure_clocks()153 writel(0, ®s->cfgr); /* Reset CFGR */ in configure_clocks()[all …]
10 consult qemu-devel and not any specific individual privately.23 W: Web-page with status/info59 ------------------------------63 L: qemu-devel@nongnu.org72 R: Philippe Mathieu-Daudé <philmd@linaro.org>75 F: docs/devel/build-environment.rst76 F: docs/devel/code-of-conduct.rst78 F: docs/devel/conflict-resolution.rst80 F: docs/devel/submitting-a-patch.rst81 F: docs/devel/submitting-a-pull-request.rst[all …]
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1 2025-12-16 03:01:16.893-0600 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler2 2025-12-16 03:01:16.967-0600 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -[all...]
1 2025-12-15 03:01:05.452-0600 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler2 2025-12-15 03:01:05.518-0600 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -[all...]