Merge git://git.denx.de/u-boot-fsl-qoriq

Merge git://git.denx.de/u-boot-sunxi

Merge git://git.denx.de/u-boot-mmc

Merge git://git.denx.de/u-boot-uniphier

clk: clk_stm32f: Use PLLSAIP as USB 48MHz clock

On all STM32F4 and F7 SoCs family (except STM32F429), PLLSAI
output P can be used as 48MHz clock source for USB and SDMMC.

Signe

clk: clk_stm32f: Use PLLSAIP as USB 48MHz clock

On all STM32F4 and F7 SoCs family (except STM32F429), PLLSAI
output P can be used as 48MHz clock source for USB and SDMMC.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Tested By: Bruno Herrera <bruherrera@gmail.com>

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SPDX: Convert all of our single license tags to Linux Kernel style

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borro

SPDX: Convert all of our single license tags to Linux Kernel style

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>

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Merge git://git.denx.de/u-boot-imx

Signed-off-by: Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-spi

Merge git://git.denx.de/u-boot-sunxi

clk: clk_stm32f: Add DSI clock support

DSI clock is available on STM32F769-disco and
STM32F469-disco board.

Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
Signed-off-

clk: clk_stm32f: Add DSI clock support

DSI clock is available on STM32F769-disco and
STM32F469-disco board.

Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

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clk: clk_stm32f: Add set_rate for LTDC clock

Implement set_rate() for LTDC clock only, set_rate for other
clocks will be added if needed. This is needed by future LTDC driver
improve

clk: clk_stm32f: Add set_rate for LTDC clock

Implement set_rate() for LTDC clock only, set_rate for other
clocks will be added if needed. This is needed by future LTDC driver
improvements.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

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clk: clk_stm32f: Configure SAI PLL to generate LTDC pixel clock

Configure SAI PLL configuration to generate LTDC pixel clock on
the PLLSAIR output.

PLLSAI is enabled only if CON

clk: clk_stm32f: Configure SAI PLL to generate LTDC pixel clock

Configure SAI PLL configuration to generate LTDC pixel clock on
the PLLSAIR output.

PLLSAI is enabled only if CONFIG_VIDEO_STM32 flag is set.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

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clk: clk_stm32f: Rework SDMMC stm32_clk_get_rate() part

Rework the way SDMMC clock get rate is done in a more
generic way :

_ Add stm32_clk_get_pllsai_rate() which give the PLLS

clk: clk_stm32f: Rework SDMMC stm32_clk_get_rate() part

Rework the way SDMMC clock get rate is done in a more
generic way :

_ Add stm32_clk_get_pllsai_rate() which give the PLLSAI
indicated output rate.

_ Add stm32_clk_get_pllsai_vco_rate() which give the VCO
internal rate.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

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clk: clk_stm32f: No more need of 48Mhz from PLL_SAI

Initially, 48Mhz for SDIO clock was generated from SAI pll for
STM32F469 and STM32F746 SoCs, but this solution was not suitable
fo

clk: clk_stm32f: No more need of 48Mhz from PLL_SAI

Initially, 48Mhz for SDIO clock was generated from SAI pll for
STM32F469 and STM32F746 SoCs, but this solution was not suitable
for STM32F429 SoCs.

A generic solution is to used the PLL_Q output as 48Mhz clock
for all STM32F SOCs family.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

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clk: clk_stm32f: Fix RCC_PLLSAICFGR mask defines

Use the correct name for RCC_PLLSAICFGR_PLLSAIx_MASK masks.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

clk: clk_stm32f: Fix stm32_clk_get_rate()

Wrong parameter was passed to stm32_clk_pll48clk_rate().
sysclk (PLL_p output value) was passed instead of VCO value.

Signed-off-by: Pa

clk: clk_stm32f: Fix stm32_clk_get_rate()

Wrong parameter was passed to stm32_clk_pll48clk_rate().
sysclk (PLL_p output value) was passed instead of VCO value.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

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board: stm32: switch to DM STM32 timer

Use available DM stm32_timer driver instead of dedicated
mach-stm32/stm32fx/timer.c.

Remove all defines or files previously used for timer

board: stm32: switch to DM STM32 timer

Use available DM stm32_timer driver instead of dedicated
mach-stm32/stm32fx/timer.c.

Remove all defines or files previously used for timer usage in
arch/arm/include/asm/arch-stm32fx and in arch/arm/mach-stm32/stm32fx

Enable DM STM32_TIMER for STM32F4/F7 and H7.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

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clk: clk_stm32f: Fix stm32_clk_get_rate() for timer

For timer clock, an additionnal prescaler is used which was
not taken into account previously.

Signed-off-by: Patrice Chotard

clk: clk_stm32f: Fix stm32_clk_get_rate() for timer

For timer clock, an additionnal prescaler is used which was
not taken into account previously.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

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Merge git://git.denx.de/u-boot-fsl-qoriq

Merge tag 'xilinx-for-v2018.03' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2018.03

- Several Kconfig fixes (also moving configs to defconfigs)
- Some DTS updates

Merge tag 'xilinx-for-v2018.03' of git://git.denx.de/u-boot-microblaze

Xilinx changes for v2018.03

- Several Kconfig fixes (also moving configs to defconfigs)
- Some DTS updates
- ZynqMP psu rework based on Zynq concept
- Add low level initialization for zc770 and zcu102
- Add support for Zynq zc770 x16 nand configuration
- Add mini nand/emmc ZynqMP targets
- Some arasan nand changes

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clk: clk_stm32: Add .set_rate callback

Since 'commit f4fcba5c5baa ("clk: implement clk_set_defaults()")'
STM32F4 family board can't boot.

Above patch calls clk_set_rate() for al

clk: clk_stm32: Add .set_rate callback

Since 'commit f4fcba5c5baa ("clk: implement clk_set_defaults()")'
STM32F4 family board can't boot.

Above patch calls clk_set_rate() for all nodes with assigned-clock-rates
property. Clock driver for STM32F family doesn't implement .set_rate
callback which make clk_set_defaults() exit on error and prevent board
to boot.

Fixes: f4fcba5c5baa ("clk: implement clk_set_defaults()")
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

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Merge git://git.denx.de/u-boot-rockchip

clk: clk_stm32f: Fix PLLSAICFGR_PLLSAIP_4 divider value

PLLSAIP divider uses 2 bits (bits 16 and 17) into RCC_PLLSAICFGR
register, available combination are :
00: PLLSAIP = 2

clk: clk_stm32f: Fix PLLSAICFGR_PLLSAIP_4 divider value

PLLSAIP divider uses 2 bits (bits 16 and 17) into RCC_PLLSAICFGR
register, available combination are :
00: PLLSAIP = 2
01: PLLSAIP = 4
10: PLLSAIP = 6
11: PLLSAIP = 8

Previously, the divider value was incorrectly set to 6.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

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clk: clk_stm32f: Move SYSCFG clock setup into configure_clocks()

Move SYSCFG clock setup into configure_clocks() instead of calling
clock_setup() from board file.

As this clock

clk: clk_stm32f: Move SYSCFG clock setup into configure_clocks()

Move SYSCFG clock setup into configure_clocks() instead of calling
clock_setup() from board file.

As this clock is only needed in case of ethernet enabled and as
both stm32f4 and stm32f7 are using the Designware ethernet IP,
we use CONFIG_ETH_DESIGNWARE to only enable this clock if needed.

Move the RMII setup from board_early_init_f() to board_init()
to insure that RMII bit is set only when clock driver is initialized.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

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clk: clk_stm32f: Remove STMMAC clock setup

Thanks to 'commit ba1f96672522 ("net: designware: add clock support")'
we don't need anymore to setup the STMMAC clock in board.

Signe

clk: clk_stm32f: Remove STMMAC clock setup

Thanks to 'commit ba1f96672522 ("net: designware: add clock support")'
we don't need anymore to setup the STMMAC clock in board.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>

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