Revision tags: v00.04.15, v00.04.14, v00.04.13, v00.04.12, v00.04.11, v00.04.10, v00.04.09, v00.04.08, v00.04.07, v00.04.06, v00.04.05, v00.04.04, v00.04.03, v00.04.02, v00.04.01, v00.04.00, v2021.04, v00.03.03, v2021.01, v2020.10, v2020.07, v00.02.13, v2020.04, v2020.01, v2019.10, v00.02.05, v00.02.04, v00.02.03, v00.02.02, v00.02.01, v2019.07, v00.02.00, v2019.04 |
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328e3f8a |
| 21-Dec-2018 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-riscv
- Add DM drivers to support RISC-V CPU and timer, plus some bug fixes. - Support SiFive UART - Rename ax25-ae350 defconfig
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60262cd0 |
| 12-Dec-2018 |
Bin Meng <bmeng.cn@gmail.com> |
timer: Add generic driver for RISC-V privileged architecture defined timer
RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime.
timer: Add generic driver for RISC-V privileged architecture defined timer
RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems.
Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter.
With this timer driver the U-Boot timer functionalities like delay works correctly now.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
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e16c888f |
| 28-Nov-2018 |
Tom Rini <trini@konsulko.com> |
Merge branch '2018-11-28-master-imports'
- Add MediaTek support
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d3c3606c |
| 14-Nov-2018 |
Ryder Lee <ryder.lee@mediatek.com> |
timer: MediaTek: add timer driver for MediaTek SoCs
This patch adds clock source and clock event for the timer found on the Mediatek SoCs.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-b
timer: MediaTek: add timer driver for MediaTek SoCs
This patch adds clock source and clock event for the timer found on the Mediatek SoCs.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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1d6edcbf |
| 16-Nov-2018 |
Tom Rini <trini@konsulko.com> |
Merge tag 'pull-14nov18' of git://git.denx.de/u-boot-dm
- virtio implementation and supporting patches - DM_FLAG_PRE_RELOC fixes - regmap improvements - minor buildman and sandbox things
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73fe4111 |
| 11-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
timer: Sort Kconfig driver entries
This is currently out of order. Sort it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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c95c666d |
| 22-Oct-2018 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-x86
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6ce38364 |
| 13-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
x86: tsc: Introduce config option for early timer frequency
So far the TSC timer driver supports trying hardware calibration first and using device tree as last resort for its running frequency as t
x86: tsc: Introduce config option for early timer frequency
So far the TSC timer driver supports trying hardware calibration first and using device tree as last resort for its running frequency as the normal timer.
However when it is used as the early timer, it only supports hardware calibration and if it fails, the driver just panics. This introduces a new config option to specify the early timer frequency in MHz and it should be equal to the value described in the device tree.
Without this patch, the travis-ci testing on QEMU x86_64 target fails each time after it finishes the 'bootefi selftest' as the test.py see an error was emitted on the console like this:
TSC frequency is ZERO resetting ... ### ERROR ### Please RESET the board ###
It's strange that this error is consistently seen on the travis-ci machine, but only occasionally seen on my local machine (maybe 1 out of 10). Since QEMU x86_64 target enables BOOTSTAGE support which uses early timer, with this fix it should work without any failure.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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97d20f69 |
| 02-Sep-2018 |
Simon Glass <sjg@chromium.org> |
Enable CONFIG_TIMER_EARLY with bootstage
In initr_bootstage() we call bootstage_mark_name() which ends up calling timer_get_us(). This call happens before initr_dm(), which inits driver model.
On x
Enable CONFIG_TIMER_EARLY with bootstage
In initr_bootstage() we call bootstage_mark_name() which ends up calling timer_get_us(). This call happens before initr_dm(), which inits driver model.
On x86 we set gd->timer to NULL in the transition from board_init_f() to board_init_r(). See board_init_f_r() for this assignment. So U-Boot knows there is no timer available in the period immediately after relocation.
On x86 the timer_get_us() call is implemented as calls to get_ticks() and get_tbclk(). Both of these call dm_timer_init() to set up the timer, if gd->timer is NULL and the early timer is not available.
However dm_timer_init() cannot succeed before initr_dm() is called.
So it seems that on x86 if we want to use CONFIG_BOOTSTAGE we must enable CONFIG_TIMER_EARLY. Update the Kconfig to handle this.
Note: On most architectures we can rely on the pre-relocation memory still being available, so that gd->timer pointers to a valid timer device and everything works correctly. Admittedly this is not strictly correct since the timer device is set up by pre-relocation U-Boot, but normally this is fine. On x86 the 'CAR' (cache-as-RAM) memory used by pre-relocation U-Boot disappears in board_init_f_r() and any attempt to access it will hang. This is the reason why we must mark the timer as invalid when we get to board_init_f_r().
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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4e710ebb |
| 18-Sep-2018 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-dm
- MPC83xx device tree additions (CPU and RAM) - Fix sandbox build error - Sync bitrev with Linux - Various ofnode/DT improvements
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2c21749d |
| 06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Add MPC83xx timer driver
Add a timer driver for the MPC83xx architecture.
Signed-off-by: Mario Six <mario.six@gdsys.cc>
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a376702f |
| 24-Aug-2018 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
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66011a08 |
| 18-Aug-2018 |
Marek Vasut <marex@denx.de> |
timer: dw-apb: Add Designware APB timer driver
Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips.
Signed-off-by: Marek Vasut <marex@denx.de>
timer: dw-apb: Add Designware APB timer driver
Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
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Revision tags: v2018.07 |
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3b52847a |
| 11-May-2018 |
Tom Rini <trini@konsulko.com> |
Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze
Xilinx changes for v2018.07
microblaze: - Align defconfig
zynq: - Rework fpga initialization and cpuinfo handling
zynqmp
Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze
Xilinx changes for v2018.07
microblaze: - Align defconfig
zynq: - Rework fpga initialization and cpuinfo handling
zynqmp: - Add ZynqMP R5 support - Wire and enable watchdog on zcu100-revC - Setup MMU map for DDR at run time - Show board info based on DT and cleanup IDENT_STRING
zynqmp tools: - Add read partition support - Add initial support for Xilinx bif format for boot.bin generation
mmc: - Fix get_timer usage on 64bit cpus - Add support for SD3.0 UHS mode
nand-zynq: - Add support for 16bit buswidth - Use address cycles from onfi params
scsi: - convert ceva sata to UCLASS_AHCI
timer: - Add Cadence TTC for ZynqMP r5
watchdog: - Minor cadence driver cleanup
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72c37d12 |
| 17-Apr-2018 |
Michal Simek <michal.simek@xilinx.com> |
timer: Add Cadence TTC timer counter support
This driver was tested on Xilinx ZynqMP SoC.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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Revision tags: v2018.03 |
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5120a083 |
| 07-Feb-2018 |
Patrice Chotard <patrice.chotard@st.com> |
timer: stm32: Add timer support for STM32 SoCs family
This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 So
timer: stm32: Add timer support for STM32 SoCs family
This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
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Revision tags: v2018.01 |
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d36a27ad |
| 29-Nov-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-nds32
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0f4a395f |
| 22-Nov-2017 |
Rick Chen <rick@andestech.com> |
atcpit100: timer: Remove arch dependency.
ATCPIT100 is often used in AE3XX platform which is based on NDS32 architecture recently. But in the future Andestech will have AE250 platform which is embed
atcpit100: timer: Remove arch dependency.
ATCPIT100 is often used in AE3XX platform which is based on NDS32 architecture recently. But in the future Andestech will have AE250 platform which is embeded ATCPIT100 timer based on RISCV architecture.
Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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fa3e354b |
| 27-Nov-2017 |
Rick Chen <rickchen36@gmail.com> |
ae3xx: timer: Rename AE3XX to ATCPIT100
ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence.
Signed-off-by: rick <rick@a
ae3xx: timer: Rename AE3XX to ATCPIT100
ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence.
Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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Revision tags: v2017.11 |
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47edaea4 |
| 15-Aug-2017 |
Wenyou.Yang@microchip.com <Wenyou.Yang@microchip.com> |
driver: timer: Add the Atmel PIT timer driver
Add the new Atmel PIT timer driver, which supports the driver model and device tree.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
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c1b62ba9 |
| 14-Aug-2017 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-rockchip
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1168d2dd |
| 28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: timer: add device-model timer driver for RK3368 (and similar)
This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such a
rockchip: timer: add device-model timer driver for RK3368 (and similar)
This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers.
This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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e9e5d9d2 |
| 28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
dm: timer: normalise SPL and TPL support
To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing
dm: timer: normalise SPL and TPL support
To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in
This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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07d77838 |
| 01-Aug-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-x86
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0ce9c576 |
| 30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: kconfig: Select TIMER and X86_TSC_TIMER
Without a timer, U-Boot just doesn't boot. This is not something we can turn off.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevche
x86: kconfig: Select TIMER and X86_TSC_TIMER
Without a timer, U-Boot just doesn't boot. This is not something we can turn off.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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