Lines Matching +full:stm32 +full:- +full:timer
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
48 #define SDMMC_DTIMER 0x24 /* SDMMC data timer */
201 data_ctrl = (__ilog2(data->blocksize) << in stm32_sdmmc2_start_data()
205 if (data->flags & MMC_DATA_READ) { in stm32_sdmmc2_start_data()
207 idmabase0 = (u32)data->dest; in stm32_sdmmc2_start_data()
209 idmabase0 = (u32)data->src; in stm32_sdmmc2_start_data()
213 writel(SDMMC_CMD_TIMEOUT, priv->base + SDMMC_DTIMER); in stm32_sdmmc2_start_data()
216 writel(ctx->data_length, priv->base + SDMMC_DLEN); in stm32_sdmmc2_start_data()
219 writel(data_ctrl, priv->base + SDMMC_DCTRL); in stm32_sdmmc2_start_data()
222 ctx->cache_start = rounddown(idmabase0, ARCH_DMA_MINALIGN); in stm32_sdmmc2_start_data()
223 ctx->cache_end = roundup(idmabase0 + ctx->data_length, in stm32_sdmmc2_start_data()
229 * Avoid issue on buffer not cached-aligned in stm32_sdmmc2_start_data()
231 flush_dcache_range(ctx->cache_start, ctx->cache_end); in stm32_sdmmc2_start_data()
234 writel(idmabase0, priv->base + SDMMC_IDMABASE0); in stm32_sdmmc2_start_data()
235 writel(SDMMC_IDMACTRL_IDMAEN, priv->base + SDMMC_IDMACTRL); in stm32_sdmmc2_start_data()
241 if (readl(priv->base + SDMMC_CMD) & SDMMC_CMD_CPSMEN) in stm32_sdmmc2_start_cmd()
242 writel(0, priv->base + SDMMC_CMD); in stm32_sdmmc2_start_cmd()
244 cmd_param |= cmd->cmdidx | SDMMC_CMD_CPSMEN; in stm32_sdmmc2_start_cmd()
245 if (cmd->resp_type & MMC_RSP_PRESENT) { in stm32_sdmmc2_start_cmd()
246 if (cmd->resp_type & MMC_RSP_136) in stm32_sdmmc2_start_cmd()
248 else if (cmd->resp_type & MMC_RSP_CRC) in stm32_sdmmc2_start_cmd()
255 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR); in stm32_sdmmc2_start_cmd()
258 writel(cmd->cmdarg, priv->base + SDMMC_ARG); in stm32_sdmmc2_start_cmd()
261 writel(cmd_param, priv->base + SDMMC_CMD); in stm32_sdmmc2_start_cmd()
272 if (cmd->resp_type & MMC_RSP_PRESENT) { in stm32_sdmmc2_end_cmd()
274 if (cmd->resp_type & MMC_RSP_CRC) in stm32_sdmmc2_end_cmd()
281 ret = readl_poll_timeout(priv->base + SDMMC_STA, status, status & mask, in stm32_sdmmc2_end_cmd()
286 ctx->dpsm_abort = true; in stm32_sdmmc2_end_cmd()
293 __func__, status, cmd->cmdidx); in stm32_sdmmc2_end_cmd()
294 ctx->dpsm_abort = true; in stm32_sdmmc2_end_cmd()
295 return -ETIMEDOUT; in stm32_sdmmc2_end_cmd()
298 if (status & SDMMC_STA_CCRCFAIL && cmd->resp_type & MMC_RSP_CRC) { in stm32_sdmmc2_end_cmd()
300 __func__, status, cmd->cmdidx); in stm32_sdmmc2_end_cmd()
301 ctx->dpsm_abort = true; in stm32_sdmmc2_end_cmd()
302 return -EILSEQ; in stm32_sdmmc2_end_cmd()
305 if (status & SDMMC_STA_CMDREND && cmd->resp_type & MMC_RSP_PRESENT) { in stm32_sdmmc2_end_cmd()
306 cmd->response[0] = readl(priv->base + SDMMC_RESP1); in stm32_sdmmc2_end_cmd()
307 if (cmd->resp_type & MMC_RSP_136) { in stm32_sdmmc2_end_cmd()
308 cmd->response[1] = readl(priv->base + SDMMC_RESP2); in stm32_sdmmc2_end_cmd()
309 cmd->response[2] = readl(priv->base + SDMMC_RESP3); in stm32_sdmmc2_end_cmd()
310 cmd->response[3] = readl(priv->base + SDMMC_RESP4); in stm32_sdmmc2_end_cmd()
326 if (data->flags & MMC_DATA_READ) in stm32_sdmmc2_end_data()
331 status = readl(priv->base + SDMMC_STA); in stm32_sdmmc2_end_data()
333 status = readl(priv->base + SDMMC_STA); in stm32_sdmmc2_end_data()
337 * cache-refill during the DMA operations (pre-fetching) in stm32_sdmmc2_end_data()
339 if (data->flags & MMC_DATA_READ) in stm32_sdmmc2_end_data()
340 invalidate_dcache_range(ctx->cache_start, ctx->cache_end); in stm32_sdmmc2_end_data()
344 __func__, status, cmd->cmdidx); in stm32_sdmmc2_end_data()
345 if (readl(priv->base + SDMMC_DCOUNT)) in stm32_sdmmc2_end_data()
346 ctx->dpsm_abort = true; in stm32_sdmmc2_end_data()
347 return -EILSEQ; in stm32_sdmmc2_end_data()
352 __func__, status, cmd->cmdidx); in stm32_sdmmc2_end_data()
353 ctx->dpsm_abort = true; in stm32_sdmmc2_end_data()
354 return -ETIMEDOUT; in stm32_sdmmc2_end_data()
359 __func__, status, cmd->cmdidx); in stm32_sdmmc2_end_data()
360 ctx->dpsm_abort = true; in stm32_sdmmc2_end_data()
361 return -EIO; in stm32_sdmmc2_end_data()
366 __func__, status, cmd->cmdidx); in stm32_sdmmc2_end_data()
367 ctx->dpsm_abort = true; in stm32_sdmmc2_end_data()
368 return -EIO; in stm32_sdmmc2_end_data()
373 __func__, status, cmd->cmdidx); in stm32_sdmmc2_end_data()
374 ctx->dpsm_abort = true; in stm32_sdmmc2_end_data()
375 return -EIO; in stm32_sdmmc2_end_data()
394 ctx.data_length = data->blocks * data->blocksize; in stm32_sdmmc2_send_cmd()
401 __func__, cmd->cmdidx, in stm32_sdmmc2_send_cmd()
410 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR); in stm32_sdmmc2_send_cmd()
412 writel(0x0, priv->base + SDMMC_IDMACTRL); in stm32_sdmmc2_send_cmd()
418 if (ctx.dpsm_abort && (cmd->cmdidx != MMC_CMD_STOP_TRANSMISSION)) { in stm32_sdmmc2_send_cmd()
431 writel(SDMMC_ICR_STATIC_FLAGS, priv->base + SDMMC_ICR); in stm32_sdmmc2_send_cmd()
434 if ((ret != -ETIMEDOUT) && (ret != 0) && retry) { in stm32_sdmmc2_send_cmd()
436 __func__, cmd->cmdidx); in stm32_sdmmc2_send_cmd()
437 retry--; in stm32_sdmmc2_send_cmd()
441 debug("%s: end for CMD %d, ret = %d\n", __func__, cmd->cmdidx, ret); in stm32_sdmmc2_send_cmd()
454 reset_assert(&priv->reset_ctl); in stm32_sdmmc2_reset()
456 reset_deassert(&priv->reset_ctl); in stm32_sdmmc2_reset()
459 writel(priv->pwr_reg_msk, priv->base + SDMMC_POWER); in stm32_sdmmc2_reset()
463 * Set the SDMMC in power-cycle state.
470 if ((readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK) == in stm32_sdmmc2_pwrcycle()
475 writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk, in stm32_sdmmc2_pwrcycle()
476 priv->base + SDMMC_POWER); in stm32_sdmmc2_pwrcycle()
480 * set the SDMMC state Power-on: the card is clocked
482 * Reset => Power-Cycle => Power-Off => Power
488 readl(priv->base + SDMMC_POWER) & SDMMC_POWER_PWRCTRL_MASK; in stm32_sdmmc2_pwron()
493 /* warning: same PWRCTRL value after reset and for power-off state in stm32_sdmmc2_pwron()
497 writel(SDMMC_POWER_PWRCTRL_CYCLE | priv->pwr_reg_msk, in stm32_sdmmc2_pwron()
498 priv->base + SDMMC_POWER); in stm32_sdmmc2_pwron()
503 * switch to Power-Off state: SDMCC disable, signals drive 1 in stm32_sdmmc2_pwron()
505 writel(SDMMC_POWER_PWRCTRL_OFF | priv->pwr_reg_msk, in stm32_sdmmc2_pwron()
506 priv->base + SDMMC_POWER); in stm32_sdmmc2_pwron()
508 /* After the 1ms delay set the SDMMC to power-on */ in stm32_sdmmc2_pwron()
510 writel(SDMMC_POWER_PWRCTRL_ON | priv->pwr_reg_msk, in stm32_sdmmc2_pwron()
511 priv->base + SDMMC_POWER); in stm32_sdmmc2_pwron()
521 u32 desired = mmc->clock; in stm32_sdmmc2_set_ios()
522 u32 sys_clock = clk_get_rate(&priv->clk); in stm32_sdmmc2_set_ios()
526 mmc->bus_width, mmc->clock); in stm32_sdmmc2_set_ios()
528 if (mmc->clk_disable) in stm32_sdmmc2_set_ios()
541 IS_RISING_EDGE(priv->clk_reg_msk))) { in stm32_sdmmc2_set_ios()
547 if (mmc->bus_width == 4) in stm32_sdmmc2_set_ios()
549 if (mmc->bus_width == 8) in stm32_sdmmc2_set_ios()
552 writel(clk | priv->clk_reg_msk | SDMMC_CLKCR_HWFC_EN, in stm32_sdmmc2_set_ios()
553 priv->base + SDMMC_CLKCR); in stm32_sdmmc2_set_ios()
564 if (dm_gpio_is_valid(&priv->cd_gpio)) in stm32_sdmmc2_getcd()
565 return dm_gpio_get_value(&priv->cd_gpio); in stm32_sdmmc2_getcd()
581 struct mmc_config *cfg = &plat->cfg; in stm32_sdmmc2_probe()
584 priv->base = dev_read_addr(dev); in stm32_sdmmc2_probe()
585 if (priv->base == FDT_ADDR_T_NONE) in stm32_sdmmc2_probe()
586 return -EINVAL; in stm32_sdmmc2_probe()
589 priv->clk_reg_msk |= SDMMC_CLKCR_NEGEDGE; in stm32_sdmmc2_probe()
591 priv->pwr_reg_msk |= SDMMC_POWER_DIRPOL; in stm32_sdmmc2_probe()
592 if (dev_read_bool(dev, "st,pin-ckin")) in stm32_sdmmc2_probe()
593 priv->clk_reg_msk |= SDMMC_CLKCR_SELCLKRX_CKIN; in stm32_sdmmc2_probe()
595 ret = clk_get_by_index(dev, 0, &priv->clk); in stm32_sdmmc2_probe()
599 ret = clk_enable(&priv->clk); in stm32_sdmmc2_probe()
603 ret = reset_get_by_index(dev, 0, &priv->reset_ctl); in stm32_sdmmc2_probe()
607 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, in stm32_sdmmc2_probe()
610 cfg->f_min = 400000; in stm32_sdmmc2_probe()
611 cfg->f_max = dev_read_u32_default(dev, "max-frequency", 52000000); in stm32_sdmmc2_probe()
612 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; in stm32_sdmmc2_probe()
613 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; in stm32_sdmmc2_probe()
614 cfg->name = "STM32 SDMMC2"; in stm32_sdmmc2_probe()
616 cfg->host_caps = 0; in stm32_sdmmc2_probe()
617 if (cfg->f_max > 25000000) in stm32_sdmmc2_probe()
618 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; in stm32_sdmmc2_probe()
620 switch (dev_read_u32_default(dev, "bus-width", 1)) { in stm32_sdmmc2_probe()
622 cfg->host_caps |= MMC_MODE_8BIT; in stm32_sdmmc2_probe()
624 cfg->host_caps |= MMC_MODE_4BIT; in stm32_sdmmc2_probe()
629 pr_err("invalid \"bus-width\" property, force to 1\n"); in stm32_sdmmc2_probe()
632 upriv->mmc = &plat->mmc; in stm32_sdmmc2_probe()
639 clk_disable(&priv->clk); in stm32_sdmmc2_probe()
641 clk_free(&priv->clk); in stm32_sdmmc2_probe()
650 return mmc_bind(dev, &plat->mmc, &plat->cfg); in stm32_sdmmc_bind()
654 { .compatible = "st,stm32-sdmmc2" },