1*4c3aebd5SPatrice ChotardSTMicroelectronics STM32H7 Reset and Clock Controller 2*4c3aebd5SPatrice Chotard===================================================== 3*4c3aebd5SPatrice Chotard 4*4c3aebd5SPatrice ChotardThe RCC IP is both a reset and a clock controller. 5*4c3aebd5SPatrice Chotard 6*4c3aebd5SPatrice ChotardPlease refer to clock-bindings.txt for common clock controller binding usage. 7*4c3aebd5SPatrice ChotardPlease also refer to reset.txt for common reset controller binding usage. 8*4c3aebd5SPatrice Chotard 9*4c3aebd5SPatrice ChotardRequired properties: 10*4c3aebd5SPatrice Chotard- compatible: Should be: 11*4c3aebd5SPatrice Chotard "st,stm32h743-rcc" 12*4c3aebd5SPatrice Chotard 13*4c3aebd5SPatrice Chotard- reg: should be register base and length as documented in the 14*4c3aebd5SPatrice Chotard datasheet 15*4c3aebd5SPatrice Chotard 16*4c3aebd5SPatrice Chotard- #reset-cells: 1, see below 17*4c3aebd5SPatrice Chotard 18*4c3aebd5SPatrice Chotard- #clock-cells : from common clock binding; shall be set to 1 19*4c3aebd5SPatrice Chotard 20*4c3aebd5SPatrice Chotard- clocks: External oscillator clock phandle 21*4c3aebd5SPatrice Chotard - high speed external clock signal (HSE) 22*4c3aebd5SPatrice Chotard - low speed external clock signal (LSE) 23*4c3aebd5SPatrice Chotard - external I2S clock (I2S_CKIN) 24*4c3aebd5SPatrice Chotard 25*4c3aebd5SPatrice Chotard- st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain 26*4c3aebd5SPatrice Chotard write protection (RTC clock). 27*4c3aebd5SPatrice Chotard 28*4c3aebd5SPatrice Chotard- pll x node: Allow to register a pll with specific parameters. 29*4c3aebd5SPatrice Chotard Please see PLL section below. 30*4c3aebd5SPatrice Chotard 31*4c3aebd5SPatrice ChotardExample: 32*4c3aebd5SPatrice Chotard 33*4c3aebd5SPatrice Chotard rcc: rcc@58024400 { 34*4c3aebd5SPatrice Chotard #reset-cells = <1>; 35*4c3aebd5SPatrice Chotard #clock-cells = <2> 36*4c3aebd5SPatrice Chotard compatible = "st,stm32h743-rcc", "st,stm32-rcc"; 37*4c3aebd5SPatrice Chotard reg = <0x58024400 0x400>; 38*4c3aebd5SPatrice Chotard clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s_ckin>; 39*4c3aebd5SPatrice Chotard 40*4c3aebd5SPatrice Chotard st,syscfg = <&pwrcfg>; 41*4c3aebd5SPatrice Chotard 42*4c3aebd5SPatrice Chotard #address-cells = <1>; 43*4c3aebd5SPatrice Chotard #size-cells = <0>; 44*4c3aebd5SPatrice Chotard 45*4c3aebd5SPatrice Chotard vco1@58024430 { 46*4c3aebd5SPatrice Chotard #clock-cells = <0>; 47*4c3aebd5SPatrice Chotard compatible = "stm32,pll"; 48*4c3aebd5SPatrice Chotard reg = <0>; 49*4c3aebd5SPatrice Chotard }; 50*4c3aebd5SPatrice Chotard 51*4c3aebd5SPatrice Chotard vco2@58024438 { 52*4c3aebd5SPatrice Chotard #clock-cells = <0>; 53*4c3aebd5SPatrice Chotard compatible = "stm32,pll"; 54*4c3aebd5SPatrice Chotard reg = <1>; 55*4c3aebd5SPatrice Chotard st,clock-div = <2>; 56*4c3aebd5SPatrice Chotard st,clock-mult = <40>; 57*4c3aebd5SPatrice Chotard st,frac-status = <0>; 58*4c3aebd5SPatrice Chotard st,frac = <0>; 59*4c3aebd5SPatrice Chotard st,vcosel = <1>; 60*4c3aebd5SPatrice Chotard st,pllrge = <2>; 61*4c3aebd5SPatrice Chotard }; 62*4c3aebd5SPatrice Chotard }; 63*4c3aebd5SPatrice Chotard 64*4c3aebd5SPatrice Chotard 65*4c3aebd5SPatrice ChotardSTM32H7 PLL 66*4c3aebd5SPatrice Chotard----------- 67*4c3aebd5SPatrice Chotard 68*4c3aebd5SPatrice ChotardThe VCO of STM32 PLL could be reprensented like this: 69*4c3aebd5SPatrice Chotard 70*4c3aebd5SPatrice Chotard Vref --------- -------- 71*4c3aebd5SPatrice Chotard ---->| / DIVM |---->| x DIVN | ------> VCO 72*4c3aebd5SPatrice Chotard --------- -------- 73*4c3aebd5SPatrice Chotard ^ 74*4c3aebd5SPatrice Chotard | 75*4c3aebd5SPatrice Chotard ------- 76*4c3aebd5SPatrice Chotard | FRACN | 77*4c3aebd5SPatrice Chotard ------- 78*4c3aebd5SPatrice Chotard 79*4c3aebd5SPatrice ChotardWhen the PLL is configured in integer mode: 80*4c3aebd5SPatrice Chotard- VCO = ( Vref / DIVM ) * DIVN 81*4c3aebd5SPatrice Chotard 82*4c3aebd5SPatrice ChotardWhen the PLL is configured in fractional mode: 83*4c3aebd5SPatrice Chotard- VCO = ( Vref / DIVM ) * ( DIVN + FRACN / 2^13) 84*4c3aebd5SPatrice Chotard 85*4c3aebd5SPatrice Chotard 86*4c3aebd5SPatrice ChotardRequired properties for pll node: 87*4c3aebd5SPatrice Chotard- compatible: Should be: 88*4c3aebd5SPatrice Chotard "stm32,pll" 89*4c3aebd5SPatrice Chotard 90*4c3aebd5SPatrice Chotard- #clock-cells: from common clock binding; shall be set to 0 91*4c3aebd5SPatrice Chotard- reg: Should be the pll number. 92*4c3aebd5SPatrice Chotard 93*4c3aebd5SPatrice ChotardOptional properties: 94*4c3aebd5SPatrice Chotard- st,clock-div: DIVM division factor : <1..63> 95*4c3aebd5SPatrice Chotard- st,clock-mult: DIVN multiplication factor : <4..512> 96*4c3aebd5SPatrice Chotard 97*4c3aebd5SPatrice Chotard- st,frac-status: 98*4c3aebd5SPatrice Chotard - 0 Pll is configured in integer mode 99*4c3aebd5SPatrice Chotard - 1 Pll is configure in fractional mode 100*4c3aebd5SPatrice Chotard 101*4c3aebd5SPatrice Chotard- st,frac: Fractional part of the multiplication factor : <0..8191> 102*4c3aebd5SPatrice Chotard 103*4c3aebd5SPatrice Chotard- st,vcosel: VCO selection 104*4c3aebd5SPatrice Chotard - 0: Wide VCO range:192 to 836 MHz 105*4c3aebd5SPatrice Chotard - 1: Medium VCO range:150 to 420 MHz 106*4c3aebd5SPatrice Chotard 107*4c3aebd5SPatrice Chotard- st,pllrge: PLL input frequency range 108*4c3aebd5SPatrice Chotard - 0: The PLL input (Vref / DIVM) clock range frequency is between 1 and 2 MHz 109*4c3aebd5SPatrice Chotard - 1: The PLL input (Vref / DIVM) clock range frequency is between 2 and 4 MHz 110*4c3aebd5SPatrice Chotard - 2: The PLL input (Vref / DIVM) clock range frequency is between 4 and 8 MHz 111*4c3aebd5SPatrice Chotard - 3: The PLL input (Vref / DIVM) clock range frequency is between 8 and 16 MHz 112*4c3aebd5SPatrice Chotard 113*4c3aebd5SPatrice Chotard 114*4c3aebd5SPatrice ChotardThe peripheral clock consumer should specify the desired clock by 115*4c3aebd5SPatrice Chotardhaving the clock ID in its "clocks" phandle cell. 116*4c3aebd5SPatrice Chotard 117*4c3aebd5SPatrice ChotardAll available clocks are defined as preprocessor macros in 118*4c3aebd5SPatrice Chotarddt-bindings/clock/stm32h7-clks.h header and can be used in device 119*4c3aebd5SPatrice Chotardtree sources. 120*4c3aebd5SPatrice Chotard 121*4c3aebd5SPatrice ChotardExample: 122*4c3aebd5SPatrice Chotard 123*4c3aebd5SPatrice Chotard timer5: timer@40000c00 { 124*4c3aebd5SPatrice Chotard compatible = "st,stm32-timer"; 125*4c3aebd5SPatrice Chotard reg = <0x40000c00 0x400>; 126*4c3aebd5SPatrice Chotard interrupts = <50>; 127*4c3aebd5SPatrice Chotard clocks = <&rcc TIM5_CK>; 128*4c3aebd5SPatrice Chotard 129*4c3aebd5SPatrice Chotard }; 130*4c3aebd5SPatrice Chotard 131*4c3aebd5SPatrice ChotardSpecifying softreset control of devices 132*4c3aebd5SPatrice Chotard======================================= 133*4c3aebd5SPatrice Chotard 134*4c3aebd5SPatrice ChotardDevice nodes should specify the reset channel required in their "resets" 135*4c3aebd5SPatrice Chotardproperty, containing a phandle to the reset device node and an index specifying 136*4c3aebd5SPatrice Chotardwhich channel to use. 137*4c3aebd5SPatrice ChotardThe index is the bit number within the RCC registers bank, starting from RCC 138*4c3aebd5SPatrice Chotardbase address. 139*4c3aebd5SPatrice ChotardIt is calculated as: index = register_offset / 4 * 32 + bit_offset. 140*4c3aebd5SPatrice ChotardWhere bit_offset is the bit offset within the register. 141*4c3aebd5SPatrice Chotard 142*4c3aebd5SPatrice ChotardFor example, for CRC reset: 143*4c3aebd5SPatrice Chotard crc = AHB4RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x88 / 4 * 32 + 19 = 1107 144*4c3aebd5SPatrice Chotard 145*4c3aebd5SPatrice ChotardAll available preprocessor macros for reset are defined dt-bindings//mfd/stm32h7-rcc.h 146*4c3aebd5SPatrice Chotardheader and can be used in device tree sources. 147*4c3aebd5SPatrice Chotard 148*4c3aebd5SPatrice Chotardexample: 149*4c3aebd5SPatrice Chotard 150*4c3aebd5SPatrice Chotard timer2 { 151*4c3aebd5SPatrice Chotard resets = <&rcc STM32H7_APB1L_RESET(TIM2)>; 152*4c3aebd5SPatrice Chotard }; 153