1a674313cSPatrick Delaunay// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2a674313cSPatrick Delaunay/* 3a674313cSPatrick Delaunay * Copyright (C) STMicroelectronics 2017 - All Rights Reserved 4a674313cSPatrick Delaunay * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5a674313cSPatrick Delaunay */ 6a674313cSPatrick Delaunay#include <dt-bindings/interrupt-controller/arm-gic.h> 7a674313cSPatrick Delaunay#include <dt-bindings/clock/stm32mp1-clks.h> 8a674313cSPatrick Delaunay#include <dt-bindings/reset/stm32mp1-resets.h> 9a674313cSPatrick Delaunay 10a674313cSPatrick Delaunay/ { 11a674313cSPatrick Delaunay #address-cells = <1>; 12a674313cSPatrick Delaunay #size-cells = <1>; 13a674313cSPatrick Delaunay 14a674313cSPatrick Delaunay cpus { 15a674313cSPatrick Delaunay #address-cells = <1>; 16a674313cSPatrick Delaunay #size-cells = <0>; 17a674313cSPatrick Delaunay 18a674313cSPatrick Delaunay cpu0: cpu@0 { 19a674313cSPatrick Delaunay compatible = "arm,cortex-a7"; 20a674313cSPatrick Delaunay device_type = "cpu"; 21a674313cSPatrick Delaunay reg = <0>; 22a674313cSPatrick Delaunay }; 23a674313cSPatrick Delaunay 24a674313cSPatrick Delaunay cpu1: cpu@1 { 25a674313cSPatrick Delaunay compatible = "arm,cortex-a7"; 26a674313cSPatrick Delaunay device_type = "cpu"; 27a674313cSPatrick Delaunay reg = <1>; 28a674313cSPatrick Delaunay }; 29a674313cSPatrick Delaunay }; 30a674313cSPatrick Delaunay 31a674313cSPatrick Delaunay psci { 32a674313cSPatrick Delaunay compatible = "arm,psci"; 33a674313cSPatrick Delaunay method = "smc"; 34a674313cSPatrick Delaunay cpu_off = <0x84000002>; 35a674313cSPatrick Delaunay cpu_on = <0x84000003>; 36a674313cSPatrick Delaunay }; 37a674313cSPatrick Delaunay 38a674313cSPatrick Delaunay aliases { 39a674313cSPatrick Delaunay gpio0 = &gpioa; 40a674313cSPatrick Delaunay gpio1 = &gpiob; 41a674313cSPatrick Delaunay gpio2 = &gpioc; 42a674313cSPatrick Delaunay gpio3 = &gpiod; 43a674313cSPatrick Delaunay gpio4 = &gpioe; 44a674313cSPatrick Delaunay gpio5 = &gpiof; 45a674313cSPatrick Delaunay gpio6 = &gpiog; 46a674313cSPatrick Delaunay gpio7 = &gpioh; 47a674313cSPatrick Delaunay gpio8 = &gpioi; 48a674313cSPatrick Delaunay gpio9 = &gpioj; 49a674313cSPatrick Delaunay gpio10 = &gpiok; 50a674313cSPatrick Delaunay serial0 = &usart1; 51a674313cSPatrick Delaunay serial1 = &usart2; 52a674313cSPatrick Delaunay serial2 = &usart3; 53a674313cSPatrick Delaunay serial3 = &uart4; 54a674313cSPatrick Delaunay serial4 = &uart5; 55a674313cSPatrick Delaunay serial5 = &usart6; 56a674313cSPatrick Delaunay serial6 = &uart7; 57a674313cSPatrick Delaunay serial7 = &uart8; 58a674313cSPatrick Delaunay }; 59a674313cSPatrick Delaunay 60a674313cSPatrick Delaunay intc: interrupt-controller@a0021000 { 61a674313cSPatrick Delaunay compatible = "arm,cortex-a7-gic"; 62a674313cSPatrick Delaunay #interrupt-cells = <3>; 63a674313cSPatrick Delaunay interrupt-controller; 64a674313cSPatrick Delaunay reg = <0xa0021000 0x1000>, 65a674313cSPatrick Delaunay <0xa0022000 0x2000>; 66a674313cSPatrick Delaunay }; 67a674313cSPatrick Delaunay 68a674313cSPatrick Delaunay timer { 69a674313cSPatrick Delaunay compatible = "arm,armv7-timer"; 70a674313cSPatrick Delaunay interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 71a674313cSPatrick Delaunay <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 72a674313cSPatrick Delaunay <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 73a674313cSPatrick Delaunay <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 74a674313cSPatrick Delaunay interrupt-parent = <&intc>; 75a674313cSPatrick Delaunay }; 76a674313cSPatrick Delaunay 77a674313cSPatrick Delaunay clocks { 78a674313cSPatrick Delaunay clk_hse: clk-hse { 79a674313cSPatrick Delaunay #clock-cells = <0>; 80a674313cSPatrick Delaunay compatible = "fixed-clock"; 81a674313cSPatrick Delaunay clock-frequency = <24000000>; 82a674313cSPatrick Delaunay }; 83a674313cSPatrick Delaunay 84a674313cSPatrick Delaunay clk_hsi: clk-hsi { 85a674313cSPatrick Delaunay #clock-cells = <0>; 86a674313cSPatrick Delaunay compatible = "fixed-clock"; 87a674313cSPatrick Delaunay clock-frequency = <64000000>; 88a674313cSPatrick Delaunay }; 89a674313cSPatrick Delaunay 90a674313cSPatrick Delaunay clk_lse: clk-lse { 91a674313cSPatrick Delaunay #clock-cells = <0>; 92a674313cSPatrick Delaunay compatible = "fixed-clock"; 93a674313cSPatrick Delaunay clock-frequency = <32768>; 94a674313cSPatrick Delaunay }; 95a674313cSPatrick Delaunay 96a674313cSPatrick Delaunay clk_lsi: clk-lsi { 97a674313cSPatrick Delaunay #clock-cells = <0>; 98a674313cSPatrick Delaunay compatible = "fixed-clock"; 99a674313cSPatrick Delaunay clock-frequency = <32000>; 100a674313cSPatrick Delaunay }; 101a674313cSPatrick Delaunay 102a674313cSPatrick Delaunay clk_csi: clk-csi { 103a674313cSPatrick Delaunay #clock-cells = <0>; 104a674313cSPatrick Delaunay compatible = "fixed-clock"; 105a674313cSPatrick Delaunay clock-frequency = <4000000>; 106a674313cSPatrick Delaunay }; 107a674313cSPatrick Delaunay }; 108a674313cSPatrick Delaunay 1098e9c94d7SPatrice Chotard pm_domain { 1108e9c94d7SPatrice Chotard #address-cells = <1>; 1118e9c94d7SPatrice Chotard #size-cells = <0>; 1128e9c94d7SPatrice Chotard compatible = "st,stm32mp157c-pd"; 1138e9c94d7SPatrice Chotard 1148e9c94d7SPatrice Chotard pd_core_ret: core-ret-power-domain@1 { 1158e9c94d7SPatrice Chotard #address-cells = <1>; 1168e9c94d7SPatrice Chotard #size-cells = <0>; 1178e9c94d7SPatrice Chotard reg = <1>; 1188e9c94d7SPatrice Chotard #power-domain-cells = <0>; 1198e9c94d7SPatrice Chotard label = "CORE-RETENTION"; 1208e9c94d7SPatrice Chotard 1218e9c94d7SPatrice Chotard pd_core: core-power-domain@2 { 1228e9c94d7SPatrice Chotard reg = <2>; 1238e9c94d7SPatrice Chotard #power-domain-cells = <0>; 1248e9c94d7SPatrice Chotard label = "CORE"; 1258e9c94d7SPatrice Chotard }; 1268e9c94d7SPatrice Chotard }; 1278e9c94d7SPatrice Chotard }; 1288e9c94d7SPatrice Chotard 129a674313cSPatrick Delaunay soc { 130a674313cSPatrick Delaunay compatible = "simple-bus"; 131a674313cSPatrick Delaunay #address-cells = <1>; 132a674313cSPatrick Delaunay #size-cells = <1>; 133a674313cSPatrick Delaunay interrupt-parent = <&intc>; 134a674313cSPatrick Delaunay ranges; 135a674313cSPatrick Delaunay 136a674313cSPatrick Delaunay timers2: timer@40000000 { 137a674313cSPatrick Delaunay #address-cells = <1>; 138a674313cSPatrick Delaunay #size-cells = <0>; 139a674313cSPatrick Delaunay compatible = "st,stm32-timers"; 140a674313cSPatrick Delaunay reg = <0x40000000 0x400>; 141a674313cSPatrick Delaunay clocks = <&rcc TIM2_K>; 142a674313cSPatrick Delaunay clock-names = "int"; 143a674313cSPatrick Delaunay status = "disabled"; 144a674313cSPatrick Delaunay 145a674313cSPatrick Delaunay pwm { 146a674313cSPatrick Delaunay compatible = "st,stm32-pwm"; 147a674313cSPatrick Delaunay status = "disabled"; 148a674313cSPatrick Delaunay }; 149a674313cSPatrick Delaunay 150a674313cSPatrick Delaunay timer@1 { 151a674313cSPatrick Delaunay compatible = "st,stm32h7-timer-trigger"; 152a674313cSPatrick Delaunay reg = <1>; 153a674313cSPatrick Delaunay status = "disabled"; 154a674313cSPatrick Delaunay }; 155a674313cSPatrick Delaunay }; 156a674313cSPatrick Delaunay 157a674313cSPatrick Delaunay timers3: timer@40001000 { 158a674313cSPatrick Delaunay #address-cells = <1>; 159a674313cSPatrick Delaunay #size-cells = <0>; 160a674313cSPatrick Delaunay compatible = "st,stm32-timers"; 161a674313cSPatrick Delaunay reg = <0x40001000 0x400>; 162a674313cSPatrick Delaunay clocks = <&rcc TIM3_K>; 163a674313cSPatrick Delaunay clock-names = "int"; 164a674313cSPatrick Delaunay status = "disabled"; 165a674313cSPatrick Delaunay 166a674313cSPatrick Delaunay pwm { 167a674313cSPatrick Delaunay compatible = "st,stm32-pwm"; 168a674313cSPatrick Delaunay status = "disabled"; 169a674313cSPatrick Delaunay }; 170a674313cSPatrick Delaunay 171a674313cSPatrick Delaunay timer@2 { 172a674313cSPatrick Delaunay compatible = "st,stm32h7-timer-trigger"; 173a674313cSPatrick Delaunay reg = <2>; 174a674313cSPatrick Delaunay status = "disabled"; 175a674313cSPatrick Delaunay }; 176a674313cSPatrick Delaunay }; 177a674313cSPatrick Delaunay 178a674313cSPatrick Delaunay timers4: timer@40002000 { 179a674313cSPatrick Delaunay #address-cells = <1>; 180a674313cSPatrick Delaunay #size-cells = <0>; 181a674313cSPatrick Delaunay compatible = "st,stm32-timers"; 182a674313cSPatrick Delaunay reg = <0x40002000 0x400>; 183a674313cSPatrick Delaunay clocks = <&rcc TIM4_K>; 184a674313cSPatrick Delaunay clock-names = "int"; 185a674313cSPatrick Delaunay status = "disabled"; 186a674313cSPatrick Delaunay 187a674313cSPatrick Delaunay pwm { 188a674313cSPatrick Delaunay compatible = "st,stm32-pwm"; 189a674313cSPatrick Delaunay status = "disabled"; 190a674313cSPatrick Delaunay }; 191a674313cSPatrick Delaunay 192a674313cSPatrick Delaunay timer@3 { 193a674313cSPatrick Delaunay compatible = "st,stm32h7-timer-trigger"; 194a674313cSPatrick Delaunay reg = <3>; 195a674313cSPatrick Delaunay status = "disabled"; 196a674313cSPatrick Delaunay }; 197a674313cSPatrick Delaunay }; 198a674313cSPatrick Delaunay 199a674313cSPatrick Delaunay timers5: timer@40003000 { 200a674313cSPatrick Delaunay #address-cells = <1>; 201a674313cSPatrick Delaunay #size-cells = <0>; 202a674313cSPatrick Delaunay compatible = "st,stm32-timers"; 203a674313cSPatrick Delaunay reg = <0x40003000 0x400>; 204a674313cSPatrick Delaunay clocks = <&rcc TIM5_K>; 205a674313cSPatrick Delaunay clock-names = "int"; 206a674313cSPatrick Delaunay status = "disabled"; 207a674313cSPatrick Delaunay 208a674313cSPatrick Delaunay pwm { 209a674313cSPatrick Delaunay compatible = "st,stm32-pwm"; 210a674313cSPatrick Delaunay status = "disabled"; 211a674313cSPatrick Delaunay }; 212a674313cSPatrick Delaunay 213a674313cSPatrick Delaunay timer@4 { 214a674313cSPatrick Delaunay compatible = "st,stm32h7-timer-trigger"; 215a674313cSPatrick Delaunay reg = <4>; 216a674313cSPatrick Delaunay status = "disabled"; 217a674313cSPatrick Delaunay }; 218a674313cSPatrick Delaunay }; 219a674313cSPatrick Delaunay 220a674313cSPatrick Delaunay timers6: timer@40004000 { 221a674313cSPatrick Delaunay #address-cells = <1>; 222a674313cSPatrick Delaunay #size-cells = <0>; 223a674313cSPatrick Delaunay compatible = "st,stm32-timers"; 224a674313cSPatrick Delaunay reg = <0x40004000 0x400>; 225a674313cSPatrick Delaunay clocks = <&rcc TIM6_K>; 226a674313cSPatrick Delaunay clock-names = "int"; 227a674313cSPatrick Delaunay status = "disabled"; 228a674313cSPatrick Delaunay 229a674313cSPatrick Delaunay timer@5 { 230a674313cSPatrick Delaunay compatible = "st,stm32h7-timer-trigger"; 231a674313cSPatrick Delaunay reg = <5>; 232a674313cSPatrick Delaunay status = "disabled"; 233a674313cSPatrick Delaunay }; 234a674313cSPatrick Delaunay }; 235a674313cSPatrick Delaunay 236a674313cSPatrick Delaunay timers7: timer@40005000 { 237a674313cSPatrick Delaunay #address-cells = <1>; 238a674313cSPatrick Delaunay #size-cells = <0>; 239a674313cSPatrick Delaunay compatible = "st,stm32-timers"; 240a674313cSPatrick Delaunay reg = <0x40005000 0x400>; 241a674313cSPatrick Delaunay clocks = <&rcc TIM7_K>; 242a674313cSPatrick Delaunay clock-names = "int"; 243a674313cSPatrick Delaunay status = "disabled"; 244a674313cSPatrick Delaunay 245a674313cSPatrick Delaunay timer@6 { 246a674313cSPatrick Delaunay compatible = "st,stm32h7-timer-trigger"; 247a674313cSPatrick Delaunay reg = <6>; 248a674313cSPatrick Delaunay status = "disabled"; 249a674313cSPatrick Delaunay }; 250a674313cSPatrick Delaunay }; 251a674313cSPatrick Delaunay 252a674313cSPatrick Delaunay timers12: timer@40006000 { 253a674313cSPatrick Delaunay #address-cells = <1>; 254a674313cSPatrick Delaunay #size-cells = <0>; 255a674313cSPatrick Delaunay compatible = "st,stm32-timers"; 256a674313cSPatrick Delaunay reg = <0x40006000 0x400>; 257a674313cSPatrick Delaunay clocks = <&rcc TIM12_K>; 258a674313cSPatrick Delaunay clock-names = "int"; 259a674313cSPatrick Delaunay status = "disabled"; 260a674313cSPatrick Delaunay 261a674313cSPatrick Delaunay pwm { 262a674313cSPatrick Delaunay compatible = "st,stm32-pwm"; 263a674313cSPatrick Delaunay status = "disabled"; 264a674313cSPatrick Delaunay }; 265a674313cSPatrick Delaunay 266a674313cSPatrick Delaunay timer@11 { 267a674313cSPatrick Delaunay compatible = "st,stm32h7-timer-trigger"; 268a674313cSPatrick Delaunay reg = <11>; 269a674313cSPatrick Delaunay status = "disabled"; 270a674313cSPatrick Delaunay }; 271a674313cSPatrick Delaunay }; 272a674313cSPatrick Delaunay 273a674313cSPatrick Delaunay timers13: timer@40007000 { 274a674313cSPatrick Delaunay #address-cells = <1>; 275a674313cSPatrick Delaunay #size-cells = <0>; 276a674313cSPatrick Delaunay compatible = "st,stm32-timers"; 277a674313cSPatrick Delaunay reg = <0x40007000 0x400>; 278a674313cSPatrick Delaunay clocks = <&rcc TIM13_K>; 279a674313cSPatrick Delaunay clock-names = "int"; 280a674313cSPatrick Delaunay status = "disabled"; 281a674313cSPatrick Delaunay 282a674313cSPatrick Delaunay pwm { 283a674313cSPatrick Delaunay compatible = "st,stm32-pwm"; 284a674313cSPatrick Delaunay status = "disabled"; 285a674313cSPatrick Delaunay }; 286a674313cSPatrick Delaunay 287a674313cSPatrick Delaunay timer@12 { 288a674313cSPatrick Delaunay compatible = "st,stm32h7-timer-trigger"; 289a674313cSPatrick Delaunay reg = <12>; 290a674313cSPatrick Delaunay status = "disabled"; 291a674313cSPatrick Delaunay }; 292a674313cSPatrick Delaunay }; 293a674313cSPatrick Delaunay 294a674313cSPatrick Delaunay timers14: timer@40008000 { 295a674313cSPatrick Delaunay #address-cells = <1>; 296a674313cSPatrick Delaunay #size-cells = <0>; 297a674313cSPatrick Delaunay compatible = "st,stm32-timers"; 298a674313cSPatrick Delaunay reg = <0x40008000 0x400>; 299a674313cSPatrick Delaunay clocks = <&rcc TIM14_K>; 300a674313cSPatrick Delaunay clock-names = "int"; 301a674313cSPatrick Delaunay status = "disabled"; 302a674313cSPatrick Delaunay 303a674313cSPatrick Delaunay pwm { 304a674313cSPatrick Delaunay compatible = "st,stm32-pwm"; 305a674313cSPatrick Delaunay status = "disabled"; 306a674313cSPatrick Delaunay }; 307a674313cSPatrick Delaunay 308a674313cSPatrick Delaunay timer@13 { 309a674313cSPatrick Delaunay compatible = "st,stm32h7-timer-trigger"; 310a674313cSPatrick Delaunay reg = <13>; 311a674313cSPatrick Delaunay status = "disabled"; 312a674313cSPatrick Delaunay }; 313a674313cSPatrick Delaunay }; 314a674313cSPatrick Delaunay 315a674313cSPatrick Delaunay lptimer1: timer@40009000 { 316a674313cSPatrick Delaunay #address-cells = <1>; 317a674313cSPatrick Delaunay #size-cells = <0>; 318a674313cSPatrick Delaunay compatible = "st,stm32-lptimer"; 319a674313cSPatrick Delaunay reg = <0x40009000 0x400>; 320a674313cSPatrick Delaunay clocks = <&rcc LPTIM1_K>; 321a674313cSPatrick Delaunay clock-names = "mux"; 322a674313cSPatrick Delaunay status = "disabled"; 323a674313cSPatrick Delaunay 324a674313cSPatrick Delaunay pwm { 325a674313cSPatrick Delaunay compatible = "st,stm32-pwm-lp"; 326a674313cSPatrick Delaunay #pwm-cells = <3>; 327a674313cSPatrick Delaunay status = "disabled"; 328a674313cSPatrick Delaunay }; 329a674313cSPatrick Delaunay 330a674313cSPatrick Delaunay trigger@0 { 331a674313cSPatrick Delaunay compatible = "st,stm32-lptimer-trigger"; 332a674313cSPatrick Delaunay reg = <0>; 333a674313cSPatrick Delaunay status = "disabled"; 334a674313cSPatrick Delaunay }; 335a674313cSPatrick Delaunay 336a674313cSPatrick Delaunay counter { 337a674313cSPatrick Delaunay compatible = "st,stm32-lptimer-counter"; 338a674313cSPatrick Delaunay status = "disabled"; 339a674313cSPatrick Delaunay }; 340a674313cSPatrick Delaunay }; 341a674313cSPatrick Delaunay 342a674313cSPatrick Delaunay usart2: serial@4000e000 { 343a674313cSPatrick Delaunay compatible = "st,stm32h7-uart"; 344a674313cSPatrick Delaunay reg = <0x4000e000 0x400>; 345a674313cSPatrick Delaunay interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 346a674313cSPatrick Delaunay clocks = <&rcc USART2_K>; 347a674313cSPatrick Delaunay status = "disabled"; 348a674313cSPatrick Delaunay }; 349a674313cSPatrick Delaunay 350a674313cSPatrick Delaunay usart3: serial@4000f000 { 351a674313cSPatrick Delaunay compatible = "st,stm32h7-uart"; 352a674313cSPatrick Delaunay reg = <0x4000f000 0x400>; 353a674313cSPatrick Delaunay interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 354a674313cSPatrick Delaunay clocks = <&rcc USART3_K>; 355a674313cSPatrick Delaunay status = "disabled"; 356a674313cSPatrick Delaunay }; 357a674313cSPatrick Delaunay 358a674313cSPatrick Delaunay uart4: serial@40010000 { 359a674313cSPatrick Delaunay compatible = "st,stm32h7-uart"; 360a674313cSPatrick Delaunay reg = <0x40010000 0x400>; 361a674313cSPatrick Delaunay interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 362a674313cSPatrick Delaunay clocks = <&rcc UART4_K>; 363a674313cSPatrick Delaunay status = "disabled"; 364a674313cSPatrick Delaunay }; 365a674313cSPatrick Delaunay 366a674313cSPatrick Delaunay uart5: serial@40011000 { 367a674313cSPatrick Delaunay compatible = "st,stm32h7-uart"; 368a674313cSPatrick Delaunay reg = <0x40011000 0x400>; 369a674313cSPatrick Delaunay interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 370a674313cSPatrick Delaunay clocks = <&rcc UART5_K>; 371a674313cSPatrick Delaunay status = "disabled"; 372a674313cSPatrick Delaunay }; 373a674313cSPatrick Delaunay 374a674313cSPatrick Delaunay i2c1: i2c@40012000 { 375a674313cSPatrick Delaunay compatible = "st,stm32f7-i2c"; 376a674313cSPatrick Delaunay reg = <0x40012000 0x400>; 377a674313cSPatrick Delaunay interrupt-names = "event", "error"; 378a674313cSPatrick Delaunay interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 379a674313cSPatrick Delaunay <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 380a674313cSPatrick Delaunay clocks = <&rcc I2C1_K>; 381a674313cSPatrick Delaunay resets = <&rcc I2C1_R>; 382a674313cSPatrick Delaunay #address-cells = <1>; 383a674313cSPatrick Delaunay #size-cells = <0>; 384a674313cSPatrick Delaunay status = "disabled"; 385a674313cSPatrick Delaunay }; 386a674313cSPatrick Delaunay 387a674313cSPatrick Delaunay i2c2: i2c@40013000 { 388a674313cSPatrick Delaunay compatible = "st,stm32f7-i2c"; 389a674313cSPatrick Delaunay reg = <0x40013000 0x400>; 390a674313cSPatrick Delaunay interrupt-names = "event", "error"; 391a674313cSPatrick Delaunay interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 392a674313cSPatrick Delaunay <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 393a674313cSPatrick Delaunay clocks = <&rcc I2C2_K>; 394a674313cSPatrick Delaunay resets = <&rcc I2C2_R>; 395a674313cSPatrick Delaunay #address-cells = <1>; 396a674313cSPatrick Delaunay #size-cells = <0>; 397a674313cSPatrick Delaunay status = "disabled"; 398a674313cSPatrick Delaunay }; 399a674313cSPatrick Delaunay 400a674313cSPatrick Delaunay i2c3: i2c@40014000 { 401a674313cSPatrick Delaunay compatible = "st,stm32f7-i2c"; 402a674313cSPatrick Delaunay reg = <0x40014000 0x400>; 403a674313cSPatrick Delaunay interrupt-names = "event", "error"; 404a674313cSPatrick Delaunay interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 405a674313cSPatrick Delaunay <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 406a674313cSPatrick Delaunay clocks = <&rcc I2C3_K>; 407a674313cSPatrick Delaunay resets = <&rcc I2C3_R>; 408a674313cSPatrick Delaunay #address-cells = <1>; 409a674313cSPatrick Delaunay #size-cells = <0>; 410a674313cSPatrick Delaunay status = "disabled"; 411a674313cSPatrick Delaunay }; 412a674313cSPatrick Delaunay 413a674313cSPatrick Delaunay i2c5: i2c@40015000 { 414a674313cSPatrick Delaunay compatible = "st,stm32f7-i2c"; 415a674313cSPatrick Delaunay reg = <0x40015000 0x400>; 416a674313cSPatrick Delaunay interrupt-names = "event", "error"; 417a674313cSPatrick Delaunay interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 418a674313cSPatrick Delaunay <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 419a674313cSPatrick Delaunay clocks = <&rcc I2C5_K>; 420a674313cSPatrick Delaunay resets = <&rcc I2C5_R>; 421a674313cSPatrick Delaunay #address-cells = <1>; 422a674313cSPatrick Delaunay #size-cells = <0>; 423a674313cSPatrick Delaunay status = "disabled"; 424a674313cSPatrick Delaunay }; 425a674313cSPatrick Delaunay 426a674313cSPatrick Delaunay cec: cec@40016000 { 427a674313cSPatrick Delaunay compatible = "st,stm32-cec"; 428a674313cSPatrick Delaunay reg = <0x40016000 0x400>; 429a674313cSPatrick Delaunay interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 430a674313cSPatrick Delaunay clocks = <&rcc CEC_K>, <&clk_lse>; 431a674313cSPatrick Delaunay clock-names = "cec", "hdmi-cec"; 432a674313cSPatrick Delaunay status = "disabled"; 433a674313cSPatrick Delaunay }; 434a674313cSPatrick Delaunay 435a674313cSPatrick Delaunay dac: dac@40017000 { 436a674313cSPatrick Delaunay compatible = "st,stm32h7-dac-core"; 437a674313cSPatrick Delaunay reg = <0x40017000 0x400>; 438a674313cSPatrick Delaunay clocks = <&rcc DAC12>; 439a674313cSPatrick Delaunay clock-names = "pclk"; 440a674313cSPatrick Delaunay #address-cells = <1>; 441a674313cSPatrick Delaunay #size-cells = <0>; 442a674313cSPatrick Delaunay status = "disabled"; 443a674313cSPatrick Delaunay 444a674313cSPatrick Delaunay dac1: dac@1 { 445a674313cSPatrick Delaunay compatible = "st,stm32-dac"; 446a674313cSPatrick Delaunay #io-channels-cells = <1>; 447a674313cSPatrick Delaunay reg = <1>; 448a674313cSPatrick Delaunay status = "disabled"; 449a674313cSPatrick Delaunay }; 450a674313cSPatrick Delaunay 451a674313cSPatrick Delaunay dac2: dac@2 { 452a674313cSPatrick Delaunay compatible = "st,stm32-dac"; 453a674313cSPatrick Delaunay #io-channels-cells = <1>; 454a674313cSPatrick Delaunay reg = <2>; 455a674313cSPatrick Delaunay status = "disabled"; 456a674313cSPatrick Delaunay }; 457a674313cSPatrick Delaunay }; 458a674313cSPatrick Delaunay 459a674313cSPatrick Delaunay uart7: serial@40018000 { 460a674313cSPatrick Delaunay compatible = "st,stm32h7-uart"; 461a674313cSPatrick Delaunay reg = <0x40018000 0x400>; 462a674313cSPatrick Delaunay interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 463a674313cSPatrick Delaunay clocks = <&rcc UART7_K>; 464a674313cSPatrick Delaunay status = "disabled"; 465a674313cSPatrick Delaunay }; 466a674313cSPatrick Delaunay 467a674313cSPatrick Delaunay uart8: serial@40019000 { 468a674313cSPatrick Delaunay compatible = "st,stm32h7-uart"; 469a674313cSPatrick Delaunay reg = <0x40019000 0x400>; 470a674313cSPatrick Delaunay interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 471a674313cSPatrick Delaunay clocks = <&rcc UART8_K>; 472a674313cSPatrick Delaunay status = "disabled"; 473a674313cSPatrick Delaunay }; 474a674313cSPatrick Delaunay 475a674313cSPatrick Delaunay timers1: timer@44000000 { 476a674313cSPatrick Delaunay #address-cells = <1>; 477a674313cSPatrick Delaunay #size-cells = <0>; 478a674313cSPatrick Delaunay compatible = "st,stm32-timers"; 479a674313cSPatrick Delaunay reg = <0x44000000 0x400>; 480a674313cSPatrick Delaunay clocks = <&rcc TIM1_K>; 481a674313cSPatrick Delaunay clock-names = "int"; 482a674313cSPatrick Delaunay status = "disabled"; 483a674313cSPatrick Delaunay 484a674313cSPatrick Delaunay pwm { 485a674313cSPatrick Delaunay compatible = "st,stm32-pwm"; 486a674313cSPatrick Delaunay status = "disabled"; 487a674313cSPatrick Delaunay }; 488a674313cSPatrick Delaunay 489a674313cSPatrick Delaunay timer@0 { 490a674313cSPatrick Delaunay compatible = "st,stm32h7-timer-trigger"; 491a674313cSPatrick Delaunay reg = <0>; 492a674313cSPatrick Delaunay status = "disabled"; 493a674313cSPatrick Delaunay }; 494a674313cSPatrick Delaunay }; 495a674313cSPatrick Delaunay 496a674313cSPatrick Delaunay timers8: timer@44001000 { 497a674313cSPatrick Delaunay #address-cells = <1>; 498a674313cSPatrick Delaunay #size-cells = <0>; 499a674313cSPatrick Delaunay compatible = "st,stm32-timers"; 500a674313cSPatrick Delaunay reg = <0x44001000 0x400>; 501a674313cSPatrick Delaunay clocks = <&rcc TIM8_K>; 502a674313cSPatrick Delaunay clock-names = "int"; 503a674313cSPatrick Delaunay status = "disabled"; 504a674313cSPatrick Delaunay 505a674313cSPatrick Delaunay pwm { 506a674313cSPatrick Delaunay compatible = "st,stm32-pwm"; 507a674313cSPatrick Delaunay status = "disabled"; 508a674313cSPatrick Delaunay }; 509a674313cSPatrick Delaunay 510a674313cSPatrick Delaunay timer@7 { 511a674313cSPatrick Delaunay compatible = "st,stm32h7-timer-trigger"; 512a674313cSPatrick Delaunay reg = <7>; 513a674313cSPatrick Delaunay status = "disabled"; 514a674313cSPatrick Delaunay }; 515a674313cSPatrick Delaunay }; 516a674313cSPatrick Delaunay 517a674313cSPatrick Delaunay usart6: serial@44003000 { 518a674313cSPatrick Delaunay compatible = "st,stm32h7-uart"; 519a674313cSPatrick Delaunay reg = <0x44003000 0x400>; 520a674313cSPatrick Delaunay interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 521a674313cSPatrick Delaunay clocks = <&rcc USART6_K>; 522a674313cSPatrick Delaunay status = "disabled"; 523a674313cSPatrick Delaunay }; 524a674313cSPatrick Delaunay 525a674313cSPatrick Delaunay timers15: timer@44006000 { 526a674313cSPatrick Delaunay #address-cells = <1>; 527a674313cSPatrick Delaunay #size-cells = <0>; 528a674313cSPatrick Delaunay compatible = "st,stm32-timers"; 529a674313cSPatrick Delaunay reg = <0x44006000 0x400>; 530a674313cSPatrick Delaunay clocks = <&rcc TIM15_K>; 531a674313cSPatrick Delaunay clock-names = "int"; 532a674313cSPatrick Delaunay status = "disabled"; 533a674313cSPatrick Delaunay 534a674313cSPatrick Delaunay pwm { 535a674313cSPatrick Delaunay compatible = "st,stm32-pwm"; 536a674313cSPatrick Delaunay status = "disabled"; 537a674313cSPatrick Delaunay }; 538a674313cSPatrick Delaunay 539a674313cSPatrick Delaunay timer@14 { 540a674313cSPatrick Delaunay compatible = "st,stm32h7-timer-trigger"; 541a674313cSPatrick Delaunay reg = <14>; 542a674313cSPatrick Delaunay status = "disabled"; 543a674313cSPatrick Delaunay }; 544a674313cSPatrick Delaunay }; 545a674313cSPatrick Delaunay 546a674313cSPatrick Delaunay timers16: timer@44007000 { 547a674313cSPatrick Delaunay #address-cells = <1>; 548a674313cSPatrick Delaunay #size-cells = <0>; 549a674313cSPatrick Delaunay compatible = "st,stm32-timers"; 550a674313cSPatrick Delaunay reg = <0x44007000 0x400>; 551a674313cSPatrick Delaunay clocks = <&rcc TIM16_K>; 552a674313cSPatrick Delaunay clock-names = "int"; 553a674313cSPatrick Delaunay status = "disabled"; 554a674313cSPatrick Delaunay 555a674313cSPatrick Delaunay pwm { 556a674313cSPatrick Delaunay compatible = "st,stm32-pwm"; 557a674313cSPatrick Delaunay status = "disabled"; 558a674313cSPatrick Delaunay }; 559a674313cSPatrick Delaunay timer@15 { 560a674313cSPatrick Delaunay compatible = "st,stm32h7-timer-trigger"; 561a674313cSPatrick Delaunay reg = <15>; 562a674313cSPatrick Delaunay status = "disabled"; 563a674313cSPatrick Delaunay }; 564a674313cSPatrick Delaunay }; 565a674313cSPatrick Delaunay 566a674313cSPatrick Delaunay timers17: timer@44008000 { 567a674313cSPatrick Delaunay #address-cells = <1>; 568a674313cSPatrick Delaunay #size-cells = <0>; 569a674313cSPatrick Delaunay compatible = "st,stm32-timers"; 570a674313cSPatrick Delaunay reg = <0x44008000 0x400>; 571a674313cSPatrick Delaunay clocks = <&rcc TIM17_K>; 572a674313cSPatrick Delaunay clock-names = "int"; 573a674313cSPatrick Delaunay status = "disabled"; 574a674313cSPatrick Delaunay 575a674313cSPatrick Delaunay pwm { 576a674313cSPatrick Delaunay compatible = "st,stm32-pwm"; 577a674313cSPatrick Delaunay status = "disabled"; 578a674313cSPatrick Delaunay }; 579a674313cSPatrick Delaunay 580a674313cSPatrick Delaunay timer@16 { 581a674313cSPatrick Delaunay compatible = "st,stm32h7-timer-trigger"; 582a674313cSPatrick Delaunay reg = <16>; 583a674313cSPatrick Delaunay status = "disabled"; 584a674313cSPatrick Delaunay }; 585a674313cSPatrick Delaunay }; 586a674313cSPatrick Delaunay 587a674313cSPatrick Delaunay dma1: dma@48000000 { 588a674313cSPatrick Delaunay compatible = "st,stm32-dma"; 589a674313cSPatrick Delaunay reg = <0x48000000 0x400>; 590a674313cSPatrick Delaunay interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 591a674313cSPatrick Delaunay <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 592a674313cSPatrick Delaunay <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 593a674313cSPatrick Delaunay <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 594a674313cSPatrick Delaunay <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 595a674313cSPatrick Delaunay <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 596a674313cSPatrick Delaunay <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 597a674313cSPatrick Delaunay <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 598a674313cSPatrick Delaunay clocks = <&rcc DMA1>; 599a674313cSPatrick Delaunay #dma-cells = <4>; 600a674313cSPatrick Delaunay st,mem2mem; 601a674313cSPatrick Delaunay dma-requests = <8>; 602a674313cSPatrick Delaunay }; 603a674313cSPatrick Delaunay 604a674313cSPatrick Delaunay dma2: dma@48001000 { 605a674313cSPatrick Delaunay compatible = "st,stm32-dma"; 606a674313cSPatrick Delaunay reg = <0x48001000 0x400>; 607a674313cSPatrick Delaunay interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 608a674313cSPatrick Delaunay <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 609a674313cSPatrick Delaunay <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 610a674313cSPatrick Delaunay <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 611a674313cSPatrick Delaunay <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 612a674313cSPatrick Delaunay <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 613a674313cSPatrick Delaunay <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 614a674313cSPatrick Delaunay <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 615a674313cSPatrick Delaunay clocks = <&rcc DMA2>; 616a674313cSPatrick Delaunay #dma-cells = <4>; 617a674313cSPatrick Delaunay st,mem2mem; 618a674313cSPatrick Delaunay dma-requests = <8>; 619a674313cSPatrick Delaunay }; 620a674313cSPatrick Delaunay 621a674313cSPatrick Delaunay dmamux1: dma-router@48002000 { 622a674313cSPatrick Delaunay compatible = "st,stm32h7-dmamux"; 623a674313cSPatrick Delaunay reg = <0x48002000 0x1c>; 624a674313cSPatrick Delaunay #dma-cells = <3>; 625a674313cSPatrick Delaunay dma-requests = <128>; 626a674313cSPatrick Delaunay dma-masters = <&dma1 &dma2>; 627a674313cSPatrick Delaunay dma-channels = <16>; 628a674313cSPatrick Delaunay clocks = <&rcc DMAMUX>; 629a674313cSPatrick Delaunay }; 630a674313cSPatrick Delaunay 631638ee5afSPatrice Chotard adc: adc@48003000 { 632638ee5afSPatrice Chotard compatible = "st,stm32mp1-adc-core"; 633638ee5afSPatrice Chotard reg = <0x48003000 0x400>; 634638ee5afSPatrice Chotard interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 635638ee5afSPatrice Chotard <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 636638ee5afSPatrice Chotard clocks = <&rcc ADC12>, <&rcc ADC12_K>; 637638ee5afSPatrice Chotard clock-names = "bus", "adc"; 638638ee5afSPatrice Chotard interrupt-controller; 639638ee5afSPatrice Chotard #interrupt-cells = <1>; 640638ee5afSPatrice Chotard #address-cells = <1>; 641638ee5afSPatrice Chotard #size-cells = <0>; 642638ee5afSPatrice Chotard status = "disabled"; 643638ee5afSPatrice Chotard 644638ee5afSPatrice Chotard adc1: adc@0 { 645638ee5afSPatrice Chotard compatible = "st,stm32mp1-adc"; 646638ee5afSPatrice Chotard #io-channel-cells = <1>; 647638ee5afSPatrice Chotard reg = <0x0>; 648638ee5afSPatrice Chotard interrupt-parent = <&adc>; 649638ee5afSPatrice Chotard interrupts = <0>; 650638ee5afSPatrice Chotard status = "disabled"; 651638ee5afSPatrice Chotard }; 652638ee5afSPatrice Chotard 653638ee5afSPatrice Chotard adc2: adc@100 { 654638ee5afSPatrice Chotard compatible = "st,stm32mp1-adc"; 655638ee5afSPatrice Chotard #io-channel-cells = <1>; 656638ee5afSPatrice Chotard reg = <0x100>; 657638ee5afSPatrice Chotard interrupt-parent = <&adc>; 658638ee5afSPatrice Chotard interrupts = <1>; 659638ee5afSPatrice Chotard status = "disabled"; 660638ee5afSPatrice Chotard }; 661638ee5afSPatrice Chotard }; 662638ee5afSPatrice Chotard 663a674313cSPatrick Delaunay sdmmc3: sdmmc@48004000 { 664a674313cSPatrick Delaunay compatible = "st,stm32-sdmmc2"; 665a674313cSPatrick Delaunay reg = <0x48004000 0x400>, <0x48005000 0x400>; 666a674313cSPatrick Delaunay reg-names = "sdmmc", "delay"; 667a674313cSPatrick Delaunay interrupts = <GIC_SPI 137 IRQ_TYPE_NONE>; 668a674313cSPatrick Delaunay clocks = <&rcc SDMMC3_K>; 669a674313cSPatrick Delaunay resets = <&rcc SDMMC3_R>; 670a674313cSPatrick Delaunay st,idma = <1>; 671a674313cSPatrick Delaunay cap-sd-highspeed; 672a674313cSPatrick Delaunay cap-mmc-highspeed; 673a674313cSPatrick Delaunay max-frequency = <120000000>; 674a674313cSPatrick Delaunay status = "disabled"; 675a674313cSPatrick Delaunay }; 676a674313cSPatrick Delaunay 6778e9c94d7SPatrice Chotard usbotg_hs: usb-otg@49000000 { 6788e9c94d7SPatrice Chotard compatible = "st,stm32mp1-hsotg", "snps,dwc2"; 6798e9c94d7SPatrice Chotard reg = <0x49000000 0x10000>; 6808e9c94d7SPatrice Chotard clocks = <&rcc USBO_K>; 6818e9c94d7SPatrice Chotard clock-names = "otg"; 6828e9c94d7SPatrice Chotard resets = <&rcc USBO_R>; 6838e9c94d7SPatrice Chotard reset-names = "dwc2"; 6848e9c94d7SPatrice Chotard interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 6858e9c94d7SPatrice Chotard g-rx-fifo-size = <256>; 6868e9c94d7SPatrice Chotard g-np-tx-fifo-size = <32>; 6878e9c94d7SPatrice Chotard g-tx-fifo-size = <128 128 64 64 64 64 32 32>; 6888e9c94d7SPatrice Chotard dr_mode = "otg"; 6898e9c94d7SPatrice Chotard power-domains = <&pd_core>; 6908e9c94d7SPatrice Chotard status = "disabled"; 6918e9c94d7SPatrice Chotard }; 6928e9c94d7SPatrice Chotard 693*9119f547SBenjamin Gaignard hwspinlock: hwspinlock@4c000000 { 694*9119f547SBenjamin Gaignard compatible = "st,stm32-hwspinlock"; 695*9119f547SBenjamin Gaignard #hwlock-cells = <1>; 696*9119f547SBenjamin Gaignard reg = <0x4c000000 0x400>; 697*9119f547SBenjamin Gaignard clocks = <&rcc HSEM>; 698*9119f547SBenjamin Gaignard clock-names = "hwspinlock"; 699*9119f547SBenjamin Gaignard status = "disabled"; 700*9119f547SBenjamin Gaignard }; 701*9119f547SBenjamin Gaignard 702a674313cSPatrick Delaunay rcc: rcc@50000000 { 703a674313cSPatrick Delaunay compatible = "st,stm32mp1-rcc", "syscon"; 704a674313cSPatrick Delaunay reg = <0x50000000 0x1000>; 705a674313cSPatrick Delaunay #clock-cells = <1>; 706a674313cSPatrick Delaunay #reset-cells = <1>; 707a674313cSPatrick Delaunay }; 708a674313cSPatrick Delaunay 709a674313cSPatrick Delaunay rcc_reboot: rcc-reboot@50000000 { 710a674313cSPatrick Delaunay compatible = "syscon-reboot"; 711a674313cSPatrick Delaunay regmap = <&rcc>; 712a674313cSPatrick Delaunay offset = <0x404>; 713a674313cSPatrick Delaunay mask = <0x1>; 714a674313cSPatrick Delaunay }; 715a674313cSPatrick Delaunay 716a674313cSPatrick Delaunay pwr: pwr@50001000 { 717a674313cSPatrick Delaunay compatible = "st,stm32mp1-pwr", "st,stm32-pwr", "syscon", "simple-mfd"; 718a674313cSPatrick Delaunay reg = <0x50001000 0x400>; 719a674313cSPatrick Delaunay system-power-controller; 720a674313cSPatrick Delaunay interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 721a674313cSPatrick Delaunay st,sysrcc = <&rcc>; 722a674313cSPatrick Delaunay clocks = <&rcc PLL2_R>; 723a674313cSPatrick Delaunay clock-names = "phyclk"; 724a674313cSPatrick Delaunay 725a674313cSPatrick Delaunay pwr-regulators@c { 726a674313cSPatrick Delaunay compatible = "st,stm32mp1,pwr-reg"; 727a674313cSPatrick Delaunay st,tzcr = <&rcc 0x0 0x1>; 728a674313cSPatrick Delaunay 729a674313cSPatrick Delaunay reg11: reg11 { 730a674313cSPatrick Delaunay regulator-name = "reg11"; 731a674313cSPatrick Delaunay regulator-min-microvolt = <1100000>; 732a674313cSPatrick Delaunay regulator-max-microvolt = <1100000>; 733a674313cSPatrick Delaunay }; 734a674313cSPatrick Delaunay 735a674313cSPatrick Delaunay reg18: reg18 { 736a674313cSPatrick Delaunay regulator-name = "reg18"; 737a674313cSPatrick Delaunay regulator-min-microvolt = <1800000>; 738a674313cSPatrick Delaunay regulator-max-microvolt = <1800000>; 739a674313cSPatrick Delaunay }; 740a674313cSPatrick Delaunay 741a674313cSPatrick Delaunay usb33: usb33 { 742a674313cSPatrick Delaunay regulator-name = "usb33"; 743a674313cSPatrick Delaunay regulator-min-microvolt = <3300000>; 744a674313cSPatrick Delaunay regulator-max-microvolt = <3300000>; 745a674313cSPatrick Delaunay }; 746a674313cSPatrick Delaunay }; 747a674313cSPatrick Delaunay }; 748a674313cSPatrick Delaunay 749a674313cSPatrick Delaunay exti: interrupt-controller@5000d000 { 750a674313cSPatrick Delaunay compatible = "st,stm32mp1-exti", "syscon"; 751a674313cSPatrick Delaunay interrupt-controller; 752a674313cSPatrick Delaunay #interrupt-cells = <2>; 753a674313cSPatrick Delaunay reg = <0x5000d000 0x400>; 754a674313cSPatrick Delaunay }; 755a674313cSPatrick Delaunay 756a674313cSPatrick Delaunay syscfg: system-config@50020000 { 757a674313cSPatrick Delaunay compatible = "st,stm32-syscfg", "syscon"; 758a674313cSPatrick Delaunay reg = <0x50020000 0x400>; 759a674313cSPatrick Delaunay }; 760a674313cSPatrick Delaunay 761a674313cSPatrick Delaunay lptimer2: timer@50021000 { 762a674313cSPatrick Delaunay #address-cells = <1>; 763a674313cSPatrick Delaunay #size-cells = <0>; 764a674313cSPatrick Delaunay compatible = "st,stm32-lptimer"; 765a674313cSPatrick Delaunay reg = <0x50021000 0x400>; 766a674313cSPatrick Delaunay clocks = <&rcc LPTIM2_K>; 767a674313cSPatrick Delaunay clock-names = "mux"; 768a674313cSPatrick Delaunay status = "disabled"; 769a674313cSPatrick Delaunay 770a674313cSPatrick Delaunay pwm { 771a674313cSPatrick Delaunay compatible = "st,stm32-pwm-lp"; 772a674313cSPatrick Delaunay #pwm-cells = <3>; 773a674313cSPatrick Delaunay status = "disabled"; 774a674313cSPatrick Delaunay }; 775a674313cSPatrick Delaunay 776a674313cSPatrick Delaunay trigger@1 { 777a674313cSPatrick Delaunay compatible = "st,stm32-lptimer-trigger"; 778a674313cSPatrick Delaunay reg = <1>; 779a674313cSPatrick Delaunay status = "disabled"; 780a674313cSPatrick Delaunay }; 781a674313cSPatrick Delaunay 782a674313cSPatrick Delaunay counter { 783a674313cSPatrick Delaunay compatible = "st,stm32-lptimer-counter"; 784a674313cSPatrick Delaunay status = "disabled"; 785a674313cSPatrick Delaunay }; 786a674313cSPatrick Delaunay }; 787a674313cSPatrick Delaunay 788a674313cSPatrick Delaunay lptimer3: timer@50022000 { 789a674313cSPatrick Delaunay #address-cells = <1>; 790a674313cSPatrick Delaunay #size-cells = <0>; 791a674313cSPatrick Delaunay compatible = "st,stm32-lptimer"; 792a674313cSPatrick Delaunay reg = <0x50022000 0x400>; 793a674313cSPatrick Delaunay clocks = <&rcc LPTIM3_K>; 794a674313cSPatrick Delaunay clock-names = "mux"; 795a674313cSPatrick Delaunay status = "disabled"; 796a674313cSPatrick Delaunay 797a674313cSPatrick Delaunay pwm { 798a674313cSPatrick Delaunay compatible = "st,stm32-pwm-lp"; 799a674313cSPatrick Delaunay #pwm-cells = <3>; 800a674313cSPatrick Delaunay status = "disabled"; 801a674313cSPatrick Delaunay }; 802a674313cSPatrick Delaunay 803a674313cSPatrick Delaunay trigger@2 { 804a674313cSPatrick Delaunay compatible = "st,stm32-lptimer-trigger"; 805a674313cSPatrick Delaunay reg = <2>; 806a674313cSPatrick Delaunay status = "disabled"; 807a674313cSPatrick Delaunay }; 808a674313cSPatrick Delaunay }; 809a674313cSPatrick Delaunay 810a674313cSPatrick Delaunay lptimer4: timer@50023000 { 811a674313cSPatrick Delaunay compatible = "st,stm32-lptimer"; 812a674313cSPatrick Delaunay reg = <0x50023000 0x400>; 813a674313cSPatrick Delaunay clocks = <&rcc LPTIM4_K>; 814a674313cSPatrick Delaunay clock-names = "mux"; 815a674313cSPatrick Delaunay status = "disabled"; 816a674313cSPatrick Delaunay 817a674313cSPatrick Delaunay pwm { 818a674313cSPatrick Delaunay compatible = "st,stm32-pwm-lp"; 819a674313cSPatrick Delaunay #pwm-cells = <3>; 820a674313cSPatrick Delaunay status = "disabled"; 821a674313cSPatrick Delaunay }; 822a674313cSPatrick Delaunay }; 823a674313cSPatrick Delaunay 824a674313cSPatrick Delaunay lptimer5: timer@50024000 { 825a674313cSPatrick Delaunay compatible = "st,stm32-lptimer"; 826a674313cSPatrick Delaunay reg = <0x50024000 0x400>; 827a674313cSPatrick Delaunay clocks = <&rcc LPTIM5_K>; 828a674313cSPatrick Delaunay clock-names = "mux"; 829a674313cSPatrick Delaunay status = "disabled"; 830a674313cSPatrick Delaunay 831a674313cSPatrick Delaunay pwm { 832a674313cSPatrick Delaunay compatible = "st,stm32-pwm-lp"; 833a674313cSPatrick Delaunay #pwm-cells = <3>; 834a674313cSPatrick Delaunay status = "disabled"; 835a674313cSPatrick Delaunay }; 836a674313cSPatrick Delaunay }; 837a674313cSPatrick Delaunay 838a674313cSPatrick Delaunay vrefbuf: vrefbuf@50025000 { 839a674313cSPatrick Delaunay compatible = "st,stm32-vrefbuf"; 840a674313cSPatrick Delaunay reg = <0x50025000 0x8>; 841a674313cSPatrick Delaunay regulator-min-microvolt = <1500000>; 842a674313cSPatrick Delaunay regulator-max-microvolt = <2500000>; 843a674313cSPatrick Delaunay clocks = <&rcc VREF>; 844a674313cSPatrick Delaunay status = "disabled"; 845a674313cSPatrick Delaunay }; 846a674313cSPatrick Delaunay 847a674313cSPatrick Delaunay cryp1: cryp@54001000 { 848a674313cSPatrick Delaunay compatible = "st,stm32mp1-cryp"; 849a674313cSPatrick Delaunay reg = <0x54001000 0x400>; 850a674313cSPatrick Delaunay interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 851a674313cSPatrick Delaunay clocks = <&rcc CRYP1>; 852a674313cSPatrick Delaunay resets = <&rcc CRYP1_R>; 853a674313cSPatrick Delaunay status = "disabled"; 854a674313cSPatrick Delaunay }; 855a674313cSPatrick Delaunay 856a674313cSPatrick Delaunay rng1: rng@54003000 { 857a674313cSPatrick Delaunay compatible = "st,stm32-rng"; 858a674313cSPatrick Delaunay reg = <0x54003000 0x400>; 859a674313cSPatrick Delaunay clocks = <&rcc RNG1_K>; 860a674313cSPatrick Delaunay resets = <&rcc RNG1_R>; 861a674313cSPatrick Delaunay status = "disabled"; 862a674313cSPatrick Delaunay }; 863a674313cSPatrick Delaunay 864a674313cSPatrick Delaunay mdma1: dma@58000000 { 865a674313cSPatrick Delaunay compatible = "st,stm32h7-mdma"; 866a674313cSPatrick Delaunay reg = <0x58000000 0x1000>; 867a674313cSPatrick Delaunay interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 868a674313cSPatrick Delaunay clocks = <&rcc MDMA>; 869a674313cSPatrick Delaunay #dma-cells = <5>; 870a674313cSPatrick Delaunay dma-channels = <32>; 871a674313cSPatrick Delaunay dma-requests = <48>; 872a674313cSPatrick Delaunay }; 873a674313cSPatrick Delaunay 874a674313cSPatrick Delaunay qspi: qspi@58003000 { 875a674313cSPatrick Delaunay compatible = "st,stm32f469-qspi"; 876a674313cSPatrick Delaunay reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; 877a674313cSPatrick Delaunay reg-names = "qspi", "qspi_mm"; 878a674313cSPatrick Delaunay interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 879a674313cSPatrick Delaunay clocks = <&rcc QSPI_K>; 880a674313cSPatrick Delaunay resets = <&rcc QSPI_R>; 881a674313cSPatrick Delaunay status = "disabled"; 882a674313cSPatrick Delaunay }; 883a674313cSPatrick Delaunay 884a674313cSPatrick Delaunay sdmmc1: sdmmc@58005000 { 885a674313cSPatrick Delaunay compatible = "st,stm32-sdmmc2"; 886a674313cSPatrick Delaunay reg = <0x58005000 0x1000>, <0x58006000 0x1000>; 887a674313cSPatrick Delaunay reg-names = "sdmmc", "delay"; 888a674313cSPatrick Delaunay clocks = <&rcc SDMMC1_K>; 889a674313cSPatrick Delaunay resets = <&rcc SDMMC1_R>; 890a674313cSPatrick Delaunay st,idma = <1>; 891a674313cSPatrick Delaunay cap-sd-highspeed; 892a674313cSPatrick Delaunay cap-mmc-highspeed; 893a674313cSPatrick Delaunay max-frequency = <120000000>; 894a674313cSPatrick Delaunay status = "disabled"; 895a674313cSPatrick Delaunay }; 896a674313cSPatrick Delaunay 897a674313cSPatrick Delaunay sdmmc2: sdmmc@58007000 { 898a674313cSPatrick Delaunay compatible = "st,stm32-sdmmc2"; 899a674313cSPatrick Delaunay reg = <0x58007000 0x1000>, <0x58008000 0x1000>; 900a674313cSPatrick Delaunay reg-names = "sdmmc", "delay"; 901a674313cSPatrick Delaunay interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>; 902a674313cSPatrick Delaunay clocks = <&rcc SDMMC2_K>; 903a674313cSPatrick Delaunay resets = <&rcc SDMMC2_R>; 904a674313cSPatrick Delaunay st,idma = <1>; 905a674313cSPatrick Delaunay cap-sd-highspeed; 906a674313cSPatrick Delaunay cap-mmc-highspeed; 907a674313cSPatrick Delaunay max-frequency = <120000000>; 908a674313cSPatrick Delaunay status = "disabled"; 909a674313cSPatrick Delaunay }; 910a674313cSPatrick Delaunay 911a674313cSPatrick Delaunay crc1: crc@58009000 { 912a674313cSPatrick Delaunay compatible = "st,stm32f7-crc"; 913a674313cSPatrick Delaunay reg = <0x58009000 0x400>; 914a674313cSPatrick Delaunay clocks = <&rcc CRC1>; 915a674313cSPatrick Delaunay status = "disabled"; 916a674313cSPatrick Delaunay }; 917a674313cSPatrick Delaunay 918a674313cSPatrick Delaunay usbh_ohci: usbh-ohci@5800c000 { 919a674313cSPatrick Delaunay compatible = "generic-ohci"; 920a674313cSPatrick Delaunay reg = <0x5800c000 0x1000>; 921a674313cSPatrick Delaunay clocks = <&rcc USBH>; 922a674313cSPatrick Delaunay resets = <&rcc USBH_R>; 923a674313cSPatrick Delaunay interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 924a674313cSPatrick Delaunay status = "disabled"; 925a674313cSPatrick Delaunay }; 926a674313cSPatrick Delaunay 927a674313cSPatrick Delaunay usbh_ehci: usbh-ehci@5800d000 { 928a674313cSPatrick Delaunay compatible = "generic-ehci"; 929a674313cSPatrick Delaunay reg = <0x5800d000 0x1000>; 930a674313cSPatrick Delaunay clocks = <&rcc USBH>; 931a674313cSPatrick Delaunay resets = <&rcc USBH_R>; 932a674313cSPatrick Delaunay interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 933a674313cSPatrick Delaunay companion = <&usbh_ohci>; 934a674313cSPatrick Delaunay status = "disabled"; 935a674313cSPatrick Delaunay }; 936a674313cSPatrick Delaunay 937a674313cSPatrick Delaunay dsi: dsi@5a000000 { 938a674313cSPatrick Delaunay compatible = "st,stm32-dsi"; 939a674313cSPatrick Delaunay reg = <0x5a000000 0x800>; 940a674313cSPatrick Delaunay clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; 941a674313cSPatrick Delaunay clock-names = "pclk", "ref", "px_clk"; 942a674313cSPatrick Delaunay resets = <&rcc DSI_R>; 943a674313cSPatrick Delaunay reset-names = "apb"; 944a674313cSPatrick Delaunay status = "disabled"; 945a674313cSPatrick Delaunay }; 946a674313cSPatrick Delaunay 947a674313cSPatrick Delaunay ltdc: display-controller@5a001000 { 948a674313cSPatrick Delaunay compatible = "st,stm32-ltdc"; 949a674313cSPatrick Delaunay reg = <0x5a001000 0x400>; 950a674313cSPatrick Delaunay interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 951a674313cSPatrick Delaunay <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 952a674313cSPatrick Delaunay clocks = <&rcc LTDC_PX>; 953a674313cSPatrick Delaunay clock-names = "lcd"; 954a674313cSPatrick Delaunay resets = <&rcc LTDC_R>; 955a674313cSPatrick Delaunay status = "disabled"; 956a674313cSPatrick Delaunay }; 957a674313cSPatrick Delaunay 958a674313cSPatrick Delaunay usbphyc: usbphyc@5a006000 { 959a674313cSPatrick Delaunay #address-cells = <1>; 960a674313cSPatrick Delaunay #size-cells = <0>; 961a674313cSPatrick Delaunay compatible = "st,stm32mp1-usbphyc"; 962a674313cSPatrick Delaunay reg = <0x5a006000 0x1000>; 963a674313cSPatrick Delaunay clocks = <&rcc USBPHY_K>; 964a674313cSPatrick Delaunay resets = <&rcc USBPHY_R>; 965a674313cSPatrick Delaunay status = "disabled"; 966a674313cSPatrick Delaunay 967a674313cSPatrick Delaunay usbphyc_port0: usb-phy@0 { 968a674313cSPatrick Delaunay #phy-cells = <0>; 969a674313cSPatrick Delaunay reg = <0>; 970a674313cSPatrick Delaunay }; 971a674313cSPatrick Delaunay 972a674313cSPatrick Delaunay usbphyc_port1: usb-phy@1 { 973a674313cSPatrick Delaunay #phy-cells = <1>; 974a674313cSPatrick Delaunay reg = <1>; 975a674313cSPatrick Delaunay }; 976a674313cSPatrick Delaunay }; 977a674313cSPatrick Delaunay 978a674313cSPatrick Delaunay usart1: serial@5c000000 { 979a674313cSPatrick Delaunay compatible = "st,stm32h7-uart"; 980a674313cSPatrick Delaunay reg = <0x5c000000 0x400>; 981a674313cSPatrick Delaunay interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 982a674313cSPatrick Delaunay clocks = <&rcc USART1_K>; 983a674313cSPatrick Delaunay status = "disabled"; 984a674313cSPatrick Delaunay }; 985a674313cSPatrick Delaunay 986a674313cSPatrick Delaunay i2c4: i2c@5c002000 { 987a674313cSPatrick Delaunay compatible = "st,stm32f7-i2c"; 988a674313cSPatrick Delaunay reg = <0x5c002000 0x400>; 989a674313cSPatrick Delaunay interrupt-names = "event", "error"; 990a674313cSPatrick Delaunay interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 991a674313cSPatrick Delaunay <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 992a674313cSPatrick Delaunay clocks = <&rcc I2C4_K>; 993a674313cSPatrick Delaunay resets = <&rcc I2C4_R>; 994a674313cSPatrick Delaunay #address-cells = <1>; 995a674313cSPatrick Delaunay #size-cells = <0>; 996a674313cSPatrick Delaunay status = "disabled"; 997a674313cSPatrick Delaunay }; 998a674313cSPatrick Delaunay 999a674313cSPatrick Delaunay i2c6: i2c@5c009000 { 1000a674313cSPatrick Delaunay compatible = "st,stm32f7-i2c"; 1001a674313cSPatrick Delaunay reg = <0x5c009000 0x400>; 1002a674313cSPatrick Delaunay interrupt-names = "event", "error"; 1003a674313cSPatrick Delaunay interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1004a674313cSPatrick Delaunay <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1005a674313cSPatrick Delaunay clocks = <&rcc I2C6_K>; 1006a674313cSPatrick Delaunay resets = <&rcc I2C6_R>; 1007a674313cSPatrick Delaunay #address-cells = <1>; 1008a674313cSPatrick Delaunay #size-cells = <0>; 1009a674313cSPatrick Delaunay status = "disabled"; 1010a674313cSPatrick Delaunay }; 1011a674313cSPatrick Delaunay }; 1012a674313cSPatrick Delaunay}; 1013