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Searched +full:sgmii +full:- +full:enable +full:- +full:pll (Results 1 – 25 of 39) sorted by relevance

12

/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm958625-meraki-alamo.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
5 * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
8 #include "bcm958625-meraki-mx6x-common.dtsi"
12 compatible = "gpio-keys-polled";
14 poll-interval = <20>;
16 button-reset {
24 compatible = "gpio-leds";
26 led-0 {
27 /* green:wan1-left */
29 function-enumerator = <0>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/dsa/
H A Dqca8k.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Crispin <john@phrozen.org>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
20 mdio-bus configurations are not supported by the hardware.
27 - enum:
28 - qca,qca8327
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/openbmc/u-boot/arch/arm/mach-mvebu/serdes/a38x/
H A Dhigh_speed_env_spec.c1 // SPDX-License-Identifier: GPL-2.0
24 * serdes_seq_db - holds all serdes sequences, their size and the
30 #define ENDED_OK "High speed PHY - Ended Successfully\n"
63 /* Selector mapping for A380-A0 and A390-Z1 */
144 * SATA and SGMII
158 /* Rx clk and Tx clk select non-inverted mode */
177 /* Rx clk and Tx clk select non-inverted mode */
185 /* SATA and SGMII - power up seq */
188 * unit_base_reg, unit_offset, mask, SATA data, SGMII data,
202 /* SATA and SGMII - speed config seq */
[all …]
/openbmc/linux/drivers/phy/freescale/
H A Dphy-fsl-lynx-28g.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (c) 2021-2022 NXP. */
24 #define LYNX_28G_LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1))
26 /* Per PLL registers */
27 #define LYNX_28G_PLLnRSTCTL(pll) (0x400 + (pll) * 0x100 + 0x0) argument
31 #define LYNX_28G_PLLnCR0(pll) (0x400 + (pll) * 0x100 + 0x4) argument
39 #define LYNX_28G_PLLnCR1(pll) (0x400 + (pll) * 0x100 + 0x8) argument
134 struct lynx_28g_pll pll[LYNX_28G_NUM_PLL]; member
143 void __iomem *reg = priv->base + off; in lynx_28g_rmw()
153 lynx_28g_rmw((lane)->priv, LYNX_28G_##reg(lane->id), \
[all …]
/openbmc/linux/drivers/phy/xilinx/
H A Dphy-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
5 * Copyright (C) 2018-2020 Xilinx Inc.
11 * This driver is tested for USB, SGMII, SATA and Display Port currently.
26 #include <dt-bindings/phy/phy.h>
32 /* TX De-emphasis parameters */
57 /* PLL Test Mode register parameters */
61 /* PLL SSC step size offsets */
161 #define XPSGTR_TYPE_SGMII0 10 /* Ethernet SGMII controller 0 */
162 #define XPSGTR_TYPE_SGMII1 11 /* Ethernet SGMII controller 1 */
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dfsl_corenet_serdes.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
19 * The work-arounds for erratum SERDES8 and SERDES-A001 are linked together.
114 if (in_be32(&regs->bank[bank].rstctl) & SRDS_RSTCTL_SDPD) in serdes_lane_enabled()
124 return !(srds_lpd_b[bank] & (8 >> (lane - (6 + 4 * bank)))); in serdes_lane_enabled()
127 return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit)); in serdes_lane_enabled()
135 if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) in is_serdes_configured()
153 return -ENODEV; in __serdes_get_first_lane()
157 * Returns the SERDES lane (0..SRDS_MAX_LANES-1) that routes to the given
171 if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) in serdes_get_first_lane()
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/openbmc/u-boot/drivers/phy/marvell/
H A Dcomphy_a3700.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Marvell International Ltd.
67 /*-----------------------------------------------------------*/
144 for (timeout = PLL_LOCK_TIMEOUT; timeout > 0; timeout--) { in comphy_poll_reg()
163 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
172 * 1. Enable max PLL. in comphy_pcie_power_up()
192 * 5. Enable idle sync in comphy_pcie_power_up()
197 * 6. Enable the output of 100M/125M/500M clock in comphy_pcie_power_up()
203 * 7. Enable TX in comphy_pcie_power_up()
208 * 8. Check crystal jumper setting and program the Power and PLL in comphy_pcie_power_up()
[all …]
H A Dcomphy_cp110.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Marvell International Ltd.
31 * For CP-110 we have 2 Selector registers "PHY Selectors",
78 } while (data != val && --usec_timout > 0); in polling_with_timeout()
100 * Add SAR (Sample-At-Reset) configuration for the PCIe clock in comphy_pcie_power_up()
102 * U-Boot to mainline version. in comphy_pcie_power_up()
104 * SerDes Lane 4/5 got the PCIe ref-clock #1, in comphy_pcie_power_up()
105 * and SerDes Lane 0 got PCIe ref-clock #0 in comphy_pcie_power_up()
111 /* enable PCIe by4 and by2 */ in comphy_pcie_power_up()
126 * we need to configure the clock-source MUX. in comphy_pcie_power_up()
[all …]
/openbmc/u-boot/board/freescale/common/
H A Dpixis.c1 // SPDX-License-Identifier: GPL-2.0+
158 * The PIXIS can be programmed to look at either the on-board dip switches
186 * The PIXIS can be programmed to look at either the on-board dip switches
190 * to ignore the on-board dip switches and use the PX_VBOOT[LBMAP] instead.
260 /* Enable the watchdog and reboot by starting the VELA sequencer */ in set_px_go_with_watchdog()
286 /* Enable or disable SGMII mode for a TSEC
290 int which_tsec = -1; in pixis_set_sgmii()
329 if (!strcmp(argv[argc - 1], "switch")) in pixis_set_sgmii()
334 /* If it's not the switches, enable or disable SGMII, as specified */ in pixis_set_sgmii()
335 if (!strcmp(argv[argc - 1], "on")) in pixis_set_sgmii()
[all …]
/openbmc/u-boot/drivers/soc/keystone/
H A Dkeystone_serdes.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <asm/ti-common/keystone_serdes.h>
49 /* SERDES PHY lane enable configuration value, indexed by PHY interface */
51 0xf000f0c0, /* SGMII */
55 /* SERDES PHY PLL enable configuration value, indexed by PHY interface */
57 0xe0000000, /* SGMII */
130 ks2_serdes_cfg_setup(base, cfg->cmu, SERDES_CMU_CFG_NUM); in ks2_serdes_init_cfg()
131 ks2_serdes_cfg_setup(base, cfg->comlane, SERDES_COMLANE_CFG_NUM); in ks2_serdes_init_cfg()
134 ks2_serdes_lane_config(base, cfg->lane, SERDES_LANE_CFG_NUM, i); in ks2_serdes_init_cfg()
143 if (serdes->intf == SERDES_PHY_PCSR) in ks2_serdes_cmu_comlane_enable()
[all …]
/openbmc/linux/drivers/net/phy/
H A Dbcm54140.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Broadcom BCM54140 Quad SGMII/QSGMII Copper/Fiber Gigabit PHY
13 #include "bcm-phy-lib.h"
15 /* RDB per-port registers
35 #define BCM54140_RDB_C_APWR_APD_MODE_EN 1 /* ADP enable */
37 #define BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG 3 /* ADP enable w/ aneg */
45 #define BCM54140_RDB_C_MISC_CTRL_WS_EN BIT(4) /* wirespeed enable */
60 #define BCM54140_RDB_MON_CTRL_SEL_RR 3 /* meassure all round-robin */
61 #define BCM54140_RDB_MON_CTRL_PWR_DOWN BIT(0) /* power-down monitor */
80 * T = 413.35 - (0.49055 * bits[9:0])
[all …]
H A Dat803x.c1 // SPDX-License-Identifier: GPL-2.0+
23 #include <dt-bindings/net/qca-ar803x.h>
103 #define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
130 /* AT803x supports either the XTAL input pad, an internal PLL or the
132 * is only used for 25 MHz output, all other frequencies need the PLL.
136 * By default the PLL is only enabled if there is a link. Otherwise
137 * the PHY will go into low power state and disabled the PLL. You can
138 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
153 * but doesn't support choosing between XTAL/PLL and DSP.
191 /* don't turn off internal PLL */
[all …]
/openbmc/linux/drivers/net/dsa/qca/
H A Dqca8k-8xxx.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
47 ret = bus->write(bus, phy_id, regnum, lo); in qca8k_mii_write_lo()
49 dev_err_ratelimited(&bus->dev, in qca8k_mii_write_lo()
62 ret = bus->write(bus, phy_id, regnum, hi); in qca8k_mii_write_hi()
64 dev_err_ratelimited(&bus->dev, in qca8k_mii_write_hi()
75 ret = bus->read(bus, phy_id, regnum); in qca8k_mii_read_lo()
83 dev_err_ratelimited(&bus->dev, in qca8k_mii_read_lo()
95 ret = bus->read(bus, phy_id, regnum); in qca8k_mii_read_hi()
103 dev_err_ratelimited(&bus->dev, in qca8k_mii_read_hi()
[all …]
/openbmc/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
41 * since the registers are 16-bit.
184 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f))
189 * (used only by SGMII code)
210 * (used only by SGMII code)
301 /*-----------------------------------------------------------*/
392 priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_ADDR); in comphy_set_indirect()
393 comphy_reg_set(priv->lane2_phy_indirect + COMPHY_LANE2_INDIR_DATA, in comphy_set_indirect()
400 if (lane->id == 2) { in comphy_lane_reg_set()
[all …]
/openbmc/linux/drivers/net/phy/mscc/
H A Dmscc_serdes.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
25 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in pll5g_detune()
39 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in pll5g_tune()
56 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_pll_cfg_wr()
72 /* qrate = 1 for SGMII, 0 for QSGMII */ in vsc85xx_sd6g_common_cfg_wr()
73 /* if_mode = 1 for SGMII, 3 for QSGMII */ in vsc85xx_sd6g_common_cfg_wr()
85 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_common_cfg_wr()
109 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_des_cfg_wr()
134 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_ib_cfg0_wr()
158 dev_err(&phydev->mdio.dev, "%s: write error\n", __func__); in vsc85xx_sd6g_ib_cfg1_wr()
[all …]
/openbmc/linux/drivers/net/dsa/
H A Dmt7530.h1 /* SPDX-License-Identifier: GPL-2.0-only */
15 #define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN)
300 /* Register for port port-and-protocol based vlan 1 control */
403 /* MT7531 SGMII register group */
404 #define MT7531_SGMII_REG_BASE(p) (0x5000 + ((p) - 5) * 0x1000)
540 /* Registers for RGMII and SGMII PLL clock */
602 /* LED enable, 0: Disable, 1: Enable (Default) */
608 /* GPIO output enable, 0: Disable, 1: Enable */
621 /* Registers for core PLL access through mmd indirect */
699 /* struct mt7530_port - This is the main data structure for holding the state
[all …]
H A Dmt7530.c1 // SPDX-License-Identifier: GPL-2.0-only
85 struct mii_bus *bus = priv->bus; in core_read_mmd_indirect()
89 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); in core_read_mmd_indirect()
94 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); in core_read_mmd_indirect()
99 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); in core_read_mmd_indirect()
104 value = bus->read(bus, 0, MII_MMD_DATA); in core_read_mmd_indirect()
108 dev_err(&bus->dev, "failed to read mmd register\n"); in core_read_mmd_indirect()
117 struct mii_bus *bus = priv->bus; in core_write_mmd_indirect()
121 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); in core_write_mmd_indirect()
126 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); in core_write_mmd_indirect()
[all …]
/openbmc/linux/drivers/net/ethernet/intel/igb/
H A De1000_82575.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
61 * igb_write_vfta_i350 - Write value to VLAN filter table
71 struct igb_adapter *adapter = hw->back; in igb_write_vfta_i350()
74 for (i = 10; i--;) in igb_write_vfta_i350()
78 adapter->shadow_vfta[offset] = value; in igb_write_vfta_i350()
82 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
93 switch (hw->mac.type) { in igb_sgmii_uses_mdio_82575()
114 * igb_check_for_link_media_swap - Check which M88E1112 interface linked
121 struct e1000_phy_info *phy = &hw->phy; in igb_check_for_link_media_swap()
[all …]
/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-intel.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/clk-provider.h>
8 #include "dwmac-intel.h"
44 int func = PCI_FUNC(pdev->devfn); in stmmac_pci_find_phy_addr()
49 return -ENODEV; in stmmac_pci_find_phy_addr()
51 dmi_data = dmi_id->driver_data; in stmmac_pci_find_phy_addr()
52 func_data = dmi_data->func; in stmmac_pci_find_phy_addr()
54 for (n = 0; n < dmi_data->nfuncs; n++, func_data++) in stmmac_pci_find_phy_addr()
55 if (func_data->func == func) in stmmac_pci_find_phy_addr()
56 return func_data->phy_addr; in stmmac_pci_find_phy_addr()
[all …]
/openbmc/linux/drivers/net/dsa/sja1105/
H A Dsja1105_clocking.c1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright 2016-2018 NXP
3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
107 sja1105_packing(buf, &idiv->clksrc, 28, 24, size, op); in sja1105_cgu_idiv_packing()
108 sja1105_packing(buf, &idiv->autoblock, 11, 11, size, op); in sja1105_cgu_idiv_packing()
109 sja1105_packing(buf, &idiv->idiv, 5, 2, size, op); in sja1105_cgu_idiv_packing()
110 sja1105_packing(buf, &idiv->pd, 0, 0, size, op); in sja1105_cgu_idiv_packing()
116 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cgu_idiv_config()
117 struct device *dev = priv->ds->dev; in sja1105_cgu_idiv_config()
121 if (regs->cgu_idiv[port] == SJA1105_RSV_ADDR) in sja1105_cgu_idiv_config()
[all …]
/openbmc/linux/drivers/phy/mediatek/
H A Dphy-mtk-tphy.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/phy/phy.h>
15 #include <linux/nvmem-consumer.h>
22 #include "phy-mtk-io.h"
24 /* version V1 sub-banks offset base address */
35 /* version V2/V3 sub-banks offset base address */
216 /* CDR Charge Pump P-path current adjustment */
235 /* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */
244 /* I-path capacitance adjustment for Gen1 */
258 /* PHY switch between pcie/usb3/sgmii/sata */
[all …]
/openbmc/linux/drivers/phy/
H A Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
11 * The first PLL clock macro is used for internal reference clock. The second
12 * PLL clock macro is used to generate the clock for the PHY. This driver
13 * configures the first PLL CMU, the second PLL CMU, and programs the PHY to
14 * operate according to the mode of operation. The first PLL CMU is only
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
[all …]
/openbmc/linux/drivers/phy/cadence/
H A Dphy-cadence-torrent.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/phy/phy-cadence.h>
12 #include <linux/clk-provider.h>
239 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver",
240 [CDNS_TORRENT_DERIVED_REFCLK] = "refclk-der",
241 [CDNS_TORRENT_RECEIVED_REFCLK] = "refclk-rec",
464 for (i = 0; i < tbl->num_entries; i++) { in cdns_torrent_get_tbl_vals()
465 if (tbl->entries[i].key == key) in cdns_torrent_get_tbl_vals()
466 return tbl->entries[i].vals; in cdns_torrent_get_tbl_vals()
[all …]
/openbmc/u-boot/drivers/net/ti/
H A Dkeystone_net.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2012-2014
20 #include <asm/ti-common/keystone_nav.h>
21 #include <asm/ti-common/keystone_net.h>
22 #include <asm/ti-common/keystone_serdes.h>
32 #define emac_gigabit_enable(x) /* no gigabit to enable */
108 * Check if link detected is giga-bit in keystone2_eth_gigabit_enable()
109 * If Gigabit mode detected, enable gigbit in MAC in keystone2_eth_gigabit_enable()
111 if (priv->has_mdio) { in keystone2_eth_gigabit_enable()
112 if (priv->phydev->speed != 1000) in keystone2_eth_gigabit_enable()
[all …]
/openbmc/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-phy-v2.c125 #include "xgbe-common.h"
149 /* Rate-change complete wait/retry count */
276 ((_x)->extd[XGBE_SFP_EXTD_SFF_8472] && \
277 !((_x)->extd[XGBE_SFP_EXTD_DIAG] & XGBE_SFP_EXTD_DIAG_ADDR_CHANGE))
284 #define XGBE_BEL_FUSE_VENDOR "BEL-FUSE "
285 #define XGBE_BEL_FUSE_PARTNO "1GBT-SFP06 "
306 /* Re-driver related definitions */
375 /* Re-driver support */
399 return pdata->i2c_if.i2c_xfer(pdata, i2c_op); in xgbe_phy_i2c_xfer()
405 struct xgbe_phy_data *phy_data = pdata->phy_data; in xgbe_phy_redrv_write()
[all …]

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