1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2015-2016 Marvell International Ltd.
4 */
5
6 #include <common.h>
7 #include <fdtdec.h>
8 #include <asm/io.h>
9 #include <asm/arch/cpu.h>
10 #include <asm/arch/soc.h>
11
12 #include "comphy_a3700.h"
13
14 DECLARE_GLOBAL_DATA_PTR;
15
16 struct comphy_mux_data a3700_comphy_mux_data[] = {
17 /* Lane 0 */
18 {
19 4,
20 {
21 { PHY_TYPE_UNCONNECTED, 0x0 },
22 { PHY_TYPE_SGMII1, 0x0 },
23 { PHY_TYPE_USB3_HOST0, 0x1 },
24 { PHY_TYPE_USB3_DEVICE, 0x1 }
25 }
26 },
27 /* Lane 1 */
28 {
29 3,
30 {
31 { PHY_TYPE_UNCONNECTED, 0x0},
32 { PHY_TYPE_SGMII0, 0x0},
33 { PHY_TYPE_PEX0, 0x1}
34 }
35 },
36 /* Lane 2 */
37 {
38 4,
39 {
40 { PHY_TYPE_UNCONNECTED, 0x0},
41 { PHY_TYPE_SATA0, 0x0},
42 { PHY_TYPE_USB3_HOST0, 0x1},
43 { PHY_TYPE_USB3_DEVICE, 0x1}
44 }
45 },
46 };
47
48 struct sgmii_phy_init_data_fix {
49 u16 addr;
50 u16 value;
51 };
52
53 /* Changes to 40M1G25 mode data required for running 40M3G125 init mode */
54 static struct sgmii_phy_init_data_fix sgmii_phy_init_fix[] = {
55 {0x005, 0x07CC}, {0x015, 0x0000}, {0x01B, 0x0000}, {0x01D, 0x0000},
56 {0x01E, 0x0000}, {0x01F, 0x0000}, {0x020, 0x0000}, {0x021, 0x0030},
57 {0x026, 0x0888}, {0x04D, 0x0152}, {0x04F, 0xA020}, {0x050, 0x07CC},
58 {0x053, 0xE9CA}, {0x055, 0xBD97}, {0x071, 0x3015}, {0x076, 0x03AA},
59 {0x07C, 0x0FDF}, {0x0C2, 0x3030}, {0x0C3, 0x8000}, {0x0E2, 0x5550},
60 {0x0E3, 0x12A4}, {0x0E4, 0x7D00}, {0x0E6, 0x0C83}, {0x101, 0xFCC0},
61 {0x104, 0x0C10}
62 };
63
64 /* 40M1G25 mode init data */
65 static u16 sgmii_phy_init[512] = {
66 /* 0 1 2 3 4 5 6 7 */
67 /*-----------------------------------------------------------*/
68 /* 8 9 A B C D E F */
69 0x3110, 0xFD83, 0x6430, 0x412F, 0x82C0, 0x06FA, 0x4500, 0x6D26, /* 00 */
70 0xAFC0, 0x8000, 0xC000, 0x0000, 0x2000, 0x49CC, 0x0BC9, 0x2A52, /* 08 */
71 0x0BD2, 0x0CDE, 0x13D2, 0x0CE8, 0x1149, 0x10E0, 0x0000, 0x0000, /* 10 */
72 0x0000, 0x0000, 0x0000, 0x0001, 0x0000, 0x4134, 0x0D2D, 0xFFFF, /* 18 */
73 0xFFE0, 0x4030, 0x1016, 0x0030, 0x0000, 0x0800, 0x0866, 0x0000, /* 20 */
74 0x0000, 0x0000, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF, /* 28 */
75 0xFFFF, 0xFFFF, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* 30 */
76 0x0000, 0x0000, 0x000F, 0x6A62, 0x1988, 0x3100, 0x3100, 0x3100, /* 38 */
77 0x3100, 0xA708, 0x2430, 0x0830, 0x1030, 0x4610, 0xFF00, 0xFF00, /* 40 */
78 0x0060, 0x1000, 0x0400, 0x0040, 0x00F0, 0x0155, 0x1100, 0xA02A, /* 48 */
79 0x06FA, 0x0080, 0xB008, 0xE3ED, 0x5002, 0xB592, 0x7A80, 0x0001, /* 50 */
80 0x020A, 0x8820, 0x6014, 0x8054, 0xACAA, 0xFC88, 0x2A02, 0x45CF, /* 58 */
81 0x000F, 0x1817, 0x2860, 0x064F, 0x0000, 0x0204, 0x1800, 0x6000, /* 60 */
82 0x810F, 0x4F23, 0x4000, 0x4498, 0x0850, 0x0000, 0x000E, 0x1002, /* 68 */
83 0x9D3A, 0x3009, 0xD066, 0x0491, 0x0001, 0x6AB0, 0x0399, 0x3780, /* 70 */
84 0x0040, 0x5AC0, 0x4A80, 0x0000, 0x01DF, 0x0000, 0x0007, 0x0000, /* 78 */
85 0x2D54, 0x00A1, 0x4000, 0x0100, 0xA20A, 0x0000, 0x0000, 0x0000, /* 80 */
86 0x0000, 0x0000, 0x0000, 0x7400, 0x0E81, 0x1000, 0x1242, 0x0210, /* 88 */
87 0x80DF, 0x0F1F, 0x2F3F, 0x4F5F, 0x6F7F, 0x0F1F, 0x2F3F, 0x4F5F, /* 90 */
88 0x6F7F, 0x4BAD, 0x0000, 0x0000, 0x0800, 0x0000, 0x2400, 0xB651, /* 98 */
89 0xC9E0, 0x4247, 0x0A24, 0x0000, 0xAF19, 0x1004, 0x0000, 0x0000, /* A0 */
90 0x0000, 0x0013, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* A8 */
91 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /* B0 */
92 0x0000, 0x0000, 0x0000, 0x0060, 0x0000, 0x0000, 0x0000, 0x0000, /* B8 */
93 0x0000, 0x0000, 0x3010, 0xFA00, 0x0000, 0x0000, 0x0000, 0x0003, /* C0 */
94 0x1618, 0x8200, 0x8000, 0x0400, 0x050F, 0x0000, 0x0000, 0x0000, /* C8 */
95 0x4C93, 0x0000, 0x1000, 0x1120, 0x0010, 0x1242, 0x1242, 0x1E00, /* D0 */
96 0x0000, 0x0000, 0x0000, 0x00F8, 0x0000, 0x0041, 0x0800, 0x0000, /* D8 */
97 0x82A0, 0x572E, 0x2490, 0x14A9, 0x4E00, 0x0000, 0x0803, 0x0541, /* E0 */
98 0x0C15, 0x0000, 0x0000, 0x0400, 0x2626, 0x0000, 0x0000, 0x4200, /* E8 */
99 0x0000, 0xAA55, 0x1020, 0x0000, 0x0000, 0x5010, 0x0000, 0x0000, /* F0 */
100 0x0000, 0x0000, 0x5000, 0x0000, 0x0000, 0x0000, 0x02F2, 0x0000, /* F8 */
101 0x101F, 0xFDC0, 0x4000, 0x8010, 0x0110, 0x0006, 0x0000, 0x0000, /*100 */
102 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*108 */
103 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04CF, 0x0000, 0x04C6, 0x0000, /*110 */
104 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*118 */
105 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*120 */
106 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*128 */
107 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*130 */
108 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*138 */
109 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*140 */
110 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*148 */
111 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*150 */
112 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*158 */
113 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*160 */
114 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*168 */
115 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*170 */
116 0x0000, 0x0000, 0x0000, 0x00F0, 0x08A2, 0x3112, 0x0A14, 0x0000, /*178 */
117 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*180 */
118 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*188 */
119 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*190 */
120 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*198 */
121 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A0 */
122 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1A8 */
123 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B0 */
124 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1B8 */
125 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C0 */
126 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1C8 */
127 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D0 */
128 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1D8 */
129 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E0 */
130 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1E8 */
131 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, /*1F0 */
132 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */
133 };
134
135 /*
136 * comphy_poll_reg
137 *
138 * return: 1 on success, 0 on timeout
139 */
comphy_poll_reg(void * addr,u32 val,u32 mask,u8 op_type)140 static u32 comphy_poll_reg(void *addr, u32 val, u32 mask, u8 op_type)
141 {
142 u32 rval = 0xDEAD, timeout;
143
144 for (timeout = PLL_LOCK_TIMEOUT; timeout > 0; timeout--) {
145 if (op_type == POLL_16B_REG)
146 rval = readw(addr); /* 16 bit */
147 else
148 rval = readl(addr) ; /* 32 bit */
149
150 if ((rval & mask) == val)
151 return 1;
152
153 udelay(10000);
154 }
155
156 debug("Time out waiting (%p = %#010x)\n", addr, rval);
157 return 0;
158 }
159
160 /*
161 * comphy_pcie_power_up
162 *
163 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
164 */
comphy_pcie_power_up(u32 speed,u32 invert)165 static int comphy_pcie_power_up(u32 speed, u32 invert)
166 {
167 int ret;
168
169 debug_enter();
170
171 /*
172 * 1. Enable max PLL.
173 */
174 reg_set16(phy_addr(PCIE, LANE_CFG1), bf_use_max_pll_rate, 0);
175
176 /*
177 * 2. Select 20 bit SERDES interface.
178 */
179 reg_set16(phy_addr(PCIE, GLOB_CLK_SRC_LO), bf_cfg_sel_20b, 0);
180
181 /*
182 * 3. Force to use reg setting for PCIe mode
183 */
184 reg_set16(phy_addr(PCIE, MISC_REG1), bf_sel_bits_pcie_force, 0);
185
186 /*
187 * 4. Change RX wait
188 */
189 reg_set16(phy_addr(PCIE, PWR_MGM_TIM1), 0x10C, 0xFFFF);
190
191 /*
192 * 5. Enable idle sync
193 */
194 reg_set16(phy_addr(PCIE, UNIT_CTRL), 0x60 | rb_idle_sync_en, 0xFFFF);
195
196 /*
197 * 6. Enable the output of 100M/125M/500M clock
198 */
199 reg_set16(phy_addr(PCIE, MISC_REG0),
200 0xA00D | rb_clk500m_en | rb_clk100m_125m_en, 0xFFFF);
201
202 /*
203 * 7. Enable TX
204 */
205 reg_set(PCIE_REF_CLK_ADDR, 0x1342, 0xFFFFFFFF);
206
207 /*
208 * 8. Check crystal jumper setting and program the Power and PLL
209 * Control accordingly
210 */
211 if (get_ref_clk() == 40) {
212 /* 40 MHz */
213 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC63, 0xFFFF);
214 } else {
215 /* 25 MHz */
216 reg_set16(phy_addr(PCIE, PWR_PLL_CTRL), 0xFC62, 0xFFFF);
217 }
218
219 /*
220 * 9. Override Speed_PLL value and use MAC PLL
221 */
222 reg_set16(phy_addr(PCIE, KVCO_CAL_CTRL), 0x0040 | rb_use_max_pll_rate,
223 0xFFFF);
224
225 /*
226 * 10. Check the Polarity invert bit
227 */
228 if (invert & PHY_POLARITY_TXD_INVERT)
229 reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0);
230
231 if (invert & PHY_POLARITY_RXD_INVERT)
232 reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0);
233
234 /*
235 * 11. Release SW reset
236 */
237 reg_set16(phy_addr(PCIE, GLOB_PHY_CTRL0),
238 rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32,
239 bf_soft_rst | bf_mode_refdiv);
240
241 /* Wait for > 55 us to allow PCLK be enabled */
242 udelay(PLL_SET_DELAY_US);
243
244 /* Assert PCLK enabled */
245 ret = comphy_poll_reg(phy_addr(PCIE, LANE_STAT1), /* address */
246 rb_txdclk_pclk_en, /* value */
247 rb_txdclk_pclk_en, /* mask */
248 POLL_16B_REG); /* 16bit */
249 if (!ret)
250 printf("Failed to lock PCIe PLL\n");
251
252 debug_exit();
253
254 /* Return the status of the PLL */
255 return ret;
256 }
257
258 /*
259 * reg_set_indirect
260 *
261 * return: void
262 */
reg_set_indirect(u32 reg,u16 data,u16 mask)263 static void reg_set_indirect(u32 reg, u16 data, u16 mask)
264 {
265 reg_set(rh_vsreg_addr, reg, 0xFFFFFFFF);
266 reg_set(rh_vsreg_data, data, mask);
267 }
268
269 /*
270 * comphy_sata_power_up
271 *
272 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
273 */
comphy_sata_power_up(void)274 static int comphy_sata_power_up(void)
275 {
276 int ret;
277
278 debug_enter();
279
280 /*
281 * 0. Swap SATA TX lines
282 */
283 reg_set_indirect(vphy_sync_pattern_reg, bs_txd_inv, bs_txd_inv);
284
285 /*
286 * 1. Select 40-bit data width width
287 */
288 reg_set_indirect(vphy_loopback_reg0, 0x800, bs_phyintf_40bit);
289
290 /*
291 * 2. Select reference clock and PHY mode (SATA)
292 */
293 if (get_ref_clk() == 40) {
294 /* 40 MHz */
295 reg_set_indirect(vphy_power_reg0, 0x3, 0x00FF);
296 } else {
297 /* 20 MHz */
298 reg_set_indirect(vphy_power_reg0, 0x1, 0x00FF);
299 }
300
301 /*
302 * 3. Use maximum PLL rate (no power save)
303 */
304 reg_set_indirect(vphy_calctl_reg, bs_max_pll_rate, bs_max_pll_rate);
305
306 /*
307 * 4. Reset reserved bit (??)
308 */
309 reg_set_indirect(vphy_reserve_reg, 0, bs_phyctrl_frm_pin);
310
311 /*
312 * 5. Set vendor-specific configuration (??)
313 */
314 reg_set(rh_vs0_a, vsata_ctrl_reg, 0xFFFFFFFF);
315 reg_set(rh_vs0_d, bs_phy_pu_pll, bs_phy_pu_pll);
316
317 /* Wait for > 55 us to allow PLL be enabled */
318 udelay(PLL_SET_DELAY_US);
319
320 /* Assert SATA PLL enabled */
321 reg_set(rh_vsreg_addr, vphy_loopback_reg0, 0xFFFFFFFF);
322 ret = comphy_poll_reg(rh_vsreg_data, /* address */
323 bs_pll_ready_tx, /* value */
324 bs_pll_ready_tx, /* mask */
325 POLL_32B_REG); /* 32bit */
326 if (!ret)
327 printf("Failed to lock SATA PLL\n");
328
329 debug_exit();
330
331 return ret;
332 }
333
334 /*
335 * usb3_reg_set16
336 *
337 * return: void
338 */
usb3_reg_set16(u32 reg,u16 data,u16 mask,u32 lane)339 static void usb3_reg_set16(u32 reg, u16 data, u16 mask, u32 lane)
340 {
341 /*
342 * When Lane 2 PHY is for USB3, access the PHY registers
343 * through indirect Address and Data registers INDIR_ACC_PHY_ADDR
344 * (RD00E0178h [31:0]) and INDIR_ACC_PHY_DATA (RD00E017Ch [31:0])
345 * within the SATA Host Controller registers, Lane 2 base register
346 * offset is 0x200
347 */
348
349 if (lane == 2)
350 reg_set_indirect(USB3PHY_LANE2_REG_BASE_OFFSET + reg, data,
351 mask);
352 else
353 reg_set16(phy_addr(USB3, reg), data, mask);
354 }
355
356 /*
357 * comphy_usb3_power_up
358 *
359 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
360 */
comphy_usb3_power_up(u32 lane,u32 type,u32 speed,u32 invert)361 static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert)
362 {
363 int ret;
364
365 debug_enter();
366
367 /*
368 * 1. Power up OTG module
369 */
370 reg_set(USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0);
371
372 /*
373 * 2. Set counter for 100us pulse in USB3 Host and Device
374 * restore default burst size limit (Reference Clock 31:24)
375 */
376 reg_set(USB3_CTRPUL_VAL_REG, 0x8 << 24, rb_usb3_ctr_100ns);
377
378
379 /* 0xd005c300 = 0x1001 */
380 /* set PRD_TXDEEMPH (3.5db de-emph) */
381 usb3_reg_set16(LANE_CFG0, 0x1, 0xFF, lane);
382
383 /*
384 * Set BIT0: enable transmitter in high impedance mode
385 * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency
386 * Set BIT6: Tx detect Rx at HiZ mode
387 * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db
388 * together with bit 0 of COMPHY_REG_LANE_CFG0_ADDR
389 * register
390 */
391 usb3_reg_set16(LANE_CFG1,
392 tx_det_rx_mode | gen2_tx_data_dly_deft
393 | tx_elec_idle_mode_en,
394 prd_txdeemph1_mask | tx_det_rx_mode
395 | gen2_tx_data_dly_mask | tx_elec_idle_mode_en, lane);
396
397 /* 0xd005c310 = 0x93: set Spread Spectrum Clock Enabled */
398 usb3_reg_set16(LANE_CFG4, bf_spread_spectrum_clock_en, 0x80, lane);
399
400 /*
401 * set Override Margining Controls From the MAC: Use margining signals
402 * from lane configuration
403 */
404 usb3_reg_set16(TEST_MODE_CTRL, rb_mode_margin_override, 0xFFFF, lane);
405
406 /* set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles */
407 /* set Mode Clock Source = PCLK is generated from REFCLK */
408 usb3_reg_set16(GLOB_CLK_SRC_LO, 0x0, 0xFF, lane);
409
410 /* set G2 Spread Spectrum Clock Amplitude at 4K */
411 usb3_reg_set16(GEN2_SETTINGS_2, g2_tx_ssc_amp, 0xF000, lane);
412
413 /*
414 * unset G3 Spread Spectrum Clock Amplitude & set G3 TX and RX Register
415 * Master Current Select
416 */
417 usb3_reg_set16(GEN2_SETTINGS_3, 0x0, 0xFFFF, lane);
418
419 /*
420 * 3. Check crystal jumper setting and program the Power and PLL
421 * Control accordingly
422 * 4. Change RX wait
423 */
424 if (get_ref_clk() == 40) {
425 /* 40 MHz */
426 usb3_reg_set16(PWR_PLL_CTRL, 0xFCA3, 0xFFFF, lane);
427 usb3_reg_set16(PWR_MGM_TIM1, 0x10C, 0xFFFF, lane);
428 } else {
429 /* 25 MHz */
430 usb3_reg_set16(PWR_PLL_CTRL, 0xFCA2, 0xFFFF, lane);
431 usb3_reg_set16(PWR_MGM_TIM1, 0x107, 0xFFFF, lane);
432 }
433
434 /*
435 * 5. Enable idle sync
436 */
437 usb3_reg_set16(UNIT_CTRL, 0x60 | rb_idle_sync_en, 0xFFFF, lane);
438
439 /*
440 * 6. Enable the output of 500M clock
441 */
442 usb3_reg_set16(MISC_REG0, 0xA00D | rb_clk500m_en, 0xFFFF, lane);
443
444 /*
445 * 7. Set 20-bit data width
446 */
447 usb3_reg_set16(DIG_LB_EN, 0x0400, 0xFFFF, lane);
448
449 /*
450 * 8. Override Speed_PLL value and use MAC PLL
451 */
452 usb3_reg_set16(KVCO_CAL_CTRL, 0x0040 | rb_use_max_pll_rate, 0xFFFF,
453 lane);
454
455 /*
456 * 9. Check the Polarity invert bit
457 */
458 if (invert & PHY_POLARITY_TXD_INVERT)
459 usb3_reg_set16(SYNC_PATTERN, phy_txd_inv, 0, lane);
460
461 if (invert & PHY_POLARITY_RXD_INVERT)
462 usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0, lane);
463
464 /*
465 * 10. Set max speed generation to USB3.0 5Gbps
466 */
467 usb3_reg_set16(SYNC_MASK_GEN, 0x0400, 0x0C00, lane);
468
469 /*
470 * 11. Set capacitor value for FFE gain peaking to 0xF
471 */
472 usb3_reg_set16(GEN3_SETTINGS_3, 0xF, 0xF, lane);
473
474 /*
475 * 12. Release SW reset
476 */
477 usb3_reg_set16(GLOB_PHY_CTRL0,
478 rb_mode_core_clk_freq_sel | rb_mode_pipe_width_32
479 | 0x20, 0xFFFF, lane);
480
481 /* Wait for > 55 us to allow PCLK be enabled */
482 udelay(PLL_SET_DELAY_US);
483
484 /* Assert PCLK enabled */
485 if (lane == 2) {
486 reg_set(rh_vsreg_addr,
487 LANE_STAT1 + USB3PHY_LANE2_REG_BASE_OFFSET,
488 0xFFFFFFFF);
489 ret = comphy_poll_reg(rh_vsreg_data, /* address */
490 rb_txdclk_pclk_en, /* value */
491 rb_txdclk_pclk_en, /* mask */
492 POLL_32B_REG); /* 32bit */
493 } else {
494 ret = comphy_poll_reg(phy_addr(USB3, LANE_STAT1), /* address */
495 rb_txdclk_pclk_en, /* value */
496 rb_txdclk_pclk_en, /* mask */
497 POLL_16B_REG); /* 16bit */
498 }
499 if (!ret)
500 printf("Failed to lock USB3 PLL\n");
501
502 /*
503 * Set Soft ID for Host mode (Device mode works with Hard ID
504 * detection)
505 */
506 if (type == PHY_TYPE_USB3_HOST0) {
507 /*
508 * set BIT0: set ID_MODE of Host/Device = "Soft ID" (BIT1)
509 * clear BIT1: set SOFT_ID = Host
510 * set BIT4: set INT_MODE = ID. Interrupt Mode: enable
511 * interrupt by ID instead of using both interrupts
512 * of HOST and Device ORed simultaneously
513 * INT_MODE=ID in order to avoid unexpected
514 * behaviour or both interrupts together
515 */
516 reg_set(USB32_CTRL_BASE,
517 usb32_ctrl_id_mode | usb32_ctrl_int_mode,
518 usb32_ctrl_id_mode | usb32_ctrl_soft_id |
519 usb32_ctrl_int_mode);
520 }
521
522 debug_exit();
523
524 return ret;
525 }
526
527 /*
528 * comphy_usb2_power_up
529 *
530 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
531 */
comphy_usb2_power_up(u8 usb32)532 static int comphy_usb2_power_up(u8 usb32)
533 {
534 int ret;
535
536 debug_enter();
537
538 if (usb32 != 0 && usb32 != 1) {
539 printf("invalid usb32 value: (%d), should be either 0 or 1\n",
540 usb32);
541 debug_exit();
542 return 0;
543 }
544
545 /*
546 * 0. Setup PLL. 40MHz clock uses defaults.
547 * See "PLL Settings for Typical REFCLK" table
548 */
549 if (get_ref_clk() == 25) {
550 reg_set(USB2_PHY_BASE(usb32), 5 | (96 << 16),
551 0x3F | (0xFF << 16) | (0x3 << 28));
552 }
553
554 /*
555 * 1. PHY pull up and disable USB2 suspend
556 */
557 reg_set(USB2_PHY_CTRL_ADDR(usb32),
558 RB_USB2PHY_SUSPM(usb32) | RB_USB2PHY_PU(usb32), 0);
559
560 if (usb32 != 0) {
561 /*
562 * 2. Power up OTG module
563 */
564 reg_set(USB2_PHY_OTG_CTRL_ADDR, rb_pu_otg, 0);
565
566 /*
567 * 3. Configure PHY charger detection
568 */
569 reg_set(USB2_PHY_CHRGR_DET_ADDR, 0,
570 rb_cdp_en | rb_dcp_en | rb_pd_en | rb_cdp_dm_auto |
571 rb_enswitch_dp | rb_enswitch_dm | rb_pu_chrg_dtc);
572 }
573
574 /* Assert PLL calibration done */
575 ret = comphy_poll_reg(USB2_PHY_CAL_CTRL_ADDR(usb32),
576 rb_usb2phy_pllcal_done, /* value */
577 rb_usb2phy_pllcal_done, /* mask */
578 POLL_32B_REG); /* 32bit */
579 if (!ret)
580 printf("Failed to end USB2 PLL calibration\n");
581
582 /* Assert impedance calibration done */
583 ret = comphy_poll_reg(USB2_PHY_CAL_CTRL_ADDR(usb32),
584 rb_usb2phy_impcal_done, /* value */
585 rb_usb2phy_impcal_done, /* mask */
586 POLL_32B_REG); /* 32bit */
587 if (!ret)
588 printf("Failed to end USB2 impedance calibration\n");
589
590 /* Assert squetch calibration done */
591 ret = comphy_poll_reg(USB2_PHY_RX_CHAN_CTRL1_ADDR(usb32),
592 rb_usb2phy_sqcal_done, /* value */
593 rb_usb2phy_sqcal_done, /* mask */
594 POLL_32B_REG); /* 32bit */
595 if (!ret)
596 printf("Failed to end USB2 unknown calibration\n");
597
598 /* Assert PLL is ready */
599 ret = comphy_poll_reg(USB2_PHY_PLL_CTRL0_ADDR(usb32),
600 rb_usb2phy_pll_ready, /* value */
601 rb_usb2phy_pll_ready, /* mask */
602 POLL_32B_REG); /* 32bit */
603
604 if (!ret)
605 printf("Failed to lock USB2 PLL\n");
606
607 debug_exit();
608
609 return ret;
610 }
611
612 /*
613 * comphy_emmc_power_up
614 *
615 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
616 */
comphy_emmc_power_up(void)617 static int comphy_emmc_power_up(void)
618 {
619 debug_enter();
620
621 /*
622 * 1. Bus power ON, Bus voltage 1.8V
623 */
624 reg_set(SDIO_HOST_CTRL1_ADDR, 0xB00, 0xF00);
625
626 /*
627 * 2. Set FIFO parameters
628 */
629 reg_set(SDIO_SDHC_FIFO_ADDR, 0x315, 0xFFFFFFFF);
630
631 /*
632 * 3. Set Capabilities 1_2
633 */
634 reg_set(SDIO_CAP_12_ADDR, 0x25FAC8B2, 0xFFFFFFFF);
635
636 /*
637 * 4. Set Endian
638 */
639 reg_set(SDIO_ENDIAN_ADDR, 0x00c00000, 0);
640
641 /*
642 * 4. Init PHY
643 */
644 reg_set(SDIO_PHY_TIMING_ADDR, 0x80000000, 0x80000000);
645 reg_set(SDIO_PHY_PAD_CTRL0_ADDR, 0x50000000, 0xF0000000);
646
647 /*
648 * 5. DLL reset
649 */
650 reg_set(SDIO_DLL_RST_ADDR, 0xFFFEFFFF, 0);
651 reg_set(SDIO_DLL_RST_ADDR, 0x00010000, 0);
652
653 debug_exit();
654
655 return 1;
656 }
657
658 /*
659 * comphy_sgmii_power_up
660 *
661 * return:
662 */
comphy_sgmii_phy_init(u32 lane,u32 speed)663 static void comphy_sgmii_phy_init(u32 lane, u32 speed)
664 {
665 const int fix_arr_sz = ARRAY_SIZE(sgmii_phy_init_fix);
666 int addr, fix_idx;
667 u16 val;
668
669 fix_idx = 0;
670 for (addr = 0; addr < 512; addr++) {
671 /*
672 * All PHY register values are defined in full for 3.125Gbps
673 * SERDES speed. The values required for 1.25 Gbps are almost
674 * the same and only few registers should be "fixed" in
675 * comparison to 3.125 Gbps values. These register values are
676 * stored in "sgmii_phy_init_fix" array.
677 */
678 if ((speed != PHY_SPEED_1_25G) &&
679 (sgmii_phy_init_fix[fix_idx].addr == addr)) {
680 /* Use new value */
681 val = sgmii_phy_init_fix[fix_idx].value;
682 if (fix_idx < fix_arr_sz)
683 fix_idx++;
684 } else {
685 val = sgmii_phy_init[addr];
686 }
687
688 reg_set16(sgmiiphy_addr(lane, addr), val, 0xFFFF);
689 }
690 }
691
692 /*
693 * comphy_sgmii_power_up
694 *
695 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
696 */
comphy_sgmii_power_up(u32 lane,u32 speed,u32 invert)697 static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
698 {
699 int ret;
700 u32 saved_selector;
701
702 debug_enter();
703
704 /*
705 * 1. Configure PHY to SATA/SAS mode by setting pin PIN_PIPE_SEL=0
706 */
707 saved_selector = readl(COMPHY_SEL_ADDR);
708 reg_set(COMPHY_SEL_ADDR, 0, 0xFFFFFFFF);
709
710 /*
711 * 2. Reset PHY by setting PHY input port PIN_RESET=1.
712 * 3. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep
713 * PHY TXP/TXN output to idle state during PHY initialization
714 * 4. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0.
715 */
716 reg_set(COMPHY_PHY_CFG1_ADDR(lane),
717 rb_pin_reset_comphy | rb_pin_tx_idle | rb_pin_pu_iveref,
718 rb_pin_reset_core | rb_pin_pu_pll |
719 rb_pin_pu_rx | rb_pin_pu_tx);
720
721 /*
722 * 5. Release reset to the PHY by setting PIN_RESET=0.
723 */
724 reg_set(COMPHY_PHY_CFG1_ADDR(lane), 0, rb_pin_reset_comphy);
725
726 /*
727 * 7. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide
728 * COMPHY bit rate
729 */
730 if (speed == PHY_SPEED_3_125G) { /* 3.125 GHz */
731 reg_set(COMPHY_PHY_CFG1_ADDR(lane),
732 (0x8 << rf_gen_rx_sel_shift) |
733 (0x8 << rf_gen_tx_sel_shift),
734 rf_gen_rx_select | rf_gen_tx_select);
735
736 } else if (speed == PHY_SPEED_1_25G) { /* 1.25 GHz */
737 reg_set(COMPHY_PHY_CFG1_ADDR(lane),
738 (0x6 << rf_gen_rx_sel_shift) |
739 (0x6 << rf_gen_tx_sel_shift),
740 rf_gen_rx_select | rf_gen_tx_select);
741 } else {
742 printf("Unsupported COMPHY speed!\n");
743 return 0;
744 }
745
746 /*
747 * 8. Wait 1mS for bandgap and reference clocks to stabilize;
748 * then start SW programming.
749 */
750 mdelay(10);
751
752 /* 9. Program COMPHY register PHY_MODE */
753 reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL),
754 PHY_MODE_SGMII << rf_phy_mode_shift, rf_phy_mode_mask);
755
756 /*
757 * 10. Set COMPHY register REFCLK_SEL to select the correct REFCLK
758 * source
759 */
760 reg_set16(sgmiiphy_addr(lane, MISC_REG0), 0, rb_ref_clk_sel);
761
762 /*
763 * 11. Set correct reference clock frequency in COMPHY register
764 * REF_FREF_SEL.
765 */
766 if (get_ref_clk() == 40) {
767 reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL),
768 0x4 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask);
769 } else {
770 /* 25MHz */
771 reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL),
772 0x1 << rf_ref_freq_sel_shift, rf_ref_freq_sel_mask);
773 }
774
775 /* 12. Program COMPHY register PHY_GEN_MAX[1:0] */
776 /*
777 * This step is mentioned in the flow received from verification team.
778 * However the PHY_GEN_MAX value is only meaningful for other
779 * interfaces (not SGMII). For instance, it selects SATA speed
780 * 1.5/3/6 Gbps or PCIe speed 2.5/5 Gbps
781 */
782
783 /*
784 * 13. Program COMPHY register SEL_BITS to set correct parallel data
785 * bus width
786 */
787 /* 10bit */
788 reg_set16(sgmiiphy_addr(lane, DIG_LB_EN), 0, rf_data_width_mask);
789
790 /*
791 * 14. As long as DFE function needs to be enabled in any mode,
792 * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F
793 * for real chip during COMPHY power on.
794 */
795 /*
796 * The step 14 exists (and empty) in the original initialization flow
797 * obtained from the verification team. According to the functional
798 * specification DFE_UPDATE_EN already has the default value 0x3F
799 */
800
801 /*
802 * 15. Program COMPHY GEN registers.
803 * These registers should be programmed based on the lab testing
804 * result to achieve optimal performance. Please contact the CEA
805 * group to get the related GEN table during real chip bring-up.
806 * We only requred to run though the entire registers programming
807 * flow defined by "comphy_sgmii_phy_init" when the REF clock is
808 * 40 MHz. For REF clock 25 MHz the default values stored in PHY
809 * registers are OK.
810 */
811 debug("Running C-DPI phy init %s mode\n",
812 speed == PHY_SPEED_3_125G ? "2G5" : "1G");
813 if (get_ref_clk() == 40)
814 comphy_sgmii_phy_init(lane, speed);
815
816 /*
817 * 16. [Simulation Only] should not be used for real chip.
818 * By pass power up calibration by programming EXT_FORCE_CAL_DONE
819 * (R02h[9]) to 1 to shorten COMPHY simulation time.
820 */
821 /*
822 * 17. [Simulation Only: should not be used for real chip]
823 * Program COMPHY register FAST_DFE_TIMER_EN=1 to shorten RX
824 * training simulation time.
825 */
826
827 /*
828 * 18. Check the PHY Polarity invert bit
829 */
830 if (invert & PHY_POLARITY_TXD_INVERT)
831 reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_txd_inv, 0);
832
833 if (invert & PHY_POLARITY_RXD_INVERT)
834 reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_rxd_inv, 0);
835
836 /*
837 * 19. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1
838 * to start PHY power up sequence. All the PHY register
839 * programming should be done before PIN_PU_PLL=1. There should be
840 * no register programming for normal PHY operation from this point.
841 */
842 reg_set(COMPHY_PHY_CFG1_ADDR(lane),
843 rb_pin_pu_pll | rb_pin_pu_rx | rb_pin_pu_tx,
844 rb_pin_pu_pll | rb_pin_pu_rx | rb_pin_pu_tx);
845
846 /*
847 * 20. Wait for PHY power up sequence to finish by checking output ports
848 * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1.
849 */
850 ret = comphy_poll_reg(COMPHY_PHY_STAT1_ADDR(lane), /* address */
851 rb_pll_ready_tx | rb_pll_ready_rx, /* value */
852 rb_pll_ready_tx | rb_pll_ready_rx, /* mask */
853 POLL_32B_REG); /* 32bit */
854 if (!ret)
855 printf("Failed to lock PLL for SGMII PHY %d\n", lane);
856
857 /*
858 * 21. Set COMPHY input port PIN_TX_IDLE=0
859 */
860 reg_set(COMPHY_PHY_CFG1_ADDR(lane), 0x0, rb_pin_tx_idle);
861
862 /*
863 * 22. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1.
864 * to start RX initialization. PIN_RX_INIT_DONE will be cleared to
865 * 0 by the PHY. After RX initialization is done, PIN_RX_INIT_DONE
866 * will be set to 1 by COMPHY. Set PIN_RX_INIT=0 after
867 * PIN_RX_INIT_DONE= 1.
868 * Please refer to RX initialization part for details.
869 */
870 reg_set(COMPHY_PHY_CFG1_ADDR(lane), rb_phy_rx_init, 0x0);
871
872 ret = comphy_poll_reg(COMPHY_PHY_STAT1_ADDR(lane), /* address */
873 rb_rx_init_done, /* value */
874 rb_rx_init_done, /* mask */
875 POLL_32B_REG); /* 32bit */
876 if (!ret)
877 printf("Failed to init RX of SGMII PHY %d\n", lane);
878
879 /*
880 * Restore saved selector.
881 */
882 reg_set(COMPHY_SEL_ADDR, saved_selector, 0xFFFFFFFF);
883
884 debug_exit();
885
886 return ret;
887 }
888
comphy_dedicated_phys_init(void)889 void comphy_dedicated_phys_init(void)
890 {
891 int node, usb32, ret = 1;
892 const void *blob = gd->fdt_blob;
893
894 debug_enter();
895
896 for (usb32 = 0; usb32 <= 1; usb32++) {
897 /*
898 * There are 2 UTMI PHYs in this SOC.
899 * One is independendent and one is paired with USB3 port (OTG)
900 */
901 if (usb32 == 0) {
902 node = fdt_node_offset_by_compatible(
903 blob, -1, "marvell,armada3700-ehci");
904 } else {
905 node = fdt_node_offset_by_compatible(
906 blob, -1, "marvell,armada3700-xhci");
907 }
908
909 if (node > 0) {
910 if (fdtdec_get_is_enabled(blob, node)) {
911 ret = comphy_usb2_power_up(usb32);
912 if (!ret)
913 printf("Failed to initialize UTMI PHY\n");
914 else
915 debug("UTMI PHY init succeed\n");
916 } else {
917 debug("USB%d node is disabled\n",
918 usb32 == 0 ? 2 : 3);
919 }
920 } else {
921 debug("No USB%d node in DT\n", usb32 == 0 ? 2 : 3);
922 }
923 }
924
925 node = fdt_node_offset_by_compatible(blob, -1,
926 "marvell,armada-3700-ahci");
927 if (node > 0) {
928 if (fdtdec_get_is_enabled(blob, node)) {
929 ret = comphy_sata_power_up();
930 if (!ret)
931 printf("Failed to initialize SATA PHY\n");
932 else
933 debug("SATA PHY init succeed\n");
934 } else {
935 debug("SATA node is disabled\n");
936 }
937 } else {
938 debug("No SATA node in DT\n");
939 }
940
941 node = fdt_node_offset_by_compatible(blob, -1,
942 "marvell,armada-8k-sdhci");
943 if (node <= 0) {
944 node = fdt_node_offset_by_compatible(
945 blob, -1, "marvell,armada-3700-sdhci");
946 }
947
948 if (node > 0) {
949 if (fdtdec_get_is_enabled(blob, node)) {
950 ret = comphy_emmc_power_up();
951 if (!ret)
952 printf("Failed to initialize SDIO/eMMC PHY\n");
953 else
954 debug("SDIO/eMMC PHY init succeed\n");
955 } else {
956 debug("SDIO/eMMC node is disabled\n");
957 }
958 } else {
959 debug("No SDIO/eMMC node in DT\n");
960 }
961
962 debug_exit();
963 }
964
comphy_a3700_init(struct chip_serdes_phy_config * chip_cfg,struct comphy_map * serdes_map)965 int comphy_a3700_init(struct chip_serdes_phy_config *chip_cfg,
966 struct comphy_map *serdes_map)
967 {
968 struct comphy_map *comphy_map;
969 u32 comphy_max_count = chip_cfg->comphy_lanes_count;
970 u32 lane, ret = 0;
971
972 debug_enter();
973
974 /* Initialize PHY mux */
975 chip_cfg->mux_data = a3700_comphy_mux_data;
976 comphy_mux_init(chip_cfg, serdes_map, COMPHY_SEL_ADDR);
977
978 for (lane = 0, comphy_map = serdes_map; lane < comphy_max_count;
979 lane++, comphy_map++) {
980 debug("Initialize serdes number %d\n", lane);
981 debug("Serdes type = 0x%x invert=%d\n",
982 comphy_map->type, comphy_map->invert);
983
984 switch (comphy_map->type) {
985 case PHY_TYPE_UNCONNECTED:
986 continue;
987 break;
988
989 case PHY_TYPE_PEX0:
990 ret = comphy_pcie_power_up(comphy_map->speed,
991 comphy_map->invert);
992 break;
993
994 case PHY_TYPE_USB3_HOST0:
995 case PHY_TYPE_USB3_DEVICE:
996 ret = comphy_usb3_power_up(lane,
997 comphy_map->type,
998 comphy_map->speed,
999 comphy_map->invert);
1000 break;
1001
1002 case PHY_TYPE_SGMII0:
1003 case PHY_TYPE_SGMII1:
1004 ret = comphy_sgmii_power_up(lane, comphy_map->speed,
1005 comphy_map->invert);
1006 break;
1007
1008 default:
1009 debug("Unknown SerDes type, skip initialize SerDes %d\n",
1010 lane);
1011 ret = 1;
1012 break;
1013 }
1014 if (!ret)
1015 printf("PLL is not locked - Failed to initialize lane %d\n",
1016 lane);
1017 }
1018
1019 debug_exit();
1020 return ret;
1021 }
1022