Lines Matching +full:sgmii +full:- +full:enable +full:- +full:pll

1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
25 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);  in pll5g_detune()
39 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);  in pll5g_tune()
56 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);  in vsc85xx_sd6g_pll_cfg_wr()
72 	/* qrate    = 1 for SGMII, 0 for QSGMII */  in vsc85xx_sd6g_common_cfg_wr()
73 	/* if_mode  = 1 for SGMII, 3 for QSGMII */  in vsc85xx_sd6g_common_cfg_wr()
85 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);  in vsc85xx_sd6g_common_cfg_wr()
109 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);  in vsc85xx_sd6g_des_cfg_wr()
134 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);  in vsc85xx_sd6g_ib_cfg0_wr()
158 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);  in vsc85xx_sd6g_ib_cfg1_wr()
180 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);  in vsc85xx_sd6g_ib_cfg2_wr()
199 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);  in vsc85xx_sd6g_ib_cfg3_wr()
218 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);  in vsc85xx_sd6g_ib_cfg4_wr()
231 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);  in vsc85xx_sd6g_misc_cfg_wr()
243 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);  in vsc85xx_sd6g_gp_cfg_wr()
266 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);  in vsc85xx_sd6g_dft_cfg2_wr()
284 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);  in vsc85xx_sd6g_dft_cfg0_wr()
303 		dev_err(&phydev->mdio.dev, "%s: write error\n", __func__);  in vsc85xx_pll5g_cfg0_wr()
346 	/* 1. Configure sd6g for SGMII prior to sd6g_IB_CAL */  in vsc85xx_sd6g_config_v2()
393 		return -ETIMEDOUT;  in vsc85xx_sd6g_config_v2()
406 	/* 5. Apply a frequency offset on RX-side (using internal FoJi logic) */  in vsc85xx_sd6g_config_v2()
486 		return -ETIMEDOUT;  in vsc85xx_sd6g_config_v2()
499 	/* 10. Re-enable transmitter */  in vsc85xx_sd6g_config_v2()
521 	/* Tune/Re-lock LCPLL */  in vsc85xx_sd6g_config_v2()
552 			dev_err(&phydev->mdio.dev, "%s: QSGMII error: %d\n",  in vsc85xx_sd6g_config_v2()
559 		/* SGMII */  in vsc85xx_sd6g_config_v2()
570 			dev_err(&phydev->mdio.dev, "%s: SGMII error: %d\n",  in vsc85xx_sd6g_config_v2()
577 		dev_err(&phydev->mdio.dev, "%s: invalid mac_if: %x\n",  in vsc85xx_sd6g_config_v2()
629 	/* 14. Wait for PLL cal to complete */  in vsc85xx_sd6g_config_v2()
642 		return -ETIMEDOUT;  in vsc85xx_sd6g_config_v2()