Lines Matching +full:sgmii +full:- +full:enable +full:- +full:pll
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Marvell International Ltd.
67 /*-----------------------------------------------------------*/
144 for (timeout = PLL_LOCK_TIMEOUT; timeout > 0; timeout--) { in comphy_poll_reg()
163 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
172 * 1. Enable max PLL. in comphy_pcie_power_up()
192 * 5. Enable idle sync in comphy_pcie_power_up()
197 * 6. Enable the output of 100M/125M/500M clock in comphy_pcie_power_up()
203 * 7. Enable TX in comphy_pcie_power_up()
208 * 8. Check crystal jumper setting and program the Power and PLL in comphy_pcie_power_up()
220 * 9. Override Speed_PLL value and use MAC PLL in comphy_pcie_power_up()
250 printf("Failed to lock PCIe PLL\n"); in comphy_pcie_power_up()
254 /* Return the status of the PLL */ in comphy_pcie_power_up()
272 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
286 * 1. Select 40-bit data width width in comphy_sata_power_up()
302 * 3. Use maximum PLL rate (no power save) in comphy_sata_power_up()
312 * 5. Set vendor-specific configuration (??) in comphy_sata_power_up()
317 /* Wait for > 55 us to allow PLL be enabled */ in comphy_sata_power_up()
320 /* Assert SATA PLL enabled */ in comphy_sata_power_up()
327 printf("Failed to lock SATA PLL\n"); in comphy_sata_power_up()
359 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
380 /* set PRD_TXDEEMPH (3.5db de-emph) */ in comphy_usb3_power_up()
384 * Set BIT0: enable transmitter in high impedance mode in comphy_usb3_power_up()
387 * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db in comphy_usb3_power_up()
406 /* set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles */ in comphy_usb3_power_up()
420 * 3. Check crystal jumper setting and program the Power and PLL in comphy_usb3_power_up()
435 * 5. Enable idle sync in comphy_usb3_power_up()
440 * 6. Enable the output of 500M clock in comphy_usb3_power_up()
445 * 7. Set 20-bit data width in comphy_usb3_power_up()
450 * 8. Override Speed_PLL value and use MAC PLL in comphy_usb3_power_up()
500 printf("Failed to lock USB3 PLL\n"); in comphy_usb3_power_up()
510 * set BIT4: set INT_MODE = ID. Interrupt Mode: enable in comphy_usb3_power_up()
530 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
546 * 0. Setup PLL. 40MHz clock uses defaults. in comphy_usb2_power_up()
547 * See "PLL Settings for Typical REFCLK" table in comphy_usb2_power_up()
574 /* Assert PLL calibration done */ in comphy_usb2_power_up()
580 printf("Failed to end USB2 PLL calibration\n"); in comphy_usb2_power_up()
598 /* Assert PLL is ready */ in comphy_usb2_power_up()
605 printf("Failed to lock USB2 PLL\n"); in comphy_usb2_power_up()
615 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
695 * return: 1 if PLL locked (OK), 0 otherwise (FAIL)
779 * interfaces (not SGMII). For instance, it selects SATA speed in comphy_sgmii_power_up()
805 * group to get the related GEN table during real chip bring-up. in comphy_sgmii_power_up()
811 debug("Running C-DPI phy init %s mode\n", in comphy_sgmii_power_up()
855 printf("Failed to lock PLL for SGMII PHY %d\n", lane); in comphy_sgmii_power_up()
877 printf("Failed to init RX of SGMII PHY %d\n", lane); in comphy_sgmii_power_up()
892 const void *blob = gd->fdt_blob; in comphy_dedicated_phys_init()
903 blob, -1, "marvell,armada3700-ehci"); in comphy_dedicated_phys_init()
906 blob, -1, "marvell,armada3700-xhci"); in comphy_dedicated_phys_init()
925 node = fdt_node_offset_by_compatible(blob, -1, in comphy_dedicated_phys_init()
926 "marvell,armada-3700-ahci"); in comphy_dedicated_phys_init()
941 node = fdt_node_offset_by_compatible(blob, -1, in comphy_dedicated_phys_init()
942 "marvell,armada-8k-sdhci"); in comphy_dedicated_phys_init()
945 blob, -1, "marvell,armada-3700-sdhci"); in comphy_dedicated_phys_init()
969 u32 comphy_max_count = chip_cfg->comphy_lanes_count; in comphy_a3700_init()
975 chip_cfg->mux_data = a3700_comphy_mux_data; in comphy_a3700_init()
982 comphy_map->type, comphy_map->invert); in comphy_a3700_init()
984 switch (comphy_map->type) { in comphy_a3700_init()
990 ret = comphy_pcie_power_up(comphy_map->speed, in comphy_a3700_init()
991 comphy_map->invert); in comphy_a3700_init()
997 comphy_map->type, in comphy_a3700_init()
998 comphy_map->speed, in comphy_a3700_init()
999 comphy_map->invert); in comphy_a3700_init()
1004 ret = comphy_sgmii_power_up(lane, comphy_map->speed, in comphy_a3700_init()
1005 comphy_map->invert); in comphy_a3700_init()
1015 printf("PLL is not locked - Failed to initialize lane %d\n", in comphy_a3700_init()