Lines Matching +full:sgmii +full:- +full:enable +full:- +full:pll
1 // SPDX-License-Identifier: BSD-3-Clause
2 /* Copyright 2016-2018 NXP
3 * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
107 sja1105_packing(buf, &idiv->clksrc, 28, 24, size, op); in sja1105_cgu_idiv_packing()
108 sja1105_packing(buf, &idiv->autoblock, 11, 11, size, op); in sja1105_cgu_idiv_packing()
109 sja1105_packing(buf, &idiv->idiv, 5, 2, size, op); in sja1105_cgu_idiv_packing()
110 sja1105_packing(buf, &idiv->pd, 0, 0, size, op); in sja1105_cgu_idiv_packing()
116 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cgu_idiv_config()
117 struct device *dev = priv->ds->dev; in sja1105_cgu_idiv_config()
121 if (regs->cgu_idiv[port] == SJA1105_RSV_ADDR) in sja1105_cgu_idiv_config()
126 return -ERANGE; in sja1105_cgu_idiv_config()
132 idiv.idiv = factor - 1; /* Divide by 1 or 10 */ in sja1105_cgu_idiv_config()
136 return sja1105_xfer_buf(priv, SPI_WRITE, regs->cgu_idiv[port], in sja1105_cgu_idiv_config()
146 sja1105_packing(buf, &cmd->clksrc, 28, 24, size, op); in sja1105_cgu_mii_control_packing()
147 sja1105_packing(buf, &cmd->autoblock, 11, 11, size, op); in sja1105_cgu_mii_control_packing()
148 sja1105_packing(buf, &cmd->pd, 0, 0, size, op); in sja1105_cgu_mii_control_packing()
154 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cgu_mii_tx_clk_config()
173 if (regs->mii_tx_clk[port] == SJA1105_RSV_ADDR) in sja1105_cgu_mii_tx_clk_config()
187 return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_tx_clk[port], in sja1105_cgu_mii_tx_clk_config()
194 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cgu_mii_rx_clk_config()
205 if (regs->mii_rx_clk[port] == SJA1105_RSV_ADDR) in sja1105_cgu_mii_rx_clk_config()
214 return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_rx_clk[port], in sja1105_cgu_mii_rx_clk_config()
221 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cgu_mii_ext_tx_clk_config()
232 if (regs->mii_ext_tx_clk[port] == SJA1105_RSV_ADDR) in sja1105_cgu_mii_ext_tx_clk_config()
241 return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_ext_tx_clk[port], in sja1105_cgu_mii_ext_tx_clk_config()
248 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cgu_mii_ext_rx_clk_config()
259 if (regs->mii_ext_rx_clk[port] == SJA1105_RSV_ADDR) in sja1105_cgu_mii_ext_rx_clk_config()
268 return sja1105_xfer_buf(priv, SPI_WRITE, regs->mii_ext_rx_clk[port], in sja1105_cgu_mii_ext_rx_clk_config()
275 struct device *dev = priv->ds->dev; in sja1105_mii_clocking_setup()
278 dev_dbg(dev, "Configuring MII-%s clocking\n", in sja1105_mii_clocking_setup()
281 * If role is PHY, enable IDIV and configure for 1/1 divider in sja1105_mii_clocking_setup()
328 sja1105_packing(buf, &cmd->pllclksrc, 28, 24, size, op); in sja1105_cgu_pll_control_packing()
329 sja1105_packing(buf, &cmd->msel, 23, 16, size, op); in sja1105_cgu_pll_control_packing()
330 sja1105_packing(buf, &cmd->autoblock, 11, 11, size, op); in sja1105_cgu_pll_control_packing()
331 sja1105_packing(buf, &cmd->psel, 9, 8, size, op); in sja1105_cgu_pll_control_packing()
332 sja1105_packing(buf, &cmd->direct, 7, 7, size, op); in sja1105_cgu_pll_control_packing()
333 sja1105_packing(buf, &cmd->fbsel, 6, 6, size, op); in sja1105_cgu_pll_control_packing()
334 sja1105_packing(buf, &cmd->bypass, 1, 1, size, op); in sja1105_cgu_pll_control_packing()
335 sja1105_packing(buf, &cmd->pd, 0, 0, size, op); in sja1105_cgu_pll_control_packing()
341 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cgu_rgmii_tx_clk_config()
346 if (regs->rgmii_tx_clk[port] == SJA1105_RSV_ADDR) in sja1105_cgu_rgmii_tx_clk_config()
349 if (speed == priv->info->port_speed[SJA1105_SPEED_1000MBPS]) { in sja1105_cgu_rgmii_tx_clk_config()
365 return sja1105_xfer_buf(priv, SPI_WRITE, regs->rgmii_tx_clk[port], in sja1105_cgu_rgmii_tx_clk_config()
376 sja1105_packing(buf, &cmd->d32_os, 28, 27, size, op); in sja1105_cfg_pad_mii_packing()
377 sja1105_packing(buf, &cmd->d32_ih, 26, 26, size, op); in sja1105_cfg_pad_mii_packing()
378 sja1105_packing(buf, &cmd->d32_ipud, 25, 24, size, op); in sja1105_cfg_pad_mii_packing()
379 sja1105_packing(buf, &cmd->d10_os, 20, 19, size, op); in sja1105_cfg_pad_mii_packing()
380 sja1105_packing(buf, &cmd->d10_ih, 18, 18, size, op); in sja1105_cfg_pad_mii_packing()
381 sja1105_packing(buf, &cmd->d10_ipud, 17, 16, size, op); in sja1105_cfg_pad_mii_packing()
382 sja1105_packing(buf, &cmd->ctrl_os, 12, 11, size, op); in sja1105_cfg_pad_mii_packing()
383 sja1105_packing(buf, &cmd->ctrl_ih, 10, 10, size, op); in sja1105_cfg_pad_mii_packing()
384 sja1105_packing(buf, &cmd->ctrl_ipud, 9, 8, size, op); in sja1105_cfg_pad_mii_packing()
385 sja1105_packing(buf, &cmd->clk_os, 4, 3, size, op); in sja1105_cfg_pad_mii_packing()
386 sja1105_packing(buf, &cmd->clk_ih, 2, 2, size, op); in sja1105_cfg_pad_mii_packing()
387 sja1105_packing(buf, &cmd->clk_ipud, 1, 0, size, op); in sja1105_cfg_pad_mii_packing()
393 const struct sja1105_regs *regs = priv->info->regs; in sja1105_rgmii_cfg_pad_tx_config()
397 if (regs->pad_mii_tx[port] == SJA1105_RSV_ADDR) in sja1105_rgmii_cfg_pad_tx_config()
416 return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_tx[port], in sja1105_rgmii_cfg_pad_tx_config()
422 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cfg_pad_rx_config()
426 if (regs->pad_mii_rx[port] == SJA1105_RSV_ADDR) in sja1105_cfg_pad_rx_config()
431 /* non-Schmitt (default) */ in sja1105_cfg_pad_rx_config()
432 pad_mii_rx.d32_ipud = 2; /* RXD[3:2] input weak pull-up/down */ in sja1105_cfg_pad_rx_config()
435 /* non-Schmitt (default) */ in sja1105_cfg_pad_rx_config()
436 pad_mii_rx.d10_ipud = 2; /* RXD[1:0] input weak pull-up/down */ in sja1105_cfg_pad_rx_config()
440 /* non-Schmitt (default) */ in sja1105_cfg_pad_rx_config()
442 /* input stage weak pull-up/down: */ in sja1105_cfg_pad_rx_config()
443 /* pull-down */ in sja1105_cfg_pad_rx_config()
447 /* non-Schmitt (default) */ in sja1105_cfg_pad_rx_config()
448 pad_mii_rx.clk_ipud = 2; /* RX_CLK/RXC input pull-up/down: */ in sja1105_cfg_pad_rx_config()
452 return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_rx[port], in sja1105_cfg_pad_rx_config()
462 sja1105_packing(buf, &cmd->rxc_stable_ovr, 15, 15, size, op); in sja1105_cfg_pad_mii_id_packing()
463 sja1105_packing(buf, &cmd->rxc_delay, 14, 10, size, op); in sja1105_cfg_pad_mii_id_packing()
464 sja1105_packing(buf, &cmd->rxc_bypass, 9, 9, size, op); in sja1105_cfg_pad_mii_id_packing()
465 sja1105_packing(buf, &cmd->rxc_pd, 8, 8, size, op); in sja1105_cfg_pad_mii_id_packing()
466 sja1105_packing(buf, &cmd->txc_stable_ovr, 7, 7, size, op); in sja1105_cfg_pad_mii_id_packing()
467 sja1105_packing(buf, &cmd->txc_delay, 6, 2, size, op); in sja1105_cfg_pad_mii_id_packing()
468 sja1105_packing(buf, &cmd->txc_bypass, 1, 1, size, op); in sja1105_cfg_pad_mii_id_packing()
469 sja1105_packing(buf, &cmd->txc_pd, 0, 0, size, op); in sja1105_cfg_pad_mii_id_packing()
489 sja1105_packing(buf, &cmd->rxc_stable_ovr, 26, 26, size, op); in sja1110_cfg_pad_mii_id_packing()
490 sja1105_packing(buf, &cmd->rxc_delay, 25, 21, size, op); in sja1110_cfg_pad_mii_id_packing()
492 sja1105_packing(buf, &cmd->rxc_bypass, 17, 17, size, op); in sja1110_cfg_pad_mii_id_packing()
493 sja1105_packing(buf, &cmd->rxc_pd, 16, 16, size, op); in sja1110_cfg_pad_mii_id_packing()
494 sja1105_packing(buf, &cmd->txc_stable_ovr, 10, 10, size, op); in sja1110_cfg_pad_mii_id_packing()
495 sja1105_packing(buf, &cmd->txc_delay, 9, 5, size, op); in sja1110_cfg_pad_mii_id_packing()
497 sja1105_packing(buf, &cmd->txc_bypass, 1, 1, size, op); in sja1110_cfg_pad_mii_id_packing()
498 sja1105_packing(buf, &cmd->txc_pd, 0, 0, size, op); in sja1110_cfg_pad_mii_id_packing()
501 /* The RGMII delay setup procedure is 2-step and gets called upon each
506 * as it will re-lock at the new frequency afterwards.
511 const struct sja1105_regs *regs = priv->info->regs; in sja1105pqrs_setup_rgmii_delay()
513 int rx_delay = priv->rgmii_rx_delay_ps[port]; in sja1105pqrs_setup_rgmii_delay()
514 int tx_delay = priv->rgmii_tx_delay_ps[port]; in sja1105pqrs_setup_rgmii_delay()
530 rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_id[port], in sja1105pqrs_setup_rgmii_delay()
546 return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_id[port], in sja1105pqrs_setup_rgmii_delay()
553 const struct sja1105_regs *regs = priv->info->regs; in sja1110_setup_rgmii_delay()
555 int rx_delay = priv->rgmii_rx_delay_ps[port]; in sja1110_setup_rgmii_delay()
556 int tx_delay = priv->rgmii_tx_delay_ps[port]; in sja1110_setup_rgmii_delay()
577 return sja1105_xfer_buf(priv, SPI_WRITE, regs->pad_mii_id[port], in sja1110_setup_rgmii_delay()
584 struct device *dev = priv->ds->dev; in sja1105_rgmii_clocking_setup()
589 mac = priv->static_config.tables[BLK_IDX_MAC_CONFIG].entries; in sja1105_rgmii_clocking_setup()
595 if (speed == priv->info->port_speed[SJA1105_SPEED_1000MBPS]) { in sja1105_rgmii_clocking_setup()
598 } else if (speed == priv->info->port_speed[SJA1105_SPEED_100MBPS]) { in sja1105_rgmii_clocking_setup()
601 } else if (speed == priv->info->port_speed[SJA1105_SPEED_10MBPS]) { in sja1105_rgmii_clocking_setup()
604 } else if (speed == priv->info->port_speed[SJA1105_SPEED_AUTO]) { in sja1105_rgmii_clocking_setup()
611 rc = -EINVAL; in sja1105_rgmii_clocking_setup()
629 if (!priv->info->setup_rgmii_delay) in sja1105_rgmii_clocking_setup()
632 return priv->info->setup_rgmii_delay(priv, port); in sja1105_rgmii_clocking_setup()
638 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cgu_rmii_ref_clk_config()
649 if (regs->rmii_ref_clk[port] == SJA1105_RSV_ADDR) in sja1105_cgu_rmii_ref_clk_config()
658 return sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_ref_clk[port], in sja1105_cgu_rmii_ref_clk_config()
665 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cgu_rmii_ext_tx_clk_config()
669 if (regs->rmii_ext_tx_clk[port] == SJA1105_RSV_ADDR) in sja1105_cgu_rmii_ext_tx_clk_config()
678 return sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_ext_tx_clk[port], in sja1105_cgu_rmii_ext_tx_clk_config()
684 const struct sja1105_regs *regs = priv->info->regs; in sja1105_cgu_rmii_pll_config()
686 struct sja1105_cgu_pll_ctrl pll = {0}; in sja1105_cgu_rmii_pll_config() local
687 struct device *dev = priv->ds->dev; in sja1105_cgu_rmii_pll_config()
690 if (regs->rmii_pll1 == SJA1105_RSV_ADDR) in sja1105_cgu_rmii_pll_config()
700 pll.pllclksrc = 0xA; in sja1105_cgu_rmii_pll_config()
701 pll.msel = 0x1; in sja1105_cgu_rmii_pll_config()
702 pll.autoblock = 0x1; in sja1105_cgu_rmii_pll_config()
703 pll.psel = 0x1; in sja1105_cgu_rmii_pll_config()
704 pll.direct = 0x0; in sja1105_cgu_rmii_pll_config()
705 pll.fbsel = 0x1; in sja1105_cgu_rmii_pll_config()
706 pll.bypass = 0x0; in sja1105_cgu_rmii_pll_config()
707 pll.pd = 0x1; in sja1105_cgu_rmii_pll_config()
709 sja1105_cgu_pll_control_packing(packed_buf, &pll, PACK); in sja1105_cgu_rmii_pll_config()
710 rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_pll1, packed_buf, in sja1105_cgu_rmii_pll_config()
717 /* Step 2: Enable PLL1 */ in sja1105_cgu_rmii_pll_config()
718 pll.pd = 0x0; in sja1105_cgu_rmii_pll_config()
720 sja1105_cgu_pll_control_packing(packed_buf, &pll, PACK); in sja1105_cgu_rmii_pll_config()
721 rc = sja1105_xfer_buf(priv, SPI_WRITE, regs->rmii_pll1, packed_buf, in sja1105_cgu_rmii_pll_config()
724 dev_err(dev, "failed to enable PLL1\n"); in sja1105_cgu_rmii_pll_config()
733 struct device *dev = priv->ds->dev; in sja1105_rmii_clocking_setup()
736 dev_dbg(dev, "Configuring RMII-%s clocking\n", in sja1105_rmii_clocking_setup()
740 /* Configure and enable PLL1 for 50Mhz output */ in sja1105_rmii_clocking_setup()
764 struct device *dev = priv->ds->dev; in sja1105_clocking_setup_port()
769 mii = priv->static_config.tables[BLK_IDX_XMII_PARAMS].entries; in sja1105_clocking_setup_port()
772 phy_mode = mii->xmii_mode[port]; in sja1105_clocking_setup_port()
774 role = mii->phy_mac[port]; in sja1105_clocking_setup_port()
787 /* Nothing to do in the CGU for SGMII */ in sja1105_clocking_setup_port()
793 return -EINVAL; in sja1105_clocking_setup_port()
807 struct dsa_switch *ds = priv->ds; in sja1105_clocking_setup()
810 for (port = 0; port < ds->num_ports; port++) { in sja1105_clocking_setup()
824 sja1105_packing(buf, &outclk->clksrc, 27, 24, size, op); in sja1110_cgu_outclk_packing()
825 sja1105_packing(buf, &outclk->autoblock, 11, 11, size, op); in sja1110_cgu_outclk_packing()
826 sja1105_packing(buf, &outclk->pd, 0, 0, size, op); in sja1110_cgu_outclk_packing()