Lines Matching +full:sgmii +full:- +full:enable +full:- +full:pll
1 // SPDX-License-Identifier: GPL-2.0-only
85 struct mii_bus *bus = priv->bus; in core_read_mmd_indirect()
89 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); in core_read_mmd_indirect()
94 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); in core_read_mmd_indirect()
99 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); in core_read_mmd_indirect()
104 value = bus->read(bus, 0, MII_MMD_DATA); in core_read_mmd_indirect()
108 dev_err(&bus->dev, "failed to read mmd register\n"); in core_read_mmd_indirect()
117 struct mii_bus *bus = priv->bus; in core_write_mmd_indirect()
121 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); in core_write_mmd_indirect()
126 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); in core_write_mmd_indirect()
131 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); in core_write_mmd_indirect()
136 ret = bus->write(bus, 0, MII_MMD_DATA, data); in core_write_mmd_indirect()
139 dev_err(&bus->dev, in core_write_mmd_indirect()
147 if (priv->bus) in mt7530_mutex_lock()
148 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); in mt7530_mutex_lock()
154 if (priv->bus) in mt7530_mutex_unlock()
155 mutex_unlock(&priv->bus->mdio_lock); in mt7530_mutex_unlock()
200 ret = regmap_write(priv->regmap, reg, val); in mt7530_mii_write()
203 dev_err(priv->dev, in mt7530_mii_write()
215 ret = regmap_read(priv->regmap, reg, &val); in mt7530_mii_read()
218 dev_err(priv->dev, in mt7530_mii_read()
239 return mt7530_mii_read(p->priv, p->reg); in _mt7530_unlocked_read()
247 mt7530_mutex_lock(p->priv); in _mt7530_read()
249 val = mt7530_mii_read(p->priv, p->reg); in _mt7530_read()
251 mt7530_mutex_unlock(p->priv); in _mt7530_read()
271 regmap_update_bits(priv->regmap, reg, mask, set); in mt7530_rmw()
303 dev_err(priv->dev, "reset timeout\n"); in mt7530_fdb_cmd()
312 return -EINVAL; in mt7530_fdb_cmd()
330 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", in mt7530_fdb_read()
334 fdb->vid = (reg[1] >> CVID) & CVID_MASK; in mt7530_fdb_read()
335 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; in mt7530_fdb_read()
336 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; in mt7530_fdb_read()
337 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; in mt7530_fdb_read()
338 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; in mt7530_fdb_read()
339 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; in mt7530_fdb_read()
340 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; in mt7530_fdb_read()
341 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; in mt7530_fdb_read()
342 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; in mt7530_fdb_read()
343 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; in mt7530_fdb_read()
382 /* Disable PLL */ in mt7530_pll_setup()
390 /* Enable PLL */ in mt7530_pll_setup()
398 /* Enable core clock */ in mt7530_pll_setup()
420 struct mt7530_priv *priv = ds->priv; in mt7530_pad_clk_setup()
426 dev_err(priv->dev, in mt7530_pad_clk_setup()
429 return -EINVAL; in mt7530_pad_clk_setup()
442 if (priv->id == ID_MT7621) { in mt7530_pad_clk_setup()
443 /* PLL frequency: 125MHz: 1.0GBit */ in mt7530_pad_clk_setup()
448 } else { /* PLL frequency: 250MHz: 2.0Gbit */ in mt7530_pad_clk_setup()
456 dev_err(priv->dev, "xMII interface %d not supported\n", in mt7530_pad_clk_setup()
458 return -EINVAL; in mt7530_pad_clk_setup()
483 /* Enable the MT7530 TRGMII clocks */ in mt7530_pad_clk_setup()
539 /* Step 3: disable PLLGP and enable program PLLGP */ in mt7531_pll_setup()
578 /* Enable 325M clock for SGMII */ in mt7531_pll_setup()
581 /* Enable 250SSC clock for RGMII */ in mt7531_pll_setup()
584 /* Step 6: Enable MT7531 PLL */ in mt7531_pll_setup()
598 struct mt7530_priv *priv = ds->priv; in mt7530_mib_reset()
606 return mdiobus_read_nested(priv->bus, port, regnum); in mt7530_phy_read_c22()
612 return mdiobus_write_nested(priv->bus, port, regnum, val); in mt7530_phy_write_c22()
618 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); in mt7530_phy_read_c45()
624 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); in mt7530_phy_write_c45()
642 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_read()
653 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_read()
664 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_read()
690 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_write()
701 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_write()
712 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c45_phy_write()
736 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_read()
748 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_read()
774 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_write()
786 dev_err(priv->dev, "poll timeout\n"); in mt7531_ind_c22_phy_write()
799 struct mt7530_priv *priv = bus->priv; in mt753x_phy_read_c22()
801 return priv->info->phy_read_c22(priv, port, regnum); in mt753x_phy_read_c22()
807 struct mt7530_priv *priv = bus->priv; in mt753x_phy_read_c45()
809 return priv->info->phy_read_c45(priv, port, devad, regnum); in mt753x_phy_read_c45()
815 struct mt7530_priv *priv = bus->priv; in mt753x_phy_write_c22()
817 return priv->info->phy_write_c22(priv, port, regnum, val); in mt753x_phy_write_c22()
824 struct mt7530_priv *priv = bus->priv; in mt753x_phy_write_c45()
826 return priv->info->phy_write_c45(priv, port, devad, regnum, val); in mt753x_phy_write_c45()
847 struct mt7530_priv *priv = ds->priv; in mt7530_get_ethtool_stats()
854 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; in mt7530_get_ethtool_stats()
857 if (mib->size == 2) { in mt7530_get_ethtool_stats()
876 struct mt7530_priv *priv = ds->priv; in mt7530_set_ageing_time()
879 unsigned int error = -1; in mt7530_set_ageing_time()
885 return -ERANGE; in mt7530_set_ageing_time()
889 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; in mt7530_set_ageing_time()
892 unsigned int tmp_error = secs - in mt7530_set_ageing_time()
933 struct mt7530_priv *priv = ds->priv; in mt7530_setup_port5()
937 mutex_lock(&priv->reg_mutex); in mt7530_setup_port5()
944 switch (priv->p5_intf_sel) { in mt7530_setup_port5()
946 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ in mt7530_setup_port5()
950 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ in mt7530_setup_port5()
957 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ in mt7530_setup_port5()
964 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", in mt7530_setup_port5()
965 priv->p5_intf_sel); in mt7530_setup_port5()
977 if (!dsa_is_dsa_port(priv->ds, 5) && in mt7530_setup_port5()
993 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", in mt7530_setup_port5()
994 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); in mt7530_setup_port5()
996 priv->p5_interface = interface; in mt7530_setup_port5()
999 mutex_unlock(&priv->reg_mutex); in mt7530_setup_port5()
1002 /* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL)
1007 * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A
1018 * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC
1035 * Link Layer Discovery Protocol (LLDP), link-local frames. They are not
1038 * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail:
1040 * Each of the reserved MAC addresses specified in Table 8-1
1041 * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be
1042 * permanently configured in the FDB in C-VLAN components and ERs.
1044 * Each of the reserved MAC addresses specified in Table 8-2
1045 * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently
1046 * configured in the FDB in S-VLAN components.
1048 * Each of the reserved MAC addresses specified in Table 8-3
1049 * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in
1056 * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of
1059 * The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no
1060 * conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN)
1061 * component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward.
1063 * that appear in Table 8-1, Table 8-2, and Table 8-3
1064 * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can
1068 * The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an
1069 * address that no conformant S-VLAN component, C-VLAN component, or MAC
1072 * appear in both Table 8-1 and Table 8-2 but not in Table 8-3
1073 * (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by
1074 * any TPMRs but will propagate no further than the nearest S-VLAN component,
1075 * C-VLAN component, or MAC Bridge.
1077 * The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address
1078 * that no conformant C-VLAN component, MAC Bridge can forward; however, it is
1079 * relayed by TPMR components and S-VLAN components. PDUs using this
1080 * destination address, or any of the other addresses that appear in Table 8-1
1081 * but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]),
1082 * will be relayed by TPMR components and S-VLAN components but will propagate
1083 * no further than the nearest C-VLAN component or MAC Bridge.
1090 * For link-local frames, only CPU port should be designated as destination port
1095 * Therefore, on the switch with CPU port architecture, link-local frames must
1096 * be trapped to CPU port, and certain link-local frames received by a Port of a
1097 * Bridge comprising a TPMR component or an S-VLAN component must be excluded
1100 * A Bridge of the switch with CPU port architecture cannot comprise a Two-Port
1106 * Therefore, a Bridge of this architecture can only comprise S-VLAN components,
1107 * C-VLAN components, or MAC Bridge components. Since there's no TPMR component,
1109 * Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge
1112 * One option to trap link-local frames to CPU port is to add static FDB entries
1116 * Bridge component or a C-VLAN component, there would have to be 16 times 4096
1119 * link-local frames from being discarded when the spanning tree Port State of
1126 * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination
1127 * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF
1132 * link-local frames with specific destination addresses to CPU port by Bridge,
1135 * Therefore, regardless of the type of the Bridge component, link-local frames
1138 * 01-80-C2-00-00-[00,01,02,03,0E]
1140 * In a Bridge comprising a MAC Bridge component or a C-VLAN component:
1142 * Link-local frames with these destination addresses won't be trapped to CPU
1143 * port which won't conform to IEEE Std 802.1Q-2022:
1145 * 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F]
1147 * In a Bridge comprising an S-VLAN component:
1149 * Link-local frames with these destination addresses will be trapped to CPU
1150 * port which won't conform to IEEE Std 802.1Q-2022:
1152 * 01-80-C2-00-00-00
1154 * Link-local frames with these destination addresses won't be trapped to CPU
1155 * port which won't conform to IEEE Std 802.1Q-2022:
1157 * 01-80-C2-00-00-[04,05,06,07,08,09,0A]
1159 * To trap link-local frames to CPU port as conformant as this switch
1160 * intellectual property can allow, link-local frames are made to be regarded as
1166 * has no PVID assigned on software, VLAN-untagged frames won't be allowed in.
1168 * have link-local frames bypass this function of the Forwarding Process.
1174 * VLAN-untagged. in mt753x_trap_frames()
1187 * them VLAN-untagged. in mt753x_trap_frames()
1201 * them VLAN-untagged. in mt753x_trap_frames()
1218 struct mt7530_priv *priv = ds->priv; in mt753x_cpu_port_enable()
1222 if (priv->info->cpu_port_config) { in mt753x_cpu_port_enable()
1223 ret = priv->info->cpu_port_config(ds, port); in mt753x_cpu_port_enable()
1228 /* Enable Mediatek header mode on the cpu port */ in mt753x_cpu_port_enable()
1232 /* Enable flooding on the CPU port */ in mt753x_cpu_port_enable()
1237 if (priv->id == ID_MT7530 || priv->id == ID_MT7621) in mt753x_cpu_port_enable()
1244 if (priv->id == ID_MT7531 || priv->id == ID_MT7988) in mt753x_cpu_port_enable()
1251 PCR_MATRIX(dsa_user_ports(priv->ds))); in mt753x_cpu_port_enable()
1265 struct mt7530_priv *priv = ds->priv; in mt7530_port_enable()
1267 mutex_lock(&priv->reg_mutex); in mt7530_port_enable()
1274 struct dsa_port *cpu_dp = dp->cpu_dp; in mt7530_port_enable()
1276 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); in mt7530_port_enable()
1278 priv->ports[port].enable = true; in mt7530_port_enable()
1280 priv->ports[port].pm); in mt7530_port_enable()
1283 mutex_unlock(&priv->reg_mutex); in mt7530_port_enable()
1291 struct mt7530_priv *priv = ds->priv; in mt7530_port_disable()
1293 mutex_lock(&priv->reg_mutex); in mt7530_port_disable()
1298 priv->ports[port].enable = false; in mt7530_port_disable()
1303 mutex_unlock(&priv->reg_mutex); in mt7530_port_disable()
1309 struct mt7530_priv *priv = ds->priv; in mt7530_port_change_mtu()
1355 struct mt7530_priv *priv = ds->priv; in mt7530_stp_state_set()
1388 return -EINVAL; in mt7530_port_pre_bridge_flags()
1398 struct mt7530_priv *priv = ds->priv; in mt7530_port_bridge_flags()
1425 struct dsa_port *cpu_dp = dp->cpu_dp; in mt7530_port_bridge_join()
1426 u32 port_bitmap = BIT(cpu_dp->index); in mt7530_port_bridge_join()
1427 struct mt7530_priv *priv = ds->priv; in mt7530_port_bridge_join()
1429 mutex_lock(&priv->reg_mutex); in mt7530_port_bridge_join()
1432 int other_port = other_dp->index; in mt7530_port_bridge_join()
1444 if (priv->ports[other_port].enable) in mt7530_port_bridge_join()
1447 priv->ports[other_port].pm |= PCR_MATRIX(BIT(port)); in mt7530_port_bridge_join()
1453 if (priv->ports[port].enable) in mt7530_port_bridge_join()
1456 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); in mt7530_port_bridge_join()
1462 mutex_unlock(&priv->reg_mutex); in mt7530_port_bridge_join()
1470 struct mt7530_priv *priv = ds->priv; in mt7530_port_set_vlan_unaware()
1474 /* This is called after .port_bridge_leave when leaving a VLAN-aware in mt7530_port_set_vlan_unaware()
1504 struct dsa_port *cpu_dp = dp->cpu_dp; in mt7530_port_set_vlan_unaware()
1506 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), in mt7530_port_set_vlan_unaware()
1507 PCR_MATRIX(dsa_user_ports(priv->ds))); in mt7530_port_set_vlan_unaware()
1508 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG in mt7530_port_set_vlan_unaware()
1516 struct mt7530_priv *priv = ds->priv; in mt7530_port_set_vlan_aware()
1525 G0_PORT_VID(priv->ports[port].pvid)); in mt7530_port_set_vlan_aware()
1528 if (!priv->ports[port].pvid) in mt7530_port_set_vlan_aware()
1558 struct dsa_port *cpu_dp = dp->cpu_dp; in mt7530_port_bridge_leave()
1559 struct mt7530_priv *priv = ds->priv; in mt7530_port_bridge_leave()
1561 mutex_lock(&priv->reg_mutex); in mt7530_port_bridge_leave()
1564 int other_port = other_dp->index; in mt7530_port_bridge_leave()
1576 if (priv->ports[other_port].enable) in mt7530_port_bridge_leave()
1579 priv->ports[other_port].pm &= ~PCR_MATRIX(BIT(port)); in mt7530_port_bridge_leave()
1585 if (priv->ports[port].enable) in mt7530_port_bridge_leave()
1587 PCR_MATRIX(BIT(cpu_dp->index))); in mt7530_port_bridge_leave()
1588 priv->ports[port].pm = PCR_MATRIX(BIT(cpu_dp->index)); in mt7530_port_bridge_leave()
1591 * back to the default as is at initial boot which is a VLAN-unaware in mt7530_port_bridge_leave()
1597 mutex_unlock(&priv->reg_mutex); in mt7530_port_bridge_leave()
1605 struct mt7530_priv *priv = ds->priv; in mt7530_port_fdb_add()
1609 mutex_lock(&priv->reg_mutex); in mt7530_port_fdb_add()
1610 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); in mt7530_port_fdb_add()
1612 mutex_unlock(&priv->reg_mutex); in mt7530_port_fdb_add()
1622 struct mt7530_priv *priv = ds->priv; in mt7530_port_fdb_del()
1626 mutex_lock(&priv->reg_mutex); in mt7530_port_fdb_del()
1627 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); in mt7530_port_fdb_del()
1629 mutex_unlock(&priv->reg_mutex); in mt7530_port_fdb_del()
1638 struct mt7530_priv *priv = ds->priv; in mt7530_port_fdb_dump()
1644 mutex_lock(&priv->reg_mutex); in mt7530_port_fdb_dump()
1660 } while (--cnt && in mt7530_port_fdb_dump()
1664 mutex_unlock(&priv->reg_mutex); in mt7530_port_fdb_dump()
1674 struct mt7530_priv *priv = ds->priv; in mt7530_port_mdb_add()
1675 const u8 *addr = mdb->addr; in mt7530_port_mdb_add()
1676 u16 vid = mdb->vid; in mt7530_port_mdb_add()
1680 mutex_lock(&priv->reg_mutex); in mt7530_port_mdb_add()
1688 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); in mt7530_port_mdb_add()
1691 mutex_unlock(&priv->reg_mutex); in mt7530_port_mdb_add()
1701 struct mt7530_priv *priv = ds->priv; in mt7530_port_mdb_del()
1702 const u8 *addr = mdb->addr; in mt7530_port_mdb_del()
1703 u16 vid = mdb->vid; in mt7530_port_mdb_del()
1707 mutex_lock(&priv->reg_mutex); in mt7530_port_mdb_del()
1715 mt7530_fdb_write(priv, vid, port_mask, addr, -1, in mt7530_port_mdb_del()
1719 mutex_unlock(&priv->reg_mutex); in mt7530_port_mdb_del()
1738 dev_err(priv->dev, "poll timeout\n"); in mt7530_vlan_cmd()
1744 dev_err(priv->dev, "read VTCR invalid\n"); in mt7530_vlan_cmd()
1745 return -EINVAL; in mt7530_vlan_cmd()
1756 struct dsa_port *cpu_dp = dp->cpu_dp; in mt7530_port_vlan_filtering()
1759 /* The port is being kept as VLAN-unaware port when bridge is in mt7530_port_vlan_filtering()
1762 * for becoming a VLAN-aware port. in mt7530_port_vlan_filtering()
1765 mt7530_port_set_vlan_aware(ds, cpu_dp->index); in mt7530_port_vlan_filtering()
1777 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); in mt7530_hw_vlan_add()
1781 new_members = entry->old_members | BIT(entry->port); in mt7530_hw_vlan_add()
1799 else if (entry->untagged) in mt7530_hw_vlan_add()
1804 ETAG_CTRL_P_MASK(entry->port), in mt7530_hw_vlan_add()
1805 ETAG_CTRL_P(entry->port, val)); in mt7530_hw_vlan_add()
1815 new_members = entry->old_members & ~BIT(entry->port); in mt7530_hw_vlan_del()
1819 dev_err(priv->dev, in mt7530_hw_vlan_del()
1846 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; in mt7530_hw_vlan_update()
1875 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; in mt7530_port_vlan_add()
1876 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; in mt7530_port_vlan_add()
1878 struct mt7530_priv *priv = ds->priv; in mt7530_port_vlan_add()
1880 mutex_lock(&priv->reg_mutex); in mt7530_port_vlan_add()
1883 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); in mt7530_port_vlan_add()
1886 priv->ports[port].pvid = vlan->vid; in mt7530_port_vlan_add()
1896 G0_PORT_VID(vlan->vid)); in mt7530_port_vlan_add()
1897 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { in mt7530_port_vlan_add()
1899 priv->ports[port].pvid = G0_PORT_VID_DEF; in mt7530_port_vlan_add()
1901 /* Only accept tagged frames if the port is VLAN-aware */ in mt7530_port_vlan_add()
1910 mutex_unlock(&priv->reg_mutex); in mt7530_port_vlan_add()
1920 struct mt7530_priv *priv = ds->priv; in mt7530_port_vlan_del()
1922 mutex_lock(&priv->reg_mutex); in mt7530_port_vlan_del()
1925 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, in mt7530_port_vlan_del()
1931 if (priv->ports[port].pvid == vlan->vid) { in mt7530_port_vlan_del()
1932 priv->ports[port].pvid = G0_PORT_VID_DEF; in mt7530_port_vlan_del()
1934 /* Only accept tagged frames if the port is VLAN-aware */ in mt7530_port_vlan_del()
1944 mutex_unlock(&priv->reg_mutex); in mt7530_port_vlan_del()
1967 struct mt7530_priv *priv = ds->priv; in mt753x_port_mirror_add()
1972 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) in mt753x_port_mirror_add()
1973 return -EEXIST; in mt753x_port_mirror_add()
1975 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); in mt753x_port_mirror_add()
1978 monitor_port = mt753x_mirror_port_get(priv->id, val); in mt753x_port_mirror_add()
1979 if (val & MT753X_MIRROR_EN(priv->id) && in mt753x_port_mirror_add()
1980 monitor_port != mirror->to_local_port) in mt753x_port_mirror_add()
1981 return -EEXIST; in mt753x_port_mirror_add()
1983 val |= MT753X_MIRROR_EN(priv->id); in mt753x_port_mirror_add()
1984 val &= ~MT753X_MIRROR_MASK(priv->id); in mt753x_port_mirror_add()
1985 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); in mt753x_port_mirror_add()
1986 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); in mt753x_port_mirror_add()
1991 priv->mirror_rx |= BIT(port); in mt753x_port_mirror_add()
1994 priv->mirror_tx |= BIT(port); in mt753x_port_mirror_add()
2004 struct mt7530_priv *priv = ds->priv; in mt753x_port_mirror_del()
2008 if (mirror->ingress) { in mt753x_port_mirror_del()
2010 priv->mirror_rx &= ~BIT(port); in mt753x_port_mirror_del()
2013 priv->mirror_tx &= ~BIT(port); in mt753x_port_mirror_del()
2017 if (!priv->mirror_rx && !priv->mirror_tx) { in mt753x_port_mirror_del()
2018 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); in mt753x_port_mirror_del()
2019 val &= ~MT753X_MIRROR_EN(priv->id); in mt753x_port_mirror_del()
2020 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); in mt753x_port_mirror_del()
2109 struct device *dev = priv->dev; in mt7530_setup_gpio()
2114 return -ENOMEM; in mt7530_setup_gpio()
2120 gc->label = "mt7530"; in mt7530_setup_gpio()
2121 gc->parent = dev; in mt7530_setup_gpio()
2122 gc->owner = THIS_MODULE; in mt7530_setup_gpio()
2123 gc->get_direction = mt7530_gpio_get_direction; in mt7530_setup_gpio()
2124 gc->direction_input = mt7530_gpio_direction_input; in mt7530_setup_gpio()
2125 gc->direction_output = mt7530_gpio_direction_output; in mt7530_setup_gpio()
2126 gc->get = mt7530_gpio_get; in mt7530_setup_gpio()
2127 gc->set = mt7530_gpio_set; in mt7530_setup_gpio()
2128 gc->base = -1; in mt7530_setup_gpio()
2129 gc->ngpio = 15; in mt7530_setup_gpio()
2130 gc->can_sleep = true; in mt7530_setup_gpio()
2153 irq = irq_find_mapping(priv->irq_domain, p); in mt7530_irq_thread_fn()
2167 priv->irq_enable &= ~BIT(d->hwirq); in mt7530_irq_mask()
2175 priv->irq_enable |= BIT(d->hwirq); in mt7530_irq_unmask()
2191 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); in mt7530_irq_bus_sync_unlock()
2207 irq_set_chip_data(irq, domain->host_data); in mt7530_irq_map()
2225 priv->irq_enable &= ~BIT(d->hwirq); in mt7988_irq_mask()
2226 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); in mt7988_irq_mask()
2234 priv->irq_enable |= BIT(d->hwirq); in mt7988_irq_unmask()
2235 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); in mt7988_irq_unmask()
2248 irq_set_chip_data(irq, domain->host_data); in mt7988_irq_map()
2264 struct dsa_switch *ds = priv->ds; in mt7530_setup_mdio_irq()
2268 if (BIT(p) & ds->phys_mii_mask) { in mt7530_setup_mdio_irq()
2271 irq = irq_create_mapping(priv->irq_domain, p); in mt7530_setup_mdio_irq()
2272 ds->slave_mii_bus->irq[p] = irq; in mt7530_setup_mdio_irq()
2280 struct device *dev = priv->dev; in mt7530_setup_irq()
2281 struct device_node *np = dev->of_node; in mt7530_setup_irq()
2284 if (!of_property_read_bool(np, "interrupt-controller")) { in mt7530_setup_irq()
2289 priv->irq = of_irq_get(np, 0); in mt7530_setup_irq()
2290 if (priv->irq <= 0) { in mt7530_setup_irq()
2291 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); in mt7530_setup_irq()
2292 return priv->irq ? : -EINVAL; in mt7530_setup_irq()
2295 if (priv->id == ID_MT7988) in mt7530_setup_irq()
2296 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, in mt7530_setup_irq()
2300 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, in mt7530_setup_irq()
2304 if (!priv->irq_domain) { in mt7530_setup_irq()
2306 return -ENOMEM; in mt7530_setup_irq()
2310 if (priv->id != ID_MT7531) in mt7530_setup_irq()
2313 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, in mt7530_setup_irq()
2316 irq_domain_remove(priv->irq_domain); in mt7530_setup_irq()
2330 if (BIT(p) & priv->ds->phys_mii_mask) { in mt7530_free_mdio_irq()
2333 irq = irq_find_mapping(priv->irq_domain, p); in mt7530_free_mdio_irq()
2342 free_irq(priv->irq, priv); in mt7530_free_irq_common()
2343 irq_domain_remove(priv->irq_domain); in mt7530_free_irq_common()
2356 struct dsa_switch *ds = priv->ds; in mt7530_setup_mdio()
2357 struct device *dev = priv->dev; in mt7530_setup_mdio()
2364 return -ENOMEM; in mt7530_setup_mdio()
2366 ds->slave_mii_bus = bus; in mt7530_setup_mdio()
2367 bus->priv = priv; in mt7530_setup_mdio()
2368 bus->name = KBUILD_MODNAME "-mii"; in mt7530_setup_mdio()
2369 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); in mt7530_setup_mdio()
2370 bus->read = mt753x_phy_read_c22; in mt7530_setup_mdio()
2371 bus->write = mt753x_phy_write_c22; in mt7530_setup_mdio()
2372 bus->read_c45 = mt753x_phy_read_c45; in mt7530_setup_mdio()
2373 bus->write_c45 = mt753x_phy_write_c45; in mt7530_setup_mdio()
2374 bus->parent = dev; in mt7530_setup_mdio()
2375 bus->phy_mask = ~ds->phys_mii_mask; in mt7530_setup_mdio()
2377 if (priv->irq) in mt7530_setup_mdio()
2383 if (priv->irq) in mt7530_setup_mdio()
2393 struct mt7530_priv *priv = ds->priv; in mt7530_setup()
2408 dn = cpu_dp->master->dev.of_node->parent; in mt7530_setup()
2416 dev_err(ds->dev, "parent OF node of DSA master not found"); in mt7530_setup()
2417 return -EINVAL; in mt7530_setup()
2420 ds->assisted_learning_on_cpu_port = true; in mt7530_setup()
2421 ds->mtu_enforcement_ingress = true; in mt7530_setup()
2423 if (priv->id == ID_MT7530) { in mt7530_setup()
2424 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); in mt7530_setup()
2425 ret = regulator_enable(priv->core_pwr); in mt7530_setup()
2427 dev_err(priv->dev, in mt7530_setup()
2428 "Failed to enable core power: %d\n", ret); in mt7530_setup()
2432 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); in mt7530_setup()
2433 ret = regulator_enable(priv->io_pwr); in mt7530_setup()
2435 dev_err(priv->dev, "Failed to enable io pwr: %d\n", in mt7530_setup()
2441 /* Reset whole chip through gpio pin or memory-mapped registers for in mt7530_setup()
2444 if (priv->mcm) { in mt7530_setup()
2445 reset_control_assert(priv->rstc); in mt7530_setup()
2447 reset_control_deassert(priv->rstc); in mt7530_setup()
2449 gpiod_set_value_cansleep(priv->reset, 0); in mt7530_setup()
2451 gpiod_set_value_cansleep(priv->reset, 1); in mt7530_setup()
2459 dev_err(priv->dev, "reset timeout\n"); in mt7530_setup()
2466 dev_err(priv->dev, "chip %x can't be supported\n", id); in mt7530_setup()
2467 return -ENODEV; in mt7530_setup()
2484 /* Enable port 6 */ in mt7530_setup()
2490 priv->p6_interface = PHY_INTERFACE_MODE_NA; in mt7530_setup()
2497 /* Enable and reset MIB counters */ in mt7530_setup()
2519 /* Enable consistent egress tag */ in mt7530_setup()
2527 /* Setup VLAN ID 0 for VLAN-unaware bridges */ in mt7530_setup()
2533 priv->p5_intf_sel = P5_DISABLED; in mt7530_setup()
2537 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; in mt7530_setup()
2538 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); in mt7530_setup()
2539 if (ret && ret != -ENODEV) in mt7530_setup()
2545 "mediatek,eth-mac")) in mt7530_setup()
2552 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); in mt7530_setup()
2556 if (phy_node->parent == priv->dev->of_node->parent) { in mt7530_setup()
2558 if (ret && ret != -ENODEV) { in mt7530_setup()
2563 id = of_mdio_parse_addr(ds->dev, phy_node); in mt7530_setup()
2565 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; in mt7530_setup()
2567 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; in mt7530_setup()
2576 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { in mt7530_setup()
2596 struct mt7530_priv *priv = ds->priv; in mt7531_setup_common()
2601 /* Enable and reset MIB counters */ in mt7531_setup_common()
2630 /* Enable consistent egress tag */ in mt7531_setup_common()
2649 struct mt7530_priv *priv = ds->priv; in mt7531_setup()
2654 /* Reset whole chip through gpio pin or memory-mapped registers for in mt7531_setup()
2657 if (priv->mcm) { in mt7531_setup()
2658 reset_control_assert(priv->rstc); in mt7531_setup()
2660 reset_control_deassert(priv->rstc); in mt7531_setup()
2662 gpiod_set_value_cansleep(priv->reset, 0); in mt7531_setup()
2664 gpiod_set_value_cansleep(priv->reset, 1); in mt7531_setup()
2672 dev_err(priv->dev, "reset timeout\n"); in mt7531_setup()
2680 dev_err(priv->dev, "chip %x can't be supported\n", id); in mt7531_setup()
2681 return -ENODEV; in mt7531_setup()
2684 /* all MACs must be forced link-down before sw reset */ in mt7531_setup()
2696 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; in mt7531_setup()
2698 /* Let ds->slave_mii_bus be able to access external phy. */ in mt7531_setup()
2704 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; in mt7531_setup()
2706 dev_dbg(ds->dev, "P5 support %s interface\n", in mt7531_setup()
2707 p5_intf_modes(priv->p5_intf_sel)); in mt7531_setup()
2713 priv->p5_interface = PHY_INTERFACE_MODE_NA; in mt7531_setup()
2714 priv->p6_interface = PHY_INTERFACE_MODE_NA; in mt7531_setup()
2716 /* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since in mt7531_setup()
2737 /* Setup VLAN ID 0 for VLAN-unaware bridges */ in mt7531_setup()
2742 ds->assisted_learning_on_cpu_port = true; in mt7531_setup()
2743 ds->mtu_enforcement_ingress = true; in mt7531_setup()
2754 config->supported_interfaces); in mt7530_mac_port_get_caps()
2758 phy_interface_set_rgmii(config->supported_interfaces); in mt7530_mac_port_get_caps()
2760 config->supported_interfaces); in mt7530_mac_port_get_caps()
2762 config->supported_interfaces); in mt7530_mac_port_get_caps()
2767 config->supported_interfaces); in mt7530_mac_port_get_caps()
2769 config->supported_interfaces); in mt7530_mac_port_get_caps()
2776 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); in mt7531_is_rgmii_port()
2782 struct mt7530_priv *priv = ds->priv; in mt7531_mac_port_get_caps()
2787 config->supported_interfaces); in mt7531_mac_port_get_caps()
2790 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ in mt7531_mac_port_get_caps()
2792 phy_interface_set_rgmii(config->supported_interfaces); in mt7531_mac_port_get_caps()
2797 case 6: /* 1st cpu port supports sgmii/8023z only */ in mt7531_mac_port_get_caps()
2799 config->supported_interfaces); in mt7531_mac_port_get_caps()
2801 config->supported_interfaces); in mt7531_mac_port_get_caps()
2803 config->supported_interfaces); in mt7531_mac_port_get_caps()
2805 config->mac_capabilities |= MAC_2500FD; in mt7531_mac_port_get_caps()
2813 phy_interface_zero(config->supported_interfaces); in mt7988_mac_port_get_caps()
2818 config->supported_interfaces); in mt7988_mac_port_get_caps()
2823 config->supported_interfaces); in mt7988_mac_port_get_caps()
2824 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | in mt7988_mac_port_get_caps()
2832 struct mt7530_priv *priv = ds->priv; in mt753x_pad_setup()
2834 return priv->info->pad_setup(ds, state->interface); in mt753x_pad_setup()
2841 struct mt7530_priv *priv = ds->priv; in mt7530_mac_config()
2847 mt7530_setup_port5(priv->ds, interface); in mt7530_mac_config()
2859 dev_err(priv->dev, "RGMII mode is not available for port %d\n", in mt7531_rgmii_setup()
2861 return -EINVAL; in mt7531_rgmii_setup()
2891 return -EINVAL; in mt7531_rgmii_setup()
2912 return -EINVAL; in mt7988_mac_config()
2919 struct mt7530_priv *priv = ds->priv; in mt7531_mac_config()
2924 dev_err(priv->dev, "port %d is not a MAC port\n", port); in mt7531_mac_config()
2925 return -EINVAL; in mt7531_mac_config()
2934 phydev = dp->slave->phydev; in mt7531_mac_config()
2940 /* handled in SGMII PCS driver */ in mt7531_mac_config()
2943 return -EINVAL; in mt7531_mac_config()
2946 return -EINVAL; in mt7531_mac_config()
2953 struct mt7530_priv *priv = ds->priv; in mt753x_mac_config()
2955 return priv->info->mac_port_config(ds, port, mode, state->interface); in mt753x_mac_config()
2962 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_mac_select_pcs()
2966 return &priv->pcs[port].pcs; in mt753x_phylink_mac_select_pcs()
2970 return priv->ports[port].sgmii_pcs; in mt753x_phylink_mac_select_pcs()
2980 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_mac_config()
2985 if (state->interface != PHY_INTERFACE_MODE_GMII && in mt753x_phylink_mac_config()
2986 state->interface != PHY_INTERFACE_MODE_INTERNAL) in mt753x_phylink_mac_config()
2990 if (priv->p5_interface == state->interface) in mt753x_phylink_mac_config()
2996 if (priv->p5_intf_sel != P5_DISABLED) in mt753x_phylink_mac_config()
2997 priv->p5_interface = state->interface; in mt753x_phylink_mac_config()
3000 if (priv->p6_interface == state->interface) in mt753x_phylink_mac_config()
3008 priv->p6_interface = state->interface; in mt753x_phylink_mac_config()
3012 dev_err(ds->dev, "%s: unsupported %s port: %i\n", in mt753x_phylink_mac_config()
3013 __func__, phy_modes(state->interface), port); in mt753x_phylink_mac_config()
3021 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); in mt753x_phylink_mac_config()
3035 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_mac_link_down()
3045 if (pcs->ops->pcs_link_up) in mt753x_phylink_pcs_link_up()
3046 pcs->ops->pcs_link_up(pcs, mode, interface, speed, duplex); in mt753x_phylink_pcs_link_up()
3056 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_mac_link_up()
3061 /* MT753x MAC works in 1G full duplex mode for all up-clocked in mt753x_phylink_mac_link_up()
3103 struct mt7530_priv *priv = ds->priv; in mt7531_cpu_port_config()
3115 priv->p5_interface = interface; in mt7531_cpu_port_config()
3120 priv->p6_interface = interface; in mt7531_cpu_port_config()
3123 return -EINVAL; in mt7531_cpu_port_config()
3135 PMCR_CPU_PORT_SETTING(priv->id)); in mt7531_cpu_port_config()
3136 mt753x_phylink_pcs_link_up(&priv->pcs[port].pcs, MLO_AN_FIXED, in mt7531_cpu_port_config()
3147 struct mt7530_priv *priv = ds->priv; in mt7988_cpu_port_config()
3150 PMCR_CPU_PORT_SETTING(priv->id)); in mt7988_cpu_port_config()
3162 struct mt7530_priv *priv = ds->priv; in mt753x_phylink_get_caps()
3164 /* This switch only supports full-duplex at 1Gbps */ in mt753x_phylink_get_caps()
3165 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | in mt753x_phylink_get_caps()
3168 priv->info->mac_port_get_caps(ds, port, config); in mt753x_phylink_get_caps()
3176 if (state->interface == PHY_INTERFACE_MODE_TRGMII || in mt753x_pcs_validate()
3177 phy_interface_mode_is_8023z(state->interface)) in mt753x_pcs_validate()
3186 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; in mt7530_pcs_get_state()
3187 int port = pcs_to_mt753x_pcs(pcs)->port; in mt7530_pcs_get_state()
3192 state->link = (pmsr & PMSR_LINK); in mt7530_pcs_get_state()
3193 state->an_complete = state->link; in mt7530_pcs_get_state()
3194 state->duplex = !!(pmsr & PMSR_DPX); in mt7530_pcs_get_state()
3198 state->speed = SPEED_10; in mt7530_pcs_get_state()
3201 state->speed = SPEED_100; in mt7530_pcs_get_state()
3204 state->speed = SPEED_1000; in mt7530_pcs_get_state()
3207 state->speed = SPEED_UNKNOWN; in mt7530_pcs_get_state()
3211 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); in mt7530_pcs_get_state()
3213 state->pause |= MLO_PAUSE_RX; in mt7530_pcs_get_state()
3215 state->pause |= MLO_PAUSE_TX; in mt7530_pcs_get_state()
3240 struct mt7530_priv *priv = ds->priv; in mt753x_setup()
3244 for (i = 0; i < priv->ds->num_ports; i++) { in mt753x_setup()
3245 priv->pcs[i].pcs.ops = priv->info->pcs_ops; in mt753x_setup()
3246 priv->pcs[i].pcs.neg_mode = true; in mt753x_setup()
3247 priv->pcs[i].priv = priv; in mt753x_setup()
3248 priv->pcs[i].port = i; in mt753x_setup()
3251 ret = priv->info->sw_setup(ds); in mt753x_setup()
3260 if (ret && priv->irq) in mt753x_setup()
3263 if (priv->create_sgmii) { in mt753x_setup()
3264 ret = priv->create_sgmii(priv, mt7531_dual_sgmii_supported(priv)); in mt753x_setup()
3265 if (ret && priv->irq) in mt753x_setup()
3275 struct mt7530_priv *priv = ds->priv; in mt753x_get_mac_eee()
3278 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); in mt753x_get_mac_eee()
3279 e->tx_lpi_timer = GET_LPI_THRESH(eeecr); in mt753x_get_mac_eee()
3287 struct mt7530_priv *priv = ds->priv; in mt753x_set_mac_eee()
3290 if (e->tx_lpi_timer > 0xFFF) in mt753x_set_mac_eee()
3291 return -EINVAL; in mt753x_set_mac_eee()
3293 set = SET_LPI_THRESH(e->tx_lpi_timer); in mt753x_set_mac_eee()
3294 if (!e->tx_lpi_enabled) in mt753x_set_mac_eee()
3309 struct mt7530_priv *priv = ds->priv; in mt7988_setup()
3312 reset_control_assert(priv->rstc); in mt7988_setup()
3314 reset_control_deassert(priv->rstc); in mt7988_setup()
3417 struct device *dev = priv->dev; in mt7530_probe_common()
3419 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); in mt7530_probe_common()
3420 if (!priv->ds) in mt7530_probe_common()
3421 return -ENOMEM; in mt7530_probe_common()
3423 priv->ds->dev = dev; in mt7530_probe_common()
3424 priv->ds->num_ports = MT7530_NUM_PORTS; in mt7530_probe_common()
3429 priv->info = of_device_get_match_data(dev); in mt7530_probe_common()
3430 if (!priv->info) in mt7530_probe_common()
3431 return -EINVAL; in mt7530_probe_common()
3436 if (!priv->info->sw_setup || !priv->info->pad_setup || in mt7530_probe_common()
3437 !priv->info->phy_read_c22 || !priv->info->phy_write_c22 || in mt7530_probe_common()
3438 !priv->info->mac_port_get_caps || in mt7530_probe_common()
3439 !priv->info->mac_port_config) in mt7530_probe_common()
3440 return -EINVAL; in mt7530_probe_common()
3442 priv->id = priv->info->id; in mt7530_probe_common()
3443 priv->dev = dev; in mt7530_probe_common()
3444 priv->ds->priv = priv; in mt7530_probe_common()
3445 priv->ds->ops = &mt7530_switch_ops; in mt7530_probe_common()
3446 mutex_init(&priv->reg_mutex); in mt7530_probe_common()
3456 if (priv->irq) in mt7530_remove_common()
3459 dsa_unregister_switch(priv->ds); in mt7530_remove_common()
3461 mutex_destroy(&priv->reg_mutex); in mt7530_remove_common()