Lines Matching +full:sgmii +full:- +full:enable +full:- +full:pll
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
11 * The first PLL clock macro is used for internal reference clock. The second
12 * PLL clock macro is used to generate the clock for the PHY. This driver
13 * configures the first PLL CMU, the second PLL CMU, and programs the PHY to
14 * operate according to the mode of operation. The first PLL CMU is only
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
24 * External Clock ------| | -------------
25 * |------|
27 * The Ref PLL CMU CSR (Configuration System Registers) is accessed
30 * The PHY PLL CMU CSR is accessed indirectly from the SDS offset at 0x0000.
33 * The Ref PLL CMU can be located within the same PHY IP or outside the PHY IP
34 * due to shared Ref PLL CMU. For PHY with Ref PLL CMU shared with another IP,
37 * to located the SDS/Ref PLL CMU module and its clock for that IP enabled.
124 /* PLL Clock Macro Unit (CMU) CSR accessing from SDS indirectly */
496 PHY_CMU = 1, /* Clock macro is the PLL for the Serdes */
501 MUX_SELECT_SGMMII = 0, /* Switch the MUX to SGMII */
526 u32 txprecursor_cn1[MAX_LANE*3]; /* Tx emphasis taps 1st pre-cursor */
527 u32 txprecursor_cn2[MAX_LANE*3]; /* Tx emphasis taps 2nd pre-cursor */
528 u32 txpostcursor_cp1[MAX_LANE*3]; /* Tx emphasis taps post-cursor */
544 * For chip earlier than A3 version, enable this flag.
545 * To enable, pass boot argument phy_xgene.preA3Chip=1
548 MODULE_PARM_DESC(preA3Chip, "Enable pre-A3 chip support (1=enable 0=disable)");
597 void __iomem *sds_base = ctx->sds_base; in cmu_wr()
608 pr_debug("CMU WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, val); in cmu_wr()
614 void __iomem *sds_base = ctx->sds_base; in cmu_rd()
660 void __iomem *sds_base = ctx->sds_base; in serdes_wr()
669 pr_debug("SERDES WR addr 0x%X value 0x%08X <-> 0x%08X\n", reg, data, in serdes_wr()
675 void __iomem *sds_base = ctx->sds_base; in serdes_rd()
714 /* Set the programmable stage delays between various enable stages */ in xgene_phy_cfg_cmu_clk_type()
728 dev_dbg(ctx->dev, "Set external reference clock\n"); in xgene_phy_cfg_cmu_clk_type()
738 dev_dbg(ctx->dev, "Set internal reference clock\n"); in xgene_phy_cfg_cmu_clk_type()
753 dev_dbg(ctx->dev, in xgene_phy_cfg_cmu_clk_type()
783 /* Configure PLL for calibration */ in xgene_phy_sata_cfg_cmu_core()
799 /* Configure the PLL for either 100MHz or 50MHz */ in xgene_phy_sata_cfg_cmu_core()
835 /* Disable force PLL lock */ in xgene_phy_sata_cfg_cmu_core()
840 /* Setup PLL loop filter */ in xgene_phy_sata_cfg_cmu_core()
850 /* Enable or disable manual calibration */ in xgene_phy_sata_cfg_cmu_core()
856 /* Configure lane for 20-bits */ in xgene_phy_sata_cfg_cmu_core()
923 /* Enable SSC, set vertical step and DSM value */ in xgene_phy_ssc_enable()
930 /* Reset the PLL */ in xgene_phy_ssc_enable()
960 ctx->sata_param.txboostgain[lane * 3 + in xgene_phy_sata_cfg_lanes()
961 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
965 * enable TX FIFO in xgene_phy_sata_cfg_lanes()
973 /* Configure Tx for 20-bits */ in xgene_phy_sata_cfg_lanes()
985 /* Set pre-emphasis first 1 and 2, and post-emphasis values */ in xgene_phy_sata_cfg_lanes()
988 ctx->sata_param.txprecursor_cn1[lane * 3 + in xgene_phy_sata_cfg_lanes()
989 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
991 ctx->sata_param.txpostcursor_cp1[lane * 3 + in xgene_phy_sata_cfg_lanes()
992 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
994 ctx->sata_param.txprecursor_cn2[lane * 3 + in xgene_phy_sata_cfg_lanes()
995 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1001 ctx->sata_param.txamplitude[lane * 3 + in xgene_phy_sata_cfg_lanes()
1002 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1009 /* Configure Rx for 20-bits */ in xgene_phy_sata_cfg_lanes()
1015 /* Set CDR and LOS values and enable Rx SSC */ in xgene_phy_sata_cfg_lanes()
1029 /* Enable Latch Off; disable SUMOS and Tx termination */ in xgene_phy_sata_cfg_lanes()
1036 /* Set period error latch to 512T and enable BWL */ in xgene_phy_sata_cfg_lanes()
1047 /* Set Eye Monitor counter width to 12-bit */ in xgene_phy_sata_cfg_lanes()
1096 ctx->sata_param.txeyedirection[lane * 3 + in xgene_phy_sata_cfg_lanes()
1097 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1099 ctx->sata_param.txeyetuning[lane * 3 + in xgene_phy_sata_cfg_lanes()
1100 ctx->sata_param.speed[lane]]); in xgene_phy_sata_cfg_lanes()
1139 void __iomem *csr_serdes = ctx->sds_base; in xgene_phy_cal_rdy_chk()
1150 * As per PHY design spec, the PLL reset requires a minimum in xgene_phy_cal_rdy_chk()
1159 * As per PHY design spec, the PLL auto calibration requires in xgene_phy_cal_rdy_chk()
1167 * As per PHY design spec, the PLL requires a minimum of in xgene_phy_cal_rdy_chk()
1188 * The serial transmit pins, TXP/TXN, have Pull-UP and Pull-DOWN in xgene_phy_cal_rdy_chk()
1207 /* Poll the PLL calibration completion status for at least 1 ms */ in xgene_phy_cal_rdy_chk()
1214 * As per PHY design spec, PLL calibration status requires in xgene_phy_cal_rdy_chk()
1218 } while (--loop > 0); in xgene_phy_cal_rdy_chk()
1221 dev_dbg(ctx->dev, "PLL calibration %s\n", in xgene_phy_cal_rdy_chk()
1224 dev_err(ctx->dev, in xgene_phy_cal_rdy_chk()
1225 "PLL calibration failed due to VCO failure\n"); in xgene_phy_cal_rdy_chk()
1226 return -1; in xgene_phy_cal_rdy_chk()
1228 dev_dbg(ctx->dev, "PLL calibration successful\n"); in xgene_phy_cal_rdy_chk()
1231 dev_dbg(ctx->dev, "PHY Tx is %sready\n", val & 0x300 ? "" : "not "); in xgene_phy_cal_rdy_chk()
1241 dev_dbg(ctx->dev, "Reset VCO and re-start again\n"); in xgene_phy_pdwn_force_vco()
1256 void __iomem *sds_base = ctx->sds_base; in xgene_phy_hw_init_sata()
1261 dev_dbg(ctx->dev, "Reset PHY\n"); in xgene_phy_hw_init_sata()
1275 ctx->sata_param.txspeed[ctx->sata_param.speed[0]]); in xgene_phy_hw_init_sata()
1278 dev_dbg(ctx->dev, "Set the customer pin mode to SATA\n"); in xgene_phy_hw_init_sata()
1289 /* Enable SSC if enabled */ in xgene_phy_hw_init_sata()
1296 /* Set Rx/Tx 20-bit */ in xgene_phy_hw_init_sata()
1302 /* Start PLL calibration and try for three times */ in xgene_phy_hw_init_sata()
1309 } while (--i > 0); in xgene_phy_hw_init_sata()
1312 dev_err(ctx->dev, "PLL calibration failed\n"); in xgene_phy_hw_init_sata()
1323 dev_dbg(ctx->dev, "PHY init clk type %d\n", clk_type); in xgene_phy_hw_initialize()
1325 if (ctx->mode == MODE_SATA) { in xgene_phy_hw_initialize()
1330 dev_err(ctx->dev, "Un-supported customer pin mode %d\n", in xgene_phy_hw_initialize()
1331 ctx->mode); in xgene_phy_hw_initialize()
1332 return -ENODEV; in xgene_phy_hw_initialize()
1341 * Calibrate the receiver signal path offset in two steps - summar and
1438 dev_dbg(ctx->dev, "Generating avg calibration value for lane %d\n", in xgene_phy_gen_avg_val()
1441 /* Enable RX Hi-Z termination */ in xgene_phy_gen_avg_val()
1451 * Calibrate the receiver signal path offset in two steps - summar in xgene_phy_gen_avg_val()
1494 dev_dbg(ctx->dev, "Iteration %d:\n", avg_loop); in xgene_phy_gen_avg_val()
1495 dev_dbg(ctx->dev, "DO 0x%x XO 0x%x EO 0x%x SO 0x%x\n", in xgene_phy_gen_avg_val()
1498 dev_dbg(ctx->dev, "DE 0x%x XE 0x%x EE 0x%x SE 0x%x\n", in xgene_phy_gen_avg_val()
1501 dev_dbg(ctx->dev, "SUM 0x%x\n", sum_cal_itr); in xgene_phy_gen_avg_val()
1504 dev_err(ctx->dev, in xgene_phy_gen_avg_val()
1546 dev_dbg(ctx->dev, "Average Value:\n"); in xgene_phy_gen_avg_val()
1547 dev_dbg(ctx->dev, "DO 0x%x XO 0x%x EO 0x%x SO 0x%x\n", in xgene_phy_gen_avg_val()
1552 dev_dbg(ctx->dev, "DE 0x%x XE 0x%x EE 0x%x SE 0x%x\n", in xgene_phy_gen_avg_val()
1557 dev_dbg(ctx->dev, "SUM 0x%x\n", in xgene_phy_gen_avg_val()
1563 dev_dbg(ctx->dev, "Enable Manual Summer calibration\n"); in xgene_phy_gen_avg_val()
1567 dev_dbg(ctx->dev, "Enable Manual Latch calibration\n"); in xgene_phy_gen_avg_val()
1570 /* Disable RX Hi-Z termination */ in xgene_phy_gen_avg_val()
1588 dev_err(ctx->dev, "PHY initialize failed %d\n", rc); in xgene_phy_hw_init()
1593 if (!IS_ERR(ctx->clk)) { in xgene_phy_hw_init()
1595 clk_prepare_enable(ctx->clk); in xgene_phy_hw_init()
1596 clk_disable_unprepare(ctx->clk); in xgene_phy_hw_init()
1597 clk_prepare_enable(ctx->clk); in xgene_phy_hw_init()
1604 dev_dbg(ctx->dev, "PHY initialized\n"); in xgene_phy_hw_init()
1618 if (args->args_count <= 0) in xgene_phy_xlate()
1619 return ERR_PTR(-EINVAL); in xgene_phy_xlate()
1620 if (args->args[0] >= MODE_MAX) in xgene_phy_xlate()
1621 return ERR_PTR(-EINVAL); in xgene_phy_xlate()
1623 ctx->mode = args->args[0]; in xgene_phy_xlate()
1624 return ctx->phy; in xgene_phy_xlate()
1634 if (!of_property_read_u32_array(pdev->dev.of_node, name, buffer, in xgene_phy_get_param()
1659 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); in xgene_phy_probe()
1661 return -ENOMEM; in xgene_phy_probe()
1663 ctx->dev = &pdev->dev; in xgene_phy_probe()
1665 ctx->sds_base = devm_platform_ioremap_resource(pdev, 0); in xgene_phy_probe()
1666 if (IS_ERR(ctx->sds_base)) in xgene_phy_probe()
1667 return PTR_ERR(ctx->sds_base); in xgene_phy_probe()
1670 ctx->clk = clk_get(&pdev->dev, NULL); in xgene_phy_probe()
1673 xgene_phy_get_param(pdev, "apm,tx-eye-tuning", in xgene_phy_probe()
1674 ctx->sata_param.txeyetuning, 6, default_txeye_tuning, 1); in xgene_phy_probe()
1675 xgene_phy_get_param(pdev, "apm,tx-eye-direction", in xgene_phy_probe()
1676 ctx->sata_param.txeyedirection, 6, default_txeye_direction, 1); in xgene_phy_probe()
1677 xgene_phy_get_param(pdev, "apm,tx-boost-gain", in xgene_phy_probe()
1678 ctx->sata_param.txboostgain, 6, default_txboost_gain, 1); in xgene_phy_probe()
1679 xgene_phy_get_param(pdev, "apm,tx-amplitude", in xgene_phy_probe()
1680 ctx->sata_param.txamplitude, 6, default_txamp, 13300); in xgene_phy_probe()
1681 xgene_phy_get_param(pdev, "apm,tx-pre-cursor1", in xgene_phy_probe()
1682 ctx->sata_param.txprecursor_cn1, 6, default_txcn1, 18200); in xgene_phy_probe()
1683 xgene_phy_get_param(pdev, "apm,tx-pre-cursor2", in xgene_phy_probe()
1684 ctx->sata_param.txprecursor_cn2, 6, default_txcn2, 18200); in xgene_phy_probe()
1685 xgene_phy_get_param(pdev, "apm,tx-post-cursor", in xgene_phy_probe()
1686 ctx->sata_param.txpostcursor_cp1, 6, default_txcp1, 18200); in xgene_phy_probe()
1687 xgene_phy_get_param(pdev, "apm,tx-speed", in xgene_phy_probe()
1688 ctx->sata_param.txspeed, 3, default_spd, 1); in xgene_phy_probe()
1690 ctx->sata_param.speed[i] = 2; /* Default to Gen3 */ in xgene_phy_probe()
1694 ctx->phy = devm_phy_create(ctx->dev, NULL, &xgene_phy_ops); in xgene_phy_probe()
1695 if (IS_ERR(ctx->phy)) { in xgene_phy_probe()
1696 dev_dbg(&pdev->dev, "Failed to create PHY\n"); in xgene_phy_probe()
1697 return PTR_ERR(ctx->phy); in xgene_phy_probe()
1699 phy_set_drvdata(ctx->phy, ctx); in xgene_phy_probe()
1701 phy_provider = devm_of_phy_provider_register(ctx->dev, xgene_phy_xlate); in xgene_phy_probe()
1706 {.compatible = "apm,xgene-phy",},
1714 .name = "xgene-phy",
1720 MODULE_DESCRIPTION("APM X-Gene Multi-Purpose PHY driver");