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/openbmc/u-boot/drivers/clk/renesas/
H A Dclk-rcar-gen2.c82 u32 value, mult, div, rate = 0; in gen2_clk_get_rate() local
94 rate = gen2_clk_get_rate(&parent); in gen2_clk_get_rate()
95 debug("%s[%i] MOD clk: parent=%lu => rate=%u\n", in gen2_clk_get_rate()
96 __func__, __LINE__, parent.id, rate); in gen2_clk_get_rate()
97 return rate; in gen2_clk_get_rate()
107 rate = clk_get_rate(&priv->clk_extal); in gen2_clk_get_rate()
108 debug("%s[%i] EXTAL clk: rate=%u\n", in gen2_clk_get_rate()
109 __func__, __LINE__, rate); in gen2_clk_get_rate()
110 return rate; in gen2_clk_get_rate()
114 rate = clk_get_rate(&priv->clk_extal_usb); in gen2_clk_get_rate()
[all …]
H A Dclk-rcar-gen3.c110 static int gen3_clk_setup_sdif_div(struct clk *clk, ulong rate) in gen3_clk_setup_sdif_div() argument
136 writel((rate == 400000000) ? 0x4 : 0x1, priv->base + core->offset); in gen3_clk_setup_sdif_div()
164 u64 rate = 0; in gen3_clk_get_rate64() local
176 rate = gen3_clk_get_rate64(&parent); in gen3_clk_get_rate64()
177 debug("%s[%i] MOD clk: parent=%lu => rate=%llu\n", in gen3_clk_get_rate64()
178 __func__, __LINE__, parent.id, rate); in gen3_clk_get_rate64()
179 return rate; in gen3_clk_get_rate64()
189 rate = clk_get_rate(&priv->clk_extal); in gen3_clk_get_rate64()
190 debug("%s[%i] EXTAL clk: rate=%llu\n", in gen3_clk_get_rate64()
191 __func__, __LINE__, rate); in gen3_clk_get_rate64()
[all …]
/openbmc/openbmc/meta-openembedded/meta-multimedia/recipes-multimedia/sox/sox/
H A DCVE-2022-31651.patch4 Subject: [PATCH] formats: reject implausible rate
23 - if (rate && ft->signal.rate && ft->signal.rate != rate)
24 + if (rate && ft->signal.rate && ft->signal.rate != rate) {
25 lsx_warn("`%s': overriding sample rate", ft->filename);
26 - else ft->signal.rate = rate;
28 + } else if (!(rate > 0)) {
29 + lsx_fail_errno(ft, EINVAL, "invalid rate value");
32 + ft->signal.rate = rate;
/openbmc/u-boot/arch/arm/mach-imx/mx7ulp/
H A Dscg.c54 u32 reg, val, rate; in scg_sircdiv_get_rate() local
84 rate = scg_src_get_rate(SCG_SIRC_CLK); in scg_sircdiv_get_rate()
85 rate = rate / (1 << (val - 1)); in scg_sircdiv_get_rate()
87 return rate; in scg_sircdiv_get_rate()
92 u32 reg, val, rate; in scg_fircdiv_get_rate() local
122 rate = scg_src_get_rate(SCG_FIRC_CLK); in scg_fircdiv_get_rate()
123 rate = rate / (1 << (val - 1)); in scg_fircdiv_get_rate()
125 return rate; in scg_fircdiv_get_rate()
130 u32 reg, val, rate; in scg_soscdiv_get_rate() local
160 rate = scg_src_get_rate(SCG_SOSC_CLK); in scg_soscdiv_get_rate()
[all …]
/openbmc/u-boot/arch/mips/mach-pic32/
H A Dcpu.c25 static ulong rate(int id) in rate() function
30 ulong rate; in rate() local
43 rate = clk_get_rate(&clk); in rate()
47 return rate; in rate()
52 return rate(PB7CLK); in clk_get_cpu_rate()
61 ulong rate; in prefetch_init() local
64 rate = clk_get_cpu_rate() / 1000000; in prefetch_init()
71 if (rate < 66) in prefetch_init()
73 else if (rate < 133) in prefetch_init()
78 if (rate <= 83) in prefetch_init()
[all …]
/openbmc/qemu/audio/
H A Drate_template.h33 struct rate *rate = opaque; in NAME() local
49 if (rate->opos_inc == (1ULL + UINT_MAX)) { in NAME()
66 ilast = rate->ilast; in NAME()
71 while (rate->ipos <= (rate->opos >> 32)) { in NAME()
73 rate->ipos++; in NAME()
89 if (rate->ipos >= 0x10001) { in NAME()
90 rate->ipos = 1; in NAME()
91 rate->opos &= 0xffffffff; in NAME()
97 t = (rate->opos & UINT_MAX) * (1.f / UINT_MAX); in NAME()
99 t = (rate->opos & UINT_MAX) / (mixeng_real) UINT_MAX; in NAME()
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H A Dmixeng.c449 * Sound Tools rate change effect file.
468 struct rate { struct
480 struct rate *rate = g_new0(struct rate, 1); in st_rate_start() local
482 rate->opos = 0; in st_rate_start()
485 rate->opos_inc = ((uint64_t) inrate << 32) / outrate; in st_rate_start()
487 rate->ipos = 0; in st_rate_start()
488 rate->ilast.l = 0; in st_rate_start()
489 rate->ilast.r = 0; in st_rate_start()
490 return rate; in st_rate_start()
510 * @opaque: pointer to struct rate
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-core.c89 clk_get_rate(c); /* Make sure rate and sel are filled in */ in peri_clk_enable()
95 debug("%s %s set rate %lu div %lu sel %d parent %lu\n", in peri_clk_enable()
96 __func__, c->name, c->rate, c->div, c->sel, in peri_clk_enable()
97 c->parent->rate); in peri_clk_enable()
159 /* Set the rate of a peripheral clock */
160 static int peri_clk_set_rate(struct clk *c, unsigned long rate) in peri_clk_set_rate() argument
171 diff = rate; in peri_clk_set_rate()
181 /* round to the new rate */ in peri_clk_set_rate()
182 div = ref->clk.rate / rate; in peri_clk_set_rate()
186 new_rate = ref->clk.rate / div; in peri_clk_set_rate()
[all …]
/openbmc/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-core.c89 clk_get_rate(c); /* Make sure rate and sel are filled in */ in peri_clk_enable()
95 debug("%s %s set rate %lu div %lu sel %d parent %lu\n", in peri_clk_enable()
96 __func__, c->name, c->rate, c->div, c->sel, in peri_clk_enable()
97 c->parent->rate); in peri_clk_enable()
159 /* Set the rate of a peripheral clock */
160 static int peri_clk_set_rate(struct clk *c, unsigned long rate) in peri_clk_set_rate() argument
171 diff = rate; in peri_clk_set_rate()
181 /* round to the new rate */ in peri_clk_set_rate()
182 div = ref->clk.rate / rate; in peri_clk_set_rate()
186 new_rate = ref->clk.rate / div; in peri_clk_set_rate()
[all …]
/openbmc/u-boot/drivers/clk/aspeed/
H A Dclk_ast2400.c58 * Get the rate of the M-PLL clock from input clock frequency and
88 * Get the rate of the H-PLL clock from input clock frequency and
118 u16 rate = (hpll_reg >> 8) & 3; in ast2400_get_hpll_rate() local
120 clkin = hpll_rates[1][rate]; in ast2400_get_hpll_rate()
123 clkin = hpll_rates[0][rate]; in ast2400_get_hpll_rate()
125 clkin = hpll_rates[0][rate]; in ast2400_get_hpll_rate()
139 * Get the rate of the D2-PLL clock from input clock frequency and
181 u32 rate = ast2400_get_hpll_rate(scu); in ast2400_get_hclk() local
185 return (rate / ahb_div); in ast2400_get_hclk()
190 u32 rate = 0; in ast2400_get_pclk() local
[all …]
H A Dclk_ast2500.c59 * Get the rate of the M-PLL clock from input clock frequency and
77 * Get the rate of the H-PLL clock from input clock frequency and
96 * Get the rate of the D-PLL clock from input clock frequency and
113 * Get the rate of the D2-PLL clock from input clock frequency and
140 u32 rate = 0; in ast2500_get_hclk() local
142 rate = ast2500_get_hpll_rate(scu); in ast2500_get_hclk()
143 return (rate / axi_div / ahb_div); in ast2500_get_hclk()
148 u32 rate = 0; in ast2500_get_pclk() local
152 rate = ast2500_get_hpll_rate(scu); in ast2500_get_pclk()
154 return (rate / apb_div); in ast2500_get_pclk()
[all …]
/openbmc/u-boot/drivers/clk/
H A Dclk_meson.c74 static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
80 ulong rate, ulong current_rate);
271 unsigned int rate, parent_rate; in meson_div_get_rate() local
306 debug("%s: parent rate of %ld is %d\n", __func__, id, parent_rate); in meson_div_get_rate()
308 rate = parent_rate / (reg + 1); in meson_div_get_rate()
310 debug("%s: rate of %ld is %d\n", __func__, id, rate); in meson_div_get_rate()
312 return rate; in meson_div_get_rate()
315 static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate, in meson_div_set_rate() argument
325 if (current_rate == rate) in meson_div_set_rate()
328 debug("%s: setting rate of %ld from %ld to %ld\n", in meson_div_set_rate()
[all …]
H A Dclk_pic32.c22 /* FRC clk rate */
170 int parent_rate, int rate, int parent_id) in pic32_set_refclk() argument
179 * rate = parent_rate / [2 * (div + (trim / 512))] in pic32_set_refclk()
181 if (parent_rate <= rate) { in pic32_set_refclk()
185 div = parent_rate / (rate << 1); in pic32_set_refclk()
188 do_div(frac, rate); in pic32_set_refclk()
251 /* get parent rate */ in pic32_get_refclk()
265 * rate = parent_rate / [2 * (div + (trim / 512))] in pic32_get_refclk()
284 u64 rate; in pic32_get_mpll_rate() local
292 rate = (SYS_POSC_CLK_HZ / idiv) * mul; in pic32_get_mpll_rate()
[all …]
H A Dclk-hsdk-cgu.c183 u32 rate; member
241 int (*update_rate)(struct hsdk_cgu_clk *clk, unsigned long rate,
280 ulong (*set_rate)(struct clk *clk, ulong rate);
372 u64 rate; in pll_get() local
395 rate = (u64)PARENT_RATE * fbdiv; in pll_get()
396 do_div(rate, idiv * odiv); in pll_get()
398 return rate; in pll_get()
401 static unsigned long hsdk_pll_round_rate(struct clk *sclk, unsigned long rate) in hsdk_pll_round_rate() argument
408 if (pll_cfg[0].rate == 0) in hsdk_pll_round_rate()
411 best_rate = pll_cfg[0].rate; in hsdk_pll_round_rate()
[all …]
H A Dclk_sandbox.c13 ulong rate[SANDBOX_CLK_ID_COUNT]; member
24 return priv->rate[clk->id]; in sandbox_clk_get_rate()
27 static ulong sandbox_clk_set_rate(struct clk *clk, ulong rate) in sandbox_clk_set_rate() argument
35 if (!rate) in sandbox_clk_set_rate()
38 old_rate = priv->rate[clk->id]; in sandbox_clk_set_rate()
39 priv->rate[clk->id] = rate; in sandbox_clk_set_rate()
95 return priv->rate[id]; in sandbox_clk_query_rate()
/openbmc/u-boot/board/synopsys/hsdk/
H A Dclk-lib.c15 int soc_clk_ctl(const char *name, ulong *rate, enum clk_ctl_ops ctl) in soc_clk_ctl() argument
39 if ((ctl & CLK_SET) && rate) { in soc_clk_ctl()
40 priv_rate = ctl & CLK_MHZ ? (*rate) * HZ_IN_MHZ : *rate; in soc_clk_ctl()
63 if ((ctl & CLK_GET) && rate) in soc_clk_ctl()
64 *rate = priv_rate; in soc_clk_ctl()
67 printf("HSDK: clock '%s' rate %lu MHz\n", name, priv_rate); in soc_clk_ctl()
69 printf("HSDK: clock '%s' rate %lu Hz\n", name, priv_rate); in soc_clk_ctl()
71 debug("HSDK: clock '%s' rate %lu MHz\n", name, mhz_rate); in soc_clk_ctl()
H A Dclk-lib.h23 * set clock rate from 'rate' argument / read clock to 'rate' argument /
24 * print clock rate. If CLK_MHZ flag set in clk_ctl_ops 'rate' is in MHz,
35 int soc_clk_ctl(const char *name, ulong *rate, enum clk_ctl_ops ctl);
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3368.c60 /* Get pll rate by id */
139 * GPLL rate from the SPL stage. in rkclk_init()
159 u32 div, con, con_id, rate; in rk3368_mmc_get_clk() local
192 rate = DIV_TO_RATE(pll_rate, div); in rk3368_mmc_get_clk()
194 debug("%s: raw rate %d (post-divide by 2)\n", __func__, rate); in rk3368_mmc_get_clk()
195 return rate >> 1; in rk3368_mmc_get_clk()
199 ulong rate, in rk3368_mmc_find_best_rate_and_parent() argument
208 ulong rate; in rk3368_mmc_find_best_rate_and_parent() member
210 { .mux = MMC_PLL_SEL_CPLL, .rate = CPLL_HZ }, in rk3368_mmc_find_best_rate_and_parent()
211 { .mux = MMC_PLL_SEL_GPLL, .rate = GPLL_HZ }, in rk3368_mmc_find_best_rate_and_parent()
[all …]
/openbmc/u-boot/arch/arm/mach-zynq/
H A Dclk.c37 ulong rate; in set_cpu_clk_info() local
51 rate = clk_get_rate(&clk) / 1000000; in set_cpu_clk_info()
53 gd->bd->bi_ddr_freq = rate; in set_cpu_clk_info()
55 gd->bd->bi_arm_freq = rate; in set_cpu_clk_info()
85 unsigned long rate; in soc_clk_dump() local
92 rate = clk_get_rate(&clk); in soc_clk_dump()
96 if ((rate == (unsigned long)-ENOSYS) || in soc_clk_dump()
97 (rate == (unsigned long)-ENXIO)) in soc_clk_dump()
100 printf("%10s%20lu\n", name, rate); in soc_clk_dump()
/openbmc/u-boot/drivers/clk/sifive/
H A Dwrpll-cln28hpc.c80 * @post_divr_freq: input clock rate after the R divider
142 * __wrpll_calc_divq() - determine DIVQ based on target PLL output clock rate
143 * @target_rate: target PLL output clock rate
144 * @vco_rate: pointer to a u64 to store the computed VCO rate into
147 * target output rate @target_rate for the PLL. Along with returning the
149 * desired target VCO rate into the variable pointed to by @vco_rate.
184 * __wrpll_update_parent_rate() - update PLL data when parent rate changes
186 * @parent_rate: PLL input refclk rate (pre-R-divider)
189 * the PLL's reference clock rate changes. The intention is to avoid
190 * computation when the parent rate remains constant - expected to be
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dcommproc.c104 /* Set a baud rate generator. This needs lots of work. There are
108 * The baud rate clock is the system clock divided by something.
111 * Baud rate clocks are zero-based in the driver code (as that maps
121 m8560_cpm_setbrg(uint brg, uint rate) in m8560_cpm_setbrg() argument
136 *bp = (((((BRG_UART_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN; in m8560_cpm_setbrg()
139 /* This function is used to set high speed synchronous baud rate
143 m8560_cpm_fastbrg(uint brg, uint rate, int div16) in m8560_cpm_fastbrg() argument
158 *bp = (((((BRG_INT_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN; in m8560_cpm_fastbrg()
163 /* This function is used to set baud rate generators using an external
168 m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel) in m8560_cpm_extcbrg() argument
[all …]
/openbmc/u-boot/drivers/adc/
H A Dstm32-adc-core.c23 /* STM32 H7 maximum analog clock rate (from datasheet) */
62 unsigned long rate; in stm32h7_adc_clk_sel() local
79 * From spec: PLL output musn't exceed max rate in stm32h7_adc_clk_sel()
81 rate = clk_get_rate(&common->aclk); in stm32h7_adc_clk_sel()
82 if (!rate) { in stm32h7_adc_clk_sel()
83 dev_err(dev, "Invalid aclk rate: 0\n"); in stm32h7_adc_clk_sel()
95 if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE) in stm32h7_adc_clk_sel()
101 rate = clk_get_rate(&common->bclk); in stm32h7_adc_clk_sel()
102 if (!rate) { in stm32h7_adc_clk_sel()
103 dev_err(dev, "Invalid bus clock rate: 0\n"); in stm32h7_adc_clk_sel()
[all …]
/openbmc/u-boot/drivers/sound/
H A Dmax98088.c27 * codec mclk clock divider coefficients based on sampling rate
29 * @param rate sampling rate
34 static int rate_value(int rate, u8 *value) in rate_value() argument
39 if (rate_table[i] >= rate) { in rate_value()
53 * @rate: Sampling rate
58 int max98088_hw_params(struct maxim_priv *priv, unsigned int rate, in max98088_hw_params() argument
81 if (rate_value(rate, &regval)) { in max98088_hw_params()
82 debug("%s: Failed to set sample rate to %d.\n", in max98088_hw_params()
83 __func__, rate); in max98088_hw_params()
89 priv->rate = rate; in max98088_hw_params()
[all …]
/openbmc/u-boot/arch/arm/mach-tegra/
H A Dclock.c21 * This is our record of the current clock rate of each clock. We don't
237 * Given the parent's rate and the required rate for the children, this works
241 * @param parent_rate clock rate of parent clock in Hz
242 * @param rate required clock rate for this clock
246 unsigned long rate) in clk_get_divider() argument
251 divider += rate - 1; in clk_get_divider()
252 do_div(divider, rate); in clk_get_divider()
263 int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate) in clock_set_pllout() argument
274 div = clk_get_divider(8, pll_rate[clkid], rate); in clock_set_pllout()
292 * Given the parent's rate and the divider in 7.1 format, this works out the
[all …]
/openbmc/u-boot/include/
H A Daudio_codec.h22 * @rate: Sampling rate in Hz
28 int (*set_params)(struct udevice *dev, int interface, int rate,
39 * @rate: Sampling rate in Hz
45 int audio_codec_set_params(struct udevice *dev, int interface, int rate,

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