59  * Get the rate of the M-PLL clock from input clock frequency and
77  * Get the rate of the H-PLL clock from input clock frequency and
96  * Get the rate of the D-PLL clock from input clock frequency and
113  * Get the rate of the D2-PLL clock from input clock frequency and
140 	u32 rate = 0;  in ast2500_get_hclk()  local
142 	rate = ast2500_get_hpll_rate(scu);  in ast2500_get_hclk()
143 	return (rate / axi_div / ahb_div);  in ast2500_get_hclk()
148 	u32 rate = 0;  in ast2500_get_pclk()  local
152 	rate = ast2500_get_hpll_rate(scu);  in ast2500_get_pclk()
154 	return (rate / apb_div);  in ast2500_get_pclk()
194 	ulong rate;  in ast2500_clk_get_rate()  local
198 		rate = ast2500_get_hpll_rate(priv->scu);  in ast2500_clk_get_rate()
201 		rate = ast2500_get_mpll_rate(priv->scu);  in ast2500_clk_get_rate()
204 		rate = ast2500_get_dpll_rate(priv->scu);  in ast2500_clk_get_rate()
207 		rate = ast2500_get_d2pll_rate(priv->scu);  in ast2500_clk_get_rate()
210 		rate = ast2500_get_hclk(priv->scu);  in ast2500_clk_get_rate()
213 		rate = ast2500_get_pclk(priv->scu);  in ast2500_clk_get_rate()
216 		rate = ast2500_get_uart_clk_rate(priv->scu, 1);  in ast2500_clk_get_rate()
219 		rate = ast2500_get_uart_clk_rate(priv->scu, 2);  in ast2500_clk_get_rate()
222 		rate = ast2500_get_uart_clk_rate(priv->scu, 3);  in ast2500_clk_get_rate()
225 		rate = ast2500_get_uart_clk_rate(priv->scu, 4);  in ast2500_clk_get_rate()
228 		rate = ast2500_get_uart_clk_rate(priv->scu, 5);  in ast2500_clk_get_rate()
231 		rate = ast2500_get_sdio_clk_rate(priv->scu);  in ast2500_clk_get_rate()
234 		pr_debug("can't get clk rate \n");  in ast2500_clk_get_rate()
239 	return rate;  in ast2500_clk_get_rate()
244 	ulong rate;  member
262 		    default_cfg->rate == requested_rate) {  in ast2500_get_clock_config_default()
272  * @input_rate - the rate of input clock in Hz
273  * @requested_rate - desired output rate in Hz
279  * @return The clock rate, when the resulting div_config is used.
313 			/* Keep the rate below requested one. */  in ast2500_calc_clock_config()
329 static ulong ast2500_configure_ddr(struct ast2500_scu *scu, ulong rate)  in ast2500_configure_ddr()  argument
339 	ast2500_calc_clock_config(clkin, rate, &div_cfg);  in ast2500_configure_ddr()
353 static ulong ast2500_configure_d2pll(struct ast2500_scu *scu, ulong rate)  in ast2500_configure_d2pll()  argument
384 	new_rate = ast2500_calc_clock_config(clkin, rate, &div_cfg);  in ast2500_configure_d2pll()
404 static unsigned long ast2500_clk_set_rate(struct clk *clk, ulong rate)  in ast2500_clk_set_rate()  argument
412 		new_rate = ast2500_configure_ddr(priv->scu, rate);  in ast2500_clk_set_rate()
416 		new_rate = ast2500_configure_d2pll(priv->scu, rate);  in ast2500_clk_set_rate()
586 	 * For MAC clocks the clock rate is  in ast2500_clk_enable()
668 	unsigned long rate;  in soc_clk_dump()  local
687 		rate = ret;  in soc_clk_dump()
703 		       aspeed_clk_names[i].name, aspeed_clk_names[i].id, rate);  in soc_clk_dump()