1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
232c1a6eeSPurna Chandra Mandal /*
332c1a6eeSPurna Chandra Mandal * Copyright (C) 2015
432c1a6eeSPurna Chandra Mandal * Purna Chandra Mandal <purna.mandal@microchip.com>
532c1a6eeSPurna Chandra Mandal *
632c1a6eeSPurna Chandra Mandal */
732c1a6eeSPurna Chandra Mandal #include <common.h>
8be961fa1SPurna Chandra Mandal #include <clk.h>
9be961fa1SPurna Chandra Mandal #include <dm.h>
10be961fa1SPurna Chandra Mandal #include <mach/pic32.h>
11be961fa1SPurna Chandra Mandal #include <mach/ddr.h>
12be961fa1SPurna Chandra Mandal #include <dt-bindings/clock/microchip,clock.h>
1332c1a6eeSPurna Chandra Mandal
14be961fa1SPurna Chandra Mandal /* Flash prefetch */
15be961fa1SPurna Chandra Mandal #define PRECON 0x00
16be961fa1SPurna Chandra Mandal
17be961fa1SPurna Chandra Mandal /* Flash ECCCON */
18be961fa1SPurna Chandra Mandal #define ECC_MASK 0x03
19be961fa1SPurna Chandra Mandal #define ECC_SHIFT 4
20be961fa1SPurna Chandra Mandal
21be961fa1SPurna Chandra Mandal #define CLK_MHZ(x) ((x) / 1000000)
22be961fa1SPurna Chandra Mandal
23be961fa1SPurna Chandra Mandal DECLARE_GLOBAL_DATA_PTR;
24be961fa1SPurna Chandra Mandal
rate(int id)25135aa950SStephen Warren static ulong rate(int id)
2632c1a6eeSPurna Chandra Mandal {
27be961fa1SPurna Chandra Mandal int ret;
28be961fa1SPurna Chandra Mandal struct udevice *dev;
29135aa950SStephen Warren struct clk clk;
30135aa950SStephen Warren ulong rate;
31be961fa1SPurna Chandra Mandal
32be961fa1SPurna Chandra Mandal ret = uclass_get_device(UCLASS_CLK, 0, &dev);
33be961fa1SPurna Chandra Mandal if (ret) {
34135aa950SStephen Warren printf("clk-uclass not found\n");
3532c1a6eeSPurna Chandra Mandal return 0;
3632c1a6eeSPurna Chandra Mandal }
37be961fa1SPurna Chandra Mandal
38135aa950SStephen Warren clk.id = id;
39135aa950SStephen Warren ret = clk_request(dev, &clk);
40135aa950SStephen Warren if (ret < 0)
41135aa950SStephen Warren return ret;
42135aa950SStephen Warren
43135aa950SStephen Warren rate = clk_get_rate(&clk);
44135aa950SStephen Warren
45135aa950SStephen Warren clk_free(&clk);
46135aa950SStephen Warren
47135aa950SStephen Warren return rate;
48135aa950SStephen Warren }
49135aa950SStephen Warren
clk_get_cpu_rate(void)50135aa950SStephen Warren static ulong clk_get_cpu_rate(void)
51135aa950SStephen Warren {
52135aa950SStephen Warren return rate(PB7CLK);
53be961fa1SPurna Chandra Mandal }
54be961fa1SPurna Chandra Mandal
55be961fa1SPurna Chandra Mandal /* initialize prefetch module related to cpu_clk */
prefetch_init(void)56be961fa1SPurna Chandra Mandal static void prefetch_init(void)
57be961fa1SPurna Chandra Mandal {
58be961fa1SPurna Chandra Mandal struct pic32_reg_atomic *regs;
59be961fa1SPurna Chandra Mandal const void __iomem *base;
60be961fa1SPurna Chandra Mandal int v, nr_waits;
61be961fa1SPurna Chandra Mandal ulong rate;
62be961fa1SPurna Chandra Mandal
63be961fa1SPurna Chandra Mandal /* cpu frequency in MHZ */
64be961fa1SPurna Chandra Mandal rate = clk_get_cpu_rate() / 1000000;
65be961fa1SPurna Chandra Mandal
66be961fa1SPurna Chandra Mandal /* get flash ECC type */
67be961fa1SPurna Chandra Mandal base = pic32_get_syscfg_base();
68be961fa1SPurna Chandra Mandal v = (readl(base + CFGCON) >> ECC_SHIFT) & ECC_MASK;
69be961fa1SPurna Chandra Mandal
70be961fa1SPurna Chandra Mandal if (v < 2) {
71be961fa1SPurna Chandra Mandal if (rate < 66)
72be961fa1SPurna Chandra Mandal nr_waits = 0;
73be961fa1SPurna Chandra Mandal else if (rate < 133)
74be961fa1SPurna Chandra Mandal nr_waits = 1;
75be961fa1SPurna Chandra Mandal else
76be961fa1SPurna Chandra Mandal nr_waits = 2;
77be961fa1SPurna Chandra Mandal } else {
78be961fa1SPurna Chandra Mandal if (rate <= 83)
79be961fa1SPurna Chandra Mandal nr_waits = 0;
80be961fa1SPurna Chandra Mandal else if (rate <= 166)
81be961fa1SPurna Chandra Mandal nr_waits = 1;
82be961fa1SPurna Chandra Mandal else
83be961fa1SPurna Chandra Mandal nr_waits = 2;
84be961fa1SPurna Chandra Mandal }
85be961fa1SPurna Chandra Mandal
86be961fa1SPurna Chandra Mandal regs = ioremap(PREFETCH_BASE + PRECON, sizeof(*regs));
87be961fa1SPurna Chandra Mandal writel(nr_waits, ®s->raw);
88be961fa1SPurna Chandra Mandal
89be961fa1SPurna Chandra Mandal /* Enable prefetch for all */
90be961fa1SPurna Chandra Mandal writel(0x30, ®s->set);
91be961fa1SPurna Chandra Mandal iounmap(regs);
92be961fa1SPurna Chandra Mandal }
93be961fa1SPurna Chandra Mandal
94be961fa1SPurna Chandra Mandal /* arch specific CPU init after DM */
arch_cpu_init_dm(void)95be961fa1SPurna Chandra Mandal int arch_cpu_init_dm(void)
96be961fa1SPurna Chandra Mandal {
97be961fa1SPurna Chandra Mandal /* flash prefetch */
98be961fa1SPurna Chandra Mandal prefetch_init();
99be961fa1SPurna Chandra Mandal return 0;
100be961fa1SPurna Chandra Mandal }
101be961fa1SPurna Chandra Mandal
102be961fa1SPurna Chandra Mandal /* Un-gate DDR2 modules (gated by default) */
ddr2_pmd_ungate(void)103be961fa1SPurna Chandra Mandal static void ddr2_pmd_ungate(void)
104be961fa1SPurna Chandra Mandal {
105be961fa1SPurna Chandra Mandal void __iomem *regs;
106be961fa1SPurna Chandra Mandal
107be961fa1SPurna Chandra Mandal regs = pic32_get_syscfg_base();
108be961fa1SPurna Chandra Mandal writel(0, regs + PMD7);
109be961fa1SPurna Chandra Mandal }
110be961fa1SPurna Chandra Mandal
111be961fa1SPurna Chandra Mandal /* initialize the DDR2 Controller and DDR2 PHY */
dram_init(void)112f1683aa7SSimon Glass int dram_init(void)
113be961fa1SPurna Chandra Mandal {
114be961fa1SPurna Chandra Mandal ddr2_pmd_ungate();
115be961fa1SPurna Chandra Mandal ddr2_phy_init();
116be961fa1SPurna Chandra Mandal ddr2_ctrl_init();
117088454cdSSimon Glass gd->ram_size = ddr2_calculate_size();
118088454cdSSimon Glass
119088454cdSSimon Glass return 0;
120be961fa1SPurna Chandra Mandal }
121be961fa1SPurna Chandra Mandal
misc_init_r(void)122be961fa1SPurna Chandra Mandal int misc_init_r(void)
123be961fa1SPurna Chandra Mandal {
124be961fa1SPurna Chandra Mandal set_io_port_base(0);
125be961fa1SPurna Chandra Mandal return 0;
126be961fa1SPurna Chandra Mandal }
127be961fa1SPurna Chandra Mandal
128be961fa1SPurna Chandra Mandal #ifdef CONFIG_DISPLAY_BOARDINFO
get_core_name(void)129be961fa1SPurna Chandra Mandal const char *get_core_name(void)
130be961fa1SPurna Chandra Mandal {
131be961fa1SPurna Chandra Mandal u32 proc_id;
132be961fa1SPurna Chandra Mandal const char *str;
133be961fa1SPurna Chandra Mandal
134be961fa1SPurna Chandra Mandal proc_id = read_c0_prid();
135be961fa1SPurna Chandra Mandal switch (proc_id) {
136be961fa1SPurna Chandra Mandal case 0x19e28:
137be961fa1SPurna Chandra Mandal str = "PIC32MZ[DA]";
138be961fa1SPurna Chandra Mandal break;
139be961fa1SPurna Chandra Mandal default:
140be961fa1SPurna Chandra Mandal str = "UNKNOWN";
141be961fa1SPurna Chandra Mandal }
142be961fa1SPurna Chandra Mandal
143be961fa1SPurna Chandra Mandal return str;
144be961fa1SPurna Chandra Mandal }
145be961fa1SPurna Chandra Mandal #endif
146be961fa1SPurna Chandra Mandal #ifdef CONFIG_CMD_CLK
147135aa950SStephen Warren
soc_clk_dump(void)148be961fa1SPurna Chandra Mandal int soc_clk_dump(void)
149be961fa1SPurna Chandra Mandal {
150135aa950SStephen Warren int i;
151be961fa1SPurna Chandra Mandal
152be961fa1SPurna Chandra Mandal printf("PLL Speed: %lu MHz\n",
153135aa950SStephen Warren CLK_MHZ(rate(PLLCLK)));
154135aa950SStephen Warren
155135aa950SStephen Warren printf("CPU Speed: %lu MHz\n", CLK_MHZ(rate(PB7CLK)));
156135aa950SStephen Warren
157135aa950SStephen Warren printf("MPLL Speed: %lu MHz\n", CLK_MHZ(rate(MPLL)));
158be961fa1SPurna Chandra Mandal
159be961fa1SPurna Chandra Mandal for (i = PB1CLK; i <= PB7CLK; i++)
160be961fa1SPurna Chandra Mandal printf("PB%d Clock Speed: %lu MHz\n", i - PB1CLK + 1,
161135aa950SStephen Warren CLK_MHZ(rate(i)));
162be961fa1SPurna Chandra Mandal
163be961fa1SPurna Chandra Mandal for (i = REF1CLK; i <= REF5CLK; i++)
164be961fa1SPurna Chandra Mandal printf("REFO%d Clock Speed: %lu MHz\n", i - REF1CLK + 1,
165135aa950SStephen Warren CLK_MHZ(rate(i)));
166be961fa1SPurna Chandra Mandal return 0;
167be961fa1SPurna Chandra Mandal }
168be961fa1SPurna Chandra Mandal #endif
169