183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2dedb60fbSMarek Vasut /*
3dedb60fbSMarek Vasut * Renesas RCar Gen2 CPG MSSR driver
4dedb60fbSMarek Vasut *
5dedb60fbSMarek Vasut * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
6dedb60fbSMarek Vasut *
7dedb60fbSMarek Vasut * Based on the following driver from Linux kernel:
8dedb60fbSMarek Vasut * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
9dedb60fbSMarek Vasut *
10dedb60fbSMarek Vasut * Copyright (C) 2016 Glider bvba
11dedb60fbSMarek Vasut */
12dedb60fbSMarek Vasut
13dedb60fbSMarek Vasut #include <common.h>
14dedb60fbSMarek Vasut #include <clk-uclass.h>
15dedb60fbSMarek Vasut #include <dm.h>
16dedb60fbSMarek Vasut #include <errno.h>
17dedb60fbSMarek Vasut #include <asm/io.h>
18dedb60fbSMarek Vasut
19dedb60fbSMarek Vasut #include <dt-bindings/clock/renesas-cpg-mssr.h>
20dedb60fbSMarek Vasut
21dedb60fbSMarek Vasut #include "renesas-cpg-mssr.h"
22dedb60fbSMarek Vasut #include "rcar-gen2-cpg.h"
23dedb60fbSMarek Vasut
24dedb60fbSMarek Vasut #define CPG_RST_MODEMR 0x0060
25dedb60fbSMarek Vasut
26dedb60fbSMarek Vasut #define CPG_PLL0CR 0x00d8
27dedb60fbSMarek Vasut #define CPG_SDCKCR 0x0074
28dedb60fbSMarek Vasut
29dedb60fbSMarek Vasut struct clk_div_table {
30dedb60fbSMarek Vasut u8 val;
31dedb60fbSMarek Vasut u8 div;
32dedb60fbSMarek Vasut };
33dedb60fbSMarek Vasut
34dedb60fbSMarek Vasut /* SDHI divisors */
35dedb60fbSMarek Vasut static const struct clk_div_table cpg_sdh_div_table[] = {
36dedb60fbSMarek Vasut { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
37dedb60fbSMarek Vasut { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
38dedb60fbSMarek Vasut { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
39dedb60fbSMarek Vasut };
40dedb60fbSMarek Vasut
41dedb60fbSMarek Vasut static const struct clk_div_table cpg_sd01_div_table[] = {
42dedb60fbSMarek Vasut { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
43dedb60fbSMarek Vasut { 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
44dedb60fbSMarek Vasut { 0, 0 },
45dedb60fbSMarek Vasut };
46dedb60fbSMarek Vasut
gen2_clk_get_sdh_div(const struct clk_div_table * table,u8 val)4745b01b46SMarek Vasut static u8 gen2_clk_get_sdh_div(const struct clk_div_table *table, u8 val)
48dedb60fbSMarek Vasut {
4945b01b46SMarek Vasut for (;;) {
5045b01b46SMarek Vasut if (!(*table).div)
51dedb60fbSMarek Vasut return 0xff;
5245b01b46SMarek Vasut
5345b01b46SMarek Vasut if ((*table).val == val)
5445b01b46SMarek Vasut return (*table).div;
5545b01b46SMarek Vasut
5645b01b46SMarek Vasut table++;
5745b01b46SMarek Vasut }
58dedb60fbSMarek Vasut }
59dedb60fbSMarek Vasut
gen2_clk_enable(struct clk * clk)60dedb60fbSMarek Vasut static int gen2_clk_enable(struct clk *clk)
61dedb60fbSMarek Vasut {
62dedb60fbSMarek Vasut struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
63dedb60fbSMarek Vasut
64dedb60fbSMarek Vasut return renesas_clk_endisable(clk, priv->base, true);
65dedb60fbSMarek Vasut }
66dedb60fbSMarek Vasut
gen2_clk_disable(struct clk * clk)67dedb60fbSMarek Vasut static int gen2_clk_disable(struct clk *clk)
68dedb60fbSMarek Vasut {
69dedb60fbSMarek Vasut struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
70dedb60fbSMarek Vasut
71dedb60fbSMarek Vasut return renesas_clk_endisable(clk, priv->base, false);
72dedb60fbSMarek Vasut }
73dedb60fbSMarek Vasut
gen2_clk_get_rate(struct clk * clk)74dedb60fbSMarek Vasut static ulong gen2_clk_get_rate(struct clk *clk)
75dedb60fbSMarek Vasut {
76dedb60fbSMarek Vasut struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
77dedb60fbSMarek Vasut struct cpg_mssr_info *info = priv->info;
78dedb60fbSMarek Vasut struct clk parent;
79dedb60fbSMarek Vasut const struct cpg_core_clk *core;
80dedb60fbSMarek Vasut const struct rcar_gen2_cpg_pll_config *pll_config =
81dedb60fbSMarek Vasut priv->cpg_pll_config;
82dedb60fbSMarek Vasut u32 value, mult, div, rate = 0;
83dedb60fbSMarek Vasut int ret;
84dedb60fbSMarek Vasut
85dedb60fbSMarek Vasut debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
86dedb60fbSMarek Vasut
87dedb60fbSMarek Vasut ret = renesas_clk_get_parent(clk, info, &parent);
88dedb60fbSMarek Vasut if (ret) {
89dedb60fbSMarek Vasut printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
90dedb60fbSMarek Vasut return ret;
91dedb60fbSMarek Vasut }
92dedb60fbSMarek Vasut
93dedb60fbSMarek Vasut if (renesas_clk_is_mod(clk)) {
94dedb60fbSMarek Vasut rate = gen2_clk_get_rate(&parent);
95dedb60fbSMarek Vasut debug("%s[%i] MOD clk: parent=%lu => rate=%u\n",
96dedb60fbSMarek Vasut __func__, __LINE__, parent.id, rate);
97dedb60fbSMarek Vasut return rate;
98dedb60fbSMarek Vasut }
99dedb60fbSMarek Vasut
100dedb60fbSMarek Vasut ret = renesas_clk_get_core(clk, info, &core);
101dedb60fbSMarek Vasut if (ret)
102dedb60fbSMarek Vasut return ret;
103dedb60fbSMarek Vasut
104dedb60fbSMarek Vasut switch (core->type) {
105dedb60fbSMarek Vasut case CLK_TYPE_IN:
106dedb60fbSMarek Vasut if (core->id == info->clk_extal_id) {
107dedb60fbSMarek Vasut rate = clk_get_rate(&priv->clk_extal);
108dedb60fbSMarek Vasut debug("%s[%i] EXTAL clk: rate=%u\n",
109dedb60fbSMarek Vasut __func__, __LINE__, rate);
110dedb60fbSMarek Vasut return rate;
111dedb60fbSMarek Vasut }
112dedb60fbSMarek Vasut
113dedb60fbSMarek Vasut if (core->id == info->clk_extal_usb_id) {
114dedb60fbSMarek Vasut rate = clk_get_rate(&priv->clk_extal_usb);
115dedb60fbSMarek Vasut debug("%s[%i] EXTALR clk: rate=%u\n",
116dedb60fbSMarek Vasut __func__, __LINE__, rate);
117dedb60fbSMarek Vasut return rate;
118dedb60fbSMarek Vasut }
119dedb60fbSMarek Vasut
120dedb60fbSMarek Vasut return -EINVAL;
121dedb60fbSMarek Vasut
122dedb60fbSMarek Vasut case CLK_TYPE_FF:
123dedb60fbSMarek Vasut rate = (gen2_clk_get_rate(&parent) * core->mult) / core->div;
1244b135d54SMarek Vasut debug("%s[%i] FIXED clk: parent=%i mul=%i div=%i => rate=%u\n",
125dedb60fbSMarek Vasut __func__, __LINE__,
126dedb60fbSMarek Vasut core->parent, core->mult, core->div, rate);
127dedb60fbSMarek Vasut return rate;
128dedb60fbSMarek Vasut
129dedb60fbSMarek Vasut case CLK_TYPE_DIV6P1: /* DIV6 Clock with 1 parent clock */
130dedb60fbSMarek Vasut value = (readl(priv->base + core->offset) & 0x3f) + 1;
131dedb60fbSMarek Vasut rate = gen2_clk_get_rate(&parent) / value;
132dedb60fbSMarek Vasut debug("%s[%i] DIV6P1 clk: parent=%i div=%i => rate=%u\n",
133dedb60fbSMarek Vasut __func__, __LINE__,
134dedb60fbSMarek Vasut core->parent, value, rate);
135dedb60fbSMarek Vasut return rate;
136dedb60fbSMarek Vasut
137dedb60fbSMarek Vasut case CLK_TYPE_GEN2_MAIN:
138dedb60fbSMarek Vasut rate = gen2_clk_get_rate(&parent) / pll_config->extal_div;
139dedb60fbSMarek Vasut debug("%s[%i] MAIN clk: parent=%i extal_div=%i => rate=%u\n",
140dedb60fbSMarek Vasut __func__, __LINE__,
141dedb60fbSMarek Vasut core->parent, pll_config->extal_div, rate);
142dedb60fbSMarek Vasut return rate;
143dedb60fbSMarek Vasut
144dedb60fbSMarek Vasut case CLK_TYPE_GEN2_PLL0:
145dedb60fbSMarek Vasut /*
146dedb60fbSMarek Vasut * PLL0 is a configurable multiplier clock except on R-Car
147dedb60fbSMarek Vasut * V2H/E2. Register the PLL0 clock as a fixed factor clock for
148dedb60fbSMarek Vasut * now as there's no generic multiplier clock implementation and
149dedb60fbSMarek Vasut * we currently have no need to change the multiplier value.
150dedb60fbSMarek Vasut */
151dedb60fbSMarek Vasut mult = pll_config->pll0_mult;
152dedb60fbSMarek Vasut if (!mult) {
153dedb60fbSMarek Vasut value = readl(priv->base + CPG_PLL0CR);
154dedb60fbSMarek Vasut mult = (((value >> 24) & 0x7f) + 1) * 2;
155dedb60fbSMarek Vasut }
156dedb60fbSMarek Vasut
157dedb60fbSMarek Vasut rate = (gen2_clk_get_rate(&parent) * mult) / info->pll0_div;
158dedb60fbSMarek Vasut debug("%s[%i] PLL0 clk: parent=%i mult=%u => rate=%u\n",
159dedb60fbSMarek Vasut __func__, __LINE__, core->parent, mult, rate);
160dedb60fbSMarek Vasut return rate;
161dedb60fbSMarek Vasut
162dedb60fbSMarek Vasut case CLK_TYPE_GEN2_PLL1:
163dedb60fbSMarek Vasut rate = (gen2_clk_get_rate(&parent) * pll_config->pll1_mult) / 2;
164dedb60fbSMarek Vasut debug("%s[%i] PLL1 clk: parent=%i mul=%i => rate=%u\n",
165dedb60fbSMarek Vasut __func__, __LINE__,
166dedb60fbSMarek Vasut core->parent, pll_config->pll1_mult, rate);
167dedb60fbSMarek Vasut return rate;
168dedb60fbSMarek Vasut
169dedb60fbSMarek Vasut case CLK_TYPE_GEN2_PLL3:
170dedb60fbSMarek Vasut rate = gen2_clk_get_rate(&parent) * pll_config->pll3_mult;
171dedb60fbSMarek Vasut debug("%s[%i] PLL3 clk: parent=%i mul=%i => rate=%u\n",
172dedb60fbSMarek Vasut __func__, __LINE__,
173dedb60fbSMarek Vasut core->parent, pll_config->pll3_mult, rate);
174dedb60fbSMarek Vasut return rate;
175dedb60fbSMarek Vasut
176dedb60fbSMarek Vasut case CLK_TYPE_GEN2_SDH:
177dedb60fbSMarek Vasut value = (readl(priv->base + CPG_SDCKCR) >> 8) & 0xf;
178dedb60fbSMarek Vasut div = gen2_clk_get_sdh_div(cpg_sdh_div_table, value);
179dedb60fbSMarek Vasut rate = gen2_clk_get_rate(&parent) / div;
180dedb60fbSMarek Vasut debug("%s[%i] SDH clk: parent=%i div=%i => rate=%u\n",
181dedb60fbSMarek Vasut __func__, __LINE__,
182dedb60fbSMarek Vasut core->parent, div, rate);
183dedb60fbSMarek Vasut return rate;
184dedb60fbSMarek Vasut
185dedb60fbSMarek Vasut case CLK_TYPE_GEN2_SD0:
186dedb60fbSMarek Vasut value = (readl(priv->base + CPG_SDCKCR) >> 4) & 0xf;
187dedb60fbSMarek Vasut div = gen2_clk_get_sdh_div(cpg_sd01_div_table, value);
188dedb60fbSMarek Vasut rate = gen2_clk_get_rate(&parent) / div;
189dedb60fbSMarek Vasut debug("%s[%i] SD0 clk: parent=%i div=%i => rate=%u\n",
190dedb60fbSMarek Vasut __func__, __LINE__,
191dedb60fbSMarek Vasut core->parent, div, rate);
192dedb60fbSMarek Vasut return rate;
193dedb60fbSMarek Vasut
194dedb60fbSMarek Vasut case CLK_TYPE_GEN2_SD1:
195dedb60fbSMarek Vasut value = (readl(priv->base + CPG_SDCKCR) >> 0) & 0xf;
196dedb60fbSMarek Vasut div = gen2_clk_get_sdh_div(cpg_sd01_div_table, value);
197dedb60fbSMarek Vasut rate = gen2_clk_get_rate(&parent) / div;
198dedb60fbSMarek Vasut debug("%s[%i] SD1 clk: parent=%i div=%i => rate=%u\n",
199dedb60fbSMarek Vasut __func__, __LINE__,
200dedb60fbSMarek Vasut core->parent, div, rate);
201dedb60fbSMarek Vasut return rate;
202dedb60fbSMarek Vasut }
203dedb60fbSMarek Vasut
204dedb60fbSMarek Vasut printf("%s[%i] unknown fail\n", __func__, __LINE__);
205dedb60fbSMarek Vasut
206dedb60fbSMarek Vasut return -ENOENT;
207dedb60fbSMarek Vasut }
208dedb60fbSMarek Vasut
gen2_clk_setup_mmcif_div(struct clk * clk,ulong rate)209*3cb2849cSMarek Vasut static int gen2_clk_setup_mmcif_div(struct clk *clk, ulong rate)
210*3cb2849cSMarek Vasut {
211*3cb2849cSMarek Vasut struct gen2_clk_priv *priv = dev_get_priv(clk->dev);
212*3cb2849cSMarek Vasut struct cpg_mssr_info *info = priv->info;
213*3cb2849cSMarek Vasut const struct cpg_core_clk *core;
214*3cb2849cSMarek Vasut struct clk parent, pparent;
215*3cb2849cSMarek Vasut u32 val;
216*3cb2849cSMarek Vasut int ret;
217*3cb2849cSMarek Vasut
218*3cb2849cSMarek Vasut ret = renesas_clk_get_parent(clk, info, &parent);
219*3cb2849cSMarek Vasut if (ret) {
220*3cb2849cSMarek Vasut debug("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
221*3cb2849cSMarek Vasut return ret;
222*3cb2849cSMarek Vasut }
223*3cb2849cSMarek Vasut
224*3cb2849cSMarek Vasut if (renesas_clk_is_mod(&parent))
225*3cb2849cSMarek Vasut return 0;
226*3cb2849cSMarek Vasut
227*3cb2849cSMarek Vasut ret = renesas_clk_get_core(&parent, info, &core);
228*3cb2849cSMarek Vasut if (ret)
229*3cb2849cSMarek Vasut return ret;
230*3cb2849cSMarek Vasut
231*3cb2849cSMarek Vasut if (strcmp(core->name, "mmc0") && strcmp(core->name, "mmc1"))
232*3cb2849cSMarek Vasut return 0;
233*3cb2849cSMarek Vasut
234*3cb2849cSMarek Vasut ret = renesas_clk_get_parent(&parent, info, &pparent);
235*3cb2849cSMarek Vasut if (ret) {
236*3cb2849cSMarek Vasut debug("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
237*3cb2849cSMarek Vasut return ret;
238*3cb2849cSMarek Vasut }
239*3cb2849cSMarek Vasut
240*3cb2849cSMarek Vasut val = (gen2_clk_get_rate(&pparent) / rate) - 1;
241*3cb2849cSMarek Vasut
242*3cb2849cSMarek Vasut debug("%s[%i] MMCIF offset=%x\n", __func__, __LINE__, core->offset);
243*3cb2849cSMarek Vasut
244*3cb2849cSMarek Vasut writel(val, priv->base + core->offset);
245*3cb2849cSMarek Vasut
246*3cb2849cSMarek Vasut return 0;
247*3cb2849cSMarek Vasut }
248*3cb2849cSMarek Vasut
gen2_clk_set_rate(struct clk * clk,ulong rate)249dedb60fbSMarek Vasut static ulong gen2_clk_set_rate(struct clk *clk, ulong rate)
250dedb60fbSMarek Vasut {
251*3cb2849cSMarek Vasut /* Force correct MMC-IF divider configuration if applicable */
252*3cb2849cSMarek Vasut gen2_clk_setup_mmcif_div(clk, rate);
253dedb60fbSMarek Vasut return gen2_clk_get_rate(clk);
254dedb60fbSMarek Vasut }
255dedb60fbSMarek Vasut
gen2_clk_of_xlate(struct clk * clk,struct ofnode_phandle_args * args)256dedb60fbSMarek Vasut static int gen2_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
257dedb60fbSMarek Vasut {
258dedb60fbSMarek Vasut if (args->args_count != 2) {
259dedb60fbSMarek Vasut debug("Invaild args_count: %d\n", args->args_count);
260dedb60fbSMarek Vasut return -EINVAL;
261dedb60fbSMarek Vasut }
262dedb60fbSMarek Vasut
263dedb60fbSMarek Vasut clk->id = (args->args[0] << 16) | args->args[1];
264dedb60fbSMarek Vasut
265dedb60fbSMarek Vasut return 0;
266dedb60fbSMarek Vasut }
267dedb60fbSMarek Vasut
268dedb60fbSMarek Vasut const struct clk_ops gen2_clk_ops = {
269dedb60fbSMarek Vasut .enable = gen2_clk_enable,
270dedb60fbSMarek Vasut .disable = gen2_clk_disable,
271dedb60fbSMarek Vasut .get_rate = gen2_clk_get_rate,
272dedb60fbSMarek Vasut .set_rate = gen2_clk_set_rate,
273dedb60fbSMarek Vasut .of_xlate = gen2_clk_of_xlate,
274dedb60fbSMarek Vasut };
275dedb60fbSMarek Vasut
gen2_clk_probe(struct udevice * dev)276dedb60fbSMarek Vasut int gen2_clk_probe(struct udevice *dev)
277dedb60fbSMarek Vasut {
278dedb60fbSMarek Vasut struct gen2_clk_priv *priv = dev_get_priv(dev);
279dedb60fbSMarek Vasut struct cpg_mssr_info *info =
280dedb60fbSMarek Vasut (struct cpg_mssr_info *)dev_get_driver_data(dev);
281dedb60fbSMarek Vasut fdt_addr_t rst_base;
282dedb60fbSMarek Vasut u32 cpg_mode;
283dedb60fbSMarek Vasut int ret;
284dedb60fbSMarek Vasut
285dedb60fbSMarek Vasut priv->base = (struct gen2_base *)devfdt_get_addr(dev);
286dedb60fbSMarek Vasut if (!priv->base)
287dedb60fbSMarek Vasut return -EINVAL;
288dedb60fbSMarek Vasut
289dedb60fbSMarek Vasut priv->info = info;
290dedb60fbSMarek Vasut ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, info->reset_node);
291dedb60fbSMarek Vasut if (ret < 0)
292dedb60fbSMarek Vasut return ret;
293dedb60fbSMarek Vasut
294dedb60fbSMarek Vasut rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg");
295dedb60fbSMarek Vasut if (rst_base == FDT_ADDR_T_NONE)
296dedb60fbSMarek Vasut return -EINVAL;
297dedb60fbSMarek Vasut
298dedb60fbSMarek Vasut cpg_mode = readl(rst_base + CPG_RST_MODEMR);
299dedb60fbSMarek Vasut
300dedb60fbSMarek Vasut priv->cpg_pll_config =
301dedb60fbSMarek Vasut (struct rcar_gen2_cpg_pll_config *)info->get_pll_config(cpg_mode);
302dedb60fbSMarek Vasut if (!priv->cpg_pll_config->extal_div)
303dedb60fbSMarek Vasut return -EINVAL;
304dedb60fbSMarek Vasut
305dedb60fbSMarek Vasut ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
306dedb60fbSMarek Vasut if (ret < 0)
307dedb60fbSMarek Vasut return ret;
308dedb60fbSMarek Vasut
309dedb60fbSMarek Vasut if (info->extal_usb_node) {
310dedb60fbSMarek Vasut ret = clk_get_by_name(dev, info->extal_usb_node,
311dedb60fbSMarek Vasut &priv->clk_extal_usb);
312dedb60fbSMarek Vasut if (ret < 0)
313dedb60fbSMarek Vasut return ret;
314dedb60fbSMarek Vasut }
315dedb60fbSMarek Vasut
316dedb60fbSMarek Vasut return 0;
317dedb60fbSMarek Vasut }
318dedb60fbSMarek Vasut
gen2_clk_remove(struct udevice * dev)319dedb60fbSMarek Vasut int gen2_clk_remove(struct udevice *dev)
320dedb60fbSMarek Vasut {
321dedb60fbSMarek Vasut struct gen2_clk_priv *priv = dev_get_priv(dev);
322dedb60fbSMarek Vasut
323dedb60fbSMarek Vasut return renesas_clk_remove(priv->base, priv->info);
324dedb60fbSMarek Vasut }
325