1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 22459afb1SQianyu Gong /* 32459afb1SQianyu Gong * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. 42459afb1SQianyu Gong * 52459afb1SQianyu Gong * Dave Liu <daveliu@freescale.com> 62459afb1SQianyu Gong * based on source code of Shlomi Gridish 72459afb1SQianyu Gong */ 82459afb1SQianyu Gong 92459afb1SQianyu Gong #ifndef __QE_H__ 102459afb1SQianyu Gong #define __QE_H__ 112459afb1SQianyu Gong 122459afb1SQianyu Gong #include "common.h" 132459afb1SQianyu Gong #ifdef CONFIG_U_QE 142459afb1SQianyu Gong #include <linux/immap_qe.h> 152459afb1SQianyu Gong #endif 162459afb1SQianyu Gong 172459afb1SQianyu Gong #define QE_NUM_OF_BRGS 16 182459afb1SQianyu Gong #define UCC_MAX_NUM 8 192459afb1SQianyu Gong 202459afb1SQianyu Gong #define QE_DATAONLY_BASE 0 212459afb1SQianyu Gong #define QE_DATAONLY_SIZE (QE_MURAM_SIZE - QE_DATAONLY_BASE) 222459afb1SQianyu Gong 232459afb1SQianyu Gong /* QE threads SNUM 242459afb1SQianyu Gong */ 252459afb1SQianyu Gong typedef enum qe_snum_state { 262459afb1SQianyu Gong QE_SNUM_STATE_USED, /* used */ 272459afb1SQianyu Gong QE_SNUM_STATE_FREE /* free */ 282459afb1SQianyu Gong } qe_snum_state_e; 292459afb1SQianyu Gong 302459afb1SQianyu Gong typedef struct qe_snum { 312459afb1SQianyu Gong u8 num; /* snum */ 322459afb1SQianyu Gong qe_snum_state_e state; /* state */ 332459afb1SQianyu Gong } qe_snum_t; 342459afb1SQianyu Gong 352459afb1SQianyu Gong /* QE RISC allocation 362459afb1SQianyu Gong */ 372459afb1SQianyu Gong #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */ 382459afb1SQianyu Gong #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */ 392459afb1SQianyu Gong #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */ 402459afb1SQianyu Gong #define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */ 412459afb1SQianyu Gong #define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \ 422459afb1SQianyu Gong QE_RISC_ALLOCATION_RISC2) 432459afb1SQianyu Gong #define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \ 442459afb1SQianyu Gong QE_RISC_ALLOCATION_RISC2 | \ 452459afb1SQianyu Gong QE_RISC_ALLOCATION_RISC3 | \ 462459afb1SQianyu Gong QE_RISC_ALLOCATION_RISC4) 472459afb1SQianyu Gong 482459afb1SQianyu Gong /* QE CECR commands for UCC fast. 492459afb1SQianyu Gong */ 502459afb1SQianyu Gong #define QE_CR_FLG 0x00010000 512459afb1SQianyu Gong #define QE_RESET 0x80000000 522459afb1SQianyu Gong #define QE_INIT_TX_RX 0x00000000 532459afb1SQianyu Gong #define QE_INIT_RX 0x00000001 542459afb1SQianyu Gong #define QE_INIT_TX 0x00000002 552459afb1SQianyu Gong #define QE_ENTER_HUNT_MODE 0x00000003 562459afb1SQianyu Gong #define QE_STOP_TX 0x00000004 572459afb1SQianyu Gong #define QE_GRACEFUL_STOP_TX 0x00000005 582459afb1SQianyu Gong #define QE_RESTART_TX 0x00000006 592459afb1SQianyu Gong #define QE_SWITCH_COMMAND 0x00000007 602459afb1SQianyu Gong #define QE_SET_GROUP_ADDRESS 0x00000008 612459afb1SQianyu Gong #define QE_INSERT_CELL 0x00000009 622459afb1SQianyu Gong #define QE_ATM_TRANSMIT 0x0000000a 632459afb1SQianyu Gong #define QE_CELL_POOL_GET 0x0000000b 642459afb1SQianyu Gong #define QE_CELL_POOL_PUT 0x0000000c 652459afb1SQianyu Gong #define QE_IMA_HOST_CMD 0x0000000d 662459afb1SQianyu Gong #define QE_ATM_MULTI_THREAD_INIT 0x00000011 672459afb1SQianyu Gong #define QE_ASSIGN_PAGE 0x00000012 682459afb1SQianyu Gong #define QE_START_FLOW_CONTROL 0x00000014 692459afb1SQianyu Gong #define QE_STOP_FLOW_CONTROL 0x00000015 702459afb1SQianyu Gong #define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016 712459afb1SQianyu Gong #define QE_GRACEFUL_STOP_RX 0x0000001a 722459afb1SQianyu Gong #define QE_RESTART_RX 0x0000001b 732459afb1SQianyu Gong 742459afb1SQianyu Gong /* QE CECR Sub Block Code - sub block code of QE command. 752459afb1SQianyu Gong */ 762459afb1SQianyu Gong #define QE_CR_SUBBLOCK_INVALID 0x00000000 772459afb1SQianyu Gong #define QE_CR_SUBBLOCK_USB 0x03200000 782459afb1SQianyu Gong #define QE_CR_SUBBLOCK_UCCFAST1 0x02000000 792459afb1SQianyu Gong #define QE_CR_SUBBLOCK_UCCFAST2 0x02200000 802459afb1SQianyu Gong #define QE_CR_SUBBLOCK_UCCFAST3 0x02400000 812459afb1SQianyu Gong #define QE_CR_SUBBLOCK_UCCFAST4 0x02600000 822459afb1SQianyu Gong #define QE_CR_SUBBLOCK_UCCFAST5 0x02800000 832459afb1SQianyu Gong #define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000 842459afb1SQianyu Gong #define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000 852459afb1SQianyu Gong #define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000 862459afb1SQianyu Gong #define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000 872459afb1SQianyu Gong #define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000 882459afb1SQianyu Gong #define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000 892459afb1SQianyu Gong #define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000 902459afb1SQianyu Gong #define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000 912459afb1SQianyu Gong #define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000 922459afb1SQianyu Gong #define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000 932459afb1SQianyu Gong #define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000 942459afb1SQianyu Gong #define QE_CR_SUBBLOCK_MCC1 0x03800000 952459afb1SQianyu Gong #define QE_CR_SUBBLOCK_MCC2 0x03a00000 962459afb1SQianyu Gong #define QE_CR_SUBBLOCK_MCC3 0x03000000 972459afb1SQianyu Gong #define QE_CR_SUBBLOCK_IDMA1 0x02800000 982459afb1SQianyu Gong #define QE_CR_SUBBLOCK_IDMA2 0x02a00000 992459afb1SQianyu Gong #define QE_CR_SUBBLOCK_IDMA3 0x02c00000 1002459afb1SQianyu Gong #define QE_CR_SUBBLOCK_IDMA4 0x02e00000 1012459afb1SQianyu Gong #define QE_CR_SUBBLOCK_HPAC 0x01e00000 1022459afb1SQianyu Gong #define QE_CR_SUBBLOCK_SPI1 0x01400000 1032459afb1SQianyu Gong #define QE_CR_SUBBLOCK_SPI2 0x01600000 1042459afb1SQianyu Gong #define QE_CR_SUBBLOCK_RAND 0x01c00000 1052459afb1SQianyu Gong #define QE_CR_SUBBLOCK_TIMER 0x01e00000 1062459afb1SQianyu Gong #define QE_CR_SUBBLOCK_GENERAL 0x03c00000 1072459afb1SQianyu Gong 1082459afb1SQianyu Gong /* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command. 1092459afb1SQianyu Gong */ 1102459afb1SQianyu Gong #define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */ 1112459afb1SQianyu Gong #define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00 1122459afb1SQianyu Gong #define QE_CR_PROTOCOL_ATM_POS 0x0A 1132459afb1SQianyu Gong #define QE_CR_PROTOCOL_ETHERNET 0x0C 1142459afb1SQianyu Gong #define QE_CR_PROTOCOL_L2_SWITCH 0x0D 1152459afb1SQianyu Gong #define QE_CR_PROTOCOL_SHIFT 6 1162459afb1SQianyu Gong 1172459afb1SQianyu Gong /* QE ASSIGN PAGE command 1182459afb1SQianyu Gong */ 1192459afb1SQianyu Gong #define QE_CR_ASSIGN_PAGE_SNUM_SHIFT 17 1202459afb1SQianyu Gong 1212459afb1SQianyu Gong /* Communication Direction. 1222459afb1SQianyu Gong */ 1232459afb1SQianyu Gong typedef enum comm_dir { 1242459afb1SQianyu Gong COMM_DIR_NONE = 0, 1252459afb1SQianyu Gong COMM_DIR_RX = 1, 1262459afb1SQianyu Gong COMM_DIR_TX = 2, 1272459afb1SQianyu Gong COMM_DIR_RX_AND_TX = 3 1282459afb1SQianyu Gong } comm_dir_e; 1292459afb1SQianyu Gong 1302459afb1SQianyu Gong /* Clocks and BRG's 1312459afb1SQianyu Gong */ 1322459afb1SQianyu Gong typedef enum qe_clock { 1332459afb1SQianyu Gong QE_CLK_NONE = 0, 1342459afb1SQianyu Gong QE_BRG1, /* Baud Rate Generator 1 */ 1352459afb1SQianyu Gong QE_BRG2, /* Baud Rate Generator 2 */ 1362459afb1SQianyu Gong QE_BRG3, /* Baud Rate Generator 3 */ 1372459afb1SQianyu Gong QE_BRG4, /* Baud Rate Generator 4 */ 1382459afb1SQianyu Gong QE_BRG5, /* Baud Rate Generator 5 */ 1392459afb1SQianyu Gong QE_BRG6, /* Baud Rate Generator 6 */ 1402459afb1SQianyu Gong QE_BRG7, /* Baud Rate Generator 7 */ 1412459afb1SQianyu Gong QE_BRG8, /* Baud Rate Generator 8 */ 1422459afb1SQianyu Gong QE_BRG9, /* Baud Rate Generator 9 */ 1432459afb1SQianyu Gong QE_BRG10, /* Baud Rate Generator 10 */ 1442459afb1SQianyu Gong QE_BRG11, /* Baud Rate Generator 11 */ 1452459afb1SQianyu Gong QE_BRG12, /* Baud Rate Generator 12 */ 1462459afb1SQianyu Gong QE_BRG13, /* Baud Rate Generator 13 */ 1472459afb1SQianyu Gong QE_BRG14, /* Baud Rate Generator 14 */ 1482459afb1SQianyu Gong QE_BRG15, /* Baud Rate Generator 15 */ 1492459afb1SQianyu Gong QE_BRG16, /* Baud Rate Generator 16 */ 1502459afb1SQianyu Gong QE_CLK1, /* Clock 1 */ 1512459afb1SQianyu Gong QE_CLK2, /* Clock 2 */ 1522459afb1SQianyu Gong QE_CLK3, /* Clock 3 */ 1532459afb1SQianyu Gong QE_CLK4, /* Clock 4 */ 1542459afb1SQianyu Gong QE_CLK5, /* Clock 5 */ 1552459afb1SQianyu Gong QE_CLK6, /* Clock 6 */ 1562459afb1SQianyu Gong QE_CLK7, /* Clock 7 */ 1572459afb1SQianyu Gong QE_CLK8, /* Clock 8 */ 1582459afb1SQianyu Gong QE_CLK9, /* Clock 9 */ 1592459afb1SQianyu Gong QE_CLK10, /* Clock 10 */ 1602459afb1SQianyu Gong QE_CLK11, /* Clock 11 */ 1612459afb1SQianyu Gong QE_CLK12, /* Clock 12 */ 1622459afb1SQianyu Gong QE_CLK13, /* Clock 13 */ 1632459afb1SQianyu Gong QE_CLK14, /* Clock 14 */ 1642459afb1SQianyu Gong QE_CLK15, /* Clock 15 */ 1652459afb1SQianyu Gong QE_CLK16, /* Clock 16 */ 1662459afb1SQianyu Gong QE_CLK17, /* Clock 17 */ 1672459afb1SQianyu Gong QE_CLK18, /* Clock 18 */ 1682459afb1SQianyu Gong QE_CLK19, /* Clock 19 */ 1692459afb1SQianyu Gong QE_CLK20, /* Clock 20 */ 1702459afb1SQianyu Gong QE_CLK21, /* Clock 21 */ 1712459afb1SQianyu Gong QE_CLK22, /* Clock 22 */ 1722459afb1SQianyu Gong QE_CLK23, /* Clock 23 */ 1732459afb1SQianyu Gong QE_CLK24, /* Clock 24 */ 1742459afb1SQianyu Gong QE_CLK_DUMMY 1752459afb1SQianyu Gong } qe_clock_e; 1762459afb1SQianyu Gong 1772459afb1SQianyu Gong /* QE CMXGCR register 1782459afb1SQianyu Gong */ 1792459afb1SQianyu Gong #define QE_CMXGCR_MII_ENET_MNG_MASK 0x00007000 1802459afb1SQianyu Gong #define QE_CMXGCR_MII_ENET_MNG_SHIFT 12 1812459afb1SQianyu Gong 1822459afb1SQianyu Gong /* QE CMXUCR registers 1832459afb1SQianyu Gong */ 1842459afb1SQianyu Gong #define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F 1852459afb1SQianyu Gong 1862459afb1SQianyu Gong /* QE BRG configuration register 1872459afb1SQianyu Gong */ 1882459afb1SQianyu Gong #define QE_BRGC_ENABLE 0x00010000 1892459afb1SQianyu Gong #define QE_BRGC_DIVISOR_SHIFT 1 1902459afb1SQianyu Gong #define QE_BRGC_DIVISOR_MAX 0xFFF 1912459afb1SQianyu Gong #define QE_BRGC_DIV16 1 1922459afb1SQianyu Gong 1932459afb1SQianyu Gong /* QE SDMA registers 1942459afb1SQianyu Gong */ 1952459afb1SQianyu Gong #define QE_SDSR_BER1 0x02000000 1962459afb1SQianyu Gong #define QE_SDSR_BER2 0x01000000 1972459afb1SQianyu Gong 1982459afb1SQianyu Gong #define QE_SDMR_GLB_1_MSK 0x80000000 1992459afb1SQianyu Gong #define QE_SDMR_ADR_SEL 0x20000000 2002459afb1SQianyu Gong #define QE_SDMR_BER1_MSK 0x02000000 2012459afb1SQianyu Gong #define QE_SDMR_BER2_MSK 0x01000000 2022459afb1SQianyu Gong #define QE_SDMR_EB1_MSK 0x00800000 2032459afb1SQianyu Gong #define QE_SDMR_ER1_MSK 0x00080000 2042459afb1SQianyu Gong #define QE_SDMR_ER2_MSK 0x00040000 2052459afb1SQianyu Gong #define QE_SDMR_CEN_MASK 0x0000E000 2062459afb1SQianyu Gong #define QE_SDMR_SBER_1 0x00000200 2072459afb1SQianyu Gong #define QE_SDMR_SBER_2 0x00000200 2082459afb1SQianyu Gong #define QE_SDMR_EB1_PR_MASK 0x000000C0 2092459afb1SQianyu Gong #define QE_SDMR_ER1_PR 0x00000008 2102459afb1SQianyu Gong 2112459afb1SQianyu Gong #define QE_SDMR_CEN_SHIFT 13 2122459afb1SQianyu Gong #define QE_SDMR_EB1_PR_SHIFT 6 2132459afb1SQianyu Gong 2142459afb1SQianyu Gong #define QE_SDTM_MSNUM_SHIFT 24 2152459afb1SQianyu Gong 2162459afb1SQianyu Gong #define QE_SDEBCR_BA_MASK 0x01FFFFFF 2172459afb1SQianyu Gong 2182459afb1SQianyu Gong /* Communication Processor */ 2192459afb1SQianyu Gong #define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */ 2202459afb1SQianyu Gong #define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */ 2212459afb1SQianyu Gong #define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */ 2222459afb1SQianyu Gong 2232459afb1SQianyu Gong /* I-RAM */ 2242459afb1SQianyu Gong #define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */ 2252459afb1SQianyu Gong #define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */ 2262459afb1SQianyu Gong #define QE_IRAM_READY 0x80000000 2272459afb1SQianyu Gong 2282459afb1SQianyu Gong /* Structure that defines QE firmware binary files. 2292459afb1SQianyu Gong * 2302459afb1SQianyu Gong * See doc/README.qe_firmware for a description of these fields. 2312459afb1SQianyu Gong */ 2322459afb1SQianyu Gong struct qe_firmware { 2332459afb1SQianyu Gong struct qe_header { 2342459afb1SQianyu Gong u32 length; /* Length of the entire structure, in bytes */ 2352459afb1SQianyu Gong u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */ 2362459afb1SQianyu Gong u8 version; /* Version of this layout. First ver is '1' */ 2372459afb1SQianyu Gong } header; 2382459afb1SQianyu Gong u8 id[62]; /* Null-terminated identifier string */ 2392459afb1SQianyu Gong u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */ 2402459afb1SQianyu Gong u8 count; /* Number of microcode[] structures */ 2412459afb1SQianyu Gong struct { 2422459afb1SQianyu Gong u16 model; /* The SOC model */ 2432459afb1SQianyu Gong u8 major; /* The SOC revision major */ 2442459afb1SQianyu Gong u8 minor; /* The SOC revision minor */ 2452459afb1SQianyu Gong } __attribute__ ((packed)) soc; 2462459afb1SQianyu Gong u8 padding[4]; /* Reserved, for alignment */ 2472459afb1SQianyu Gong u64 extended_modes; /* Extended modes */ 2482459afb1SQianyu Gong u32 vtraps[8]; /* Virtual trap addresses */ 2492459afb1SQianyu Gong u8 reserved[4]; /* Reserved, for future expansion */ 2502459afb1SQianyu Gong struct qe_microcode { 2512459afb1SQianyu Gong u8 id[32]; /* Null-terminated identifier */ 2522459afb1SQianyu Gong u32 traps[16]; /* Trap addresses, 0 == ignore */ 2532459afb1SQianyu Gong u32 eccr; /* The value for the ECCR register */ 2542459afb1SQianyu Gong u32 iram_offset;/* Offset into I-RAM for the code */ 2552459afb1SQianyu Gong u32 count; /* Number of 32-bit words of the code */ 2562459afb1SQianyu Gong u32 code_offset;/* Offset of the actual microcode */ 2572459afb1SQianyu Gong u8 major; /* The microcode version major */ 2582459afb1SQianyu Gong u8 minor; /* The microcode version minor */ 2592459afb1SQianyu Gong u8 revision; /* The microcode version revision */ 2602459afb1SQianyu Gong u8 padding; /* Reserved, for alignment */ 2612459afb1SQianyu Gong u8 reserved[4]; /* Reserved, for future expansion */ 2622459afb1SQianyu Gong } __attribute__ ((packed)) microcode[1]; 2632459afb1SQianyu Gong /* All microcode binaries should be located here */ 2642459afb1SQianyu Gong /* CRC32 should be located here, after the microcode binaries */ 2652459afb1SQianyu Gong } __attribute__ ((packed)); 2662459afb1SQianyu Gong 2672459afb1SQianyu Gong struct qe_firmware_info { 2682459afb1SQianyu Gong char id[64]; /* Firmware name */ 2692459afb1SQianyu Gong u32 vtraps[8]; /* Virtual trap addresses */ 2702459afb1SQianyu Gong u64 extended_modes; /* Extended modes */ 2712459afb1SQianyu Gong }; 2722459afb1SQianyu Gong 2732459afb1SQianyu Gong void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign); 2742459afb1SQianyu Gong void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data); 2752459afb1SQianyu Gong uint qe_muram_alloc(uint size, uint align); 2762459afb1SQianyu Gong void *qe_muram_addr(uint offset); 2772459afb1SQianyu Gong int qe_get_snum(void); 2782459afb1SQianyu Gong void qe_put_snum(u8 snum); 2792459afb1SQianyu Gong void qe_init(uint qe_base); 2802459afb1SQianyu Gong void qe_reset(void); 2812459afb1SQianyu Gong void qe_assign_page(uint snum, uint para_ram_base); 2822459afb1SQianyu Gong int qe_set_brg(uint brg, uint rate); 2832459afb1SQianyu Gong int qe_set_mii_clk_src(int ucc_num); 2842459afb1SQianyu Gong int qe_upload_firmware(const struct qe_firmware *firmware); 2852459afb1SQianyu Gong struct qe_firmware_info *qe_get_firmware_info(void); 2862459afb1SQianyu Gong void ft_qe_setup(void *blob); 2872459afb1SQianyu Gong void qe_init(uint qe_base); 2882459afb1SQianyu Gong void qe_reset(void); 2892459afb1SQianyu Gong 2902459afb1SQianyu Gong #ifdef CONFIG_U_QE 2912459afb1SQianyu Gong void u_qe_init(void); 2922459afb1SQianyu Gong int u_qe_upload_firmware(const struct qe_firmware *firmware); 2932459afb1SQianyu Gong void u_qe_resume(void); 2942459afb1SQianyu Gong int u_qe_firmware_resume(const struct qe_firmware *firmware, 2952459afb1SQianyu Gong qe_map_t *qe_immrr); 2962459afb1SQianyu Gong #endif 2972459afb1SQianyu Gong 2982459afb1SQianyu Gong #endif /* __QE_H__ */ 299