21  * This is our record of the current clock rate of each clock. We don't
237  * Given the parent's rate and the required rate for the children, this works
241  * @param parent_rate	clock rate of parent clock in Hz
242  * @param rate		required clock rate for this clock
246 			   unsigned long rate)  in clk_get_divider()  argument
251 	divider += rate - 1;  in clk_get_divider()
252 	do_div(divider, rate);  in clk_get_divider()
263 int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)  in clock_set_pllout()  argument
274 	div = clk_get_divider(8, pll_rate[clkid], rate);  in clock_set_pllout()
292  * Given the parent's rate and the divider in 7.1 format, this works out the
293  * resulting peripheral clock rate.
295  * @param parent_rate	clock rate of parent clock in Hz
297  * @return effective clock rate of peripheral
302 	u64 rate;  in get_rate_from_divider()  local
304 	rate = (u64)parent_rate * 2;  in get_rate_from_divider()
305 	do_div(rate, divider + 2);  in get_rate_from_divider()
306 	return rate;  in get_rate_from_divider()
356  * Find the best available 7.1 format divisor given a parent clock rate and
357  * required child clock rate. This function assumes that a second-stage
361  * @param parent_rate	clock rate of parent clock in Hz
362  * @param rate		required clock rate for this clock
369 				unsigned long rate, int *extra_div)  in find_best_divider()  argument
373 	int best_error = rate;  in find_best_divider()
379 						rate);  in find_best_divider()
382 		int error = rate - effective_rate;  in find_best_divider()
440 		enum clock_id parent, unsigned rate, int *extra_div)  in clock_adjust_periph_pll_div()  argument
452 				    rate, &xdiv);  in clock_adjust_periph_pll_div()
459 	debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,  in clock_adjust_periph_pll_div()
467 	if (rate != effective_rate)  in clock_adjust_periph_pll_div()
468 		debug("Requested clock rate %u not honored (got %u)\n",  in clock_adjust_periph_pll_div()
469 			rate, effective_rate);  in clock_adjust_periph_pll_div()
474 		enum clock_id parent, unsigned rate)  in clock_start_periph_pll()  argument
481 	effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,  in clock_start_periph_pll()
536 	u64 parent_rate, rate;  in clock_get_rate()  local
551 	rate = parent_rate * ((base >> pllinfo->n_shift) & pllinfo->n_mask);  in clock_get_rate()
567 	do_div(rate, divm);  in clock_get_rate()
568 	return rate;  in clock_get_rate()
750 	 * to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to  in tegra30_set_up_pllp()