23 /* STM32 H7 maximum analog clock rate (from datasheet) */
62 	unsigned long rate;  in stm32h7_adc_clk_sel()  local
79 		 * From spec: PLL output musn't exceed max rate  in stm32h7_adc_clk_sel()
81 		rate = clk_get_rate(&common->aclk);  in stm32h7_adc_clk_sel()
82 		if (!rate) {  in stm32h7_adc_clk_sel()
83 			dev_err(dev, "Invalid aclk rate: 0\n");  in stm32h7_adc_clk_sel()
95 			if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE)  in stm32h7_adc_clk_sel()
101 	rate = clk_get_rate(&common->bclk);  in stm32h7_adc_clk_sel()
102 	if (!rate) {  in stm32h7_adc_clk_sel()
103 		dev_err(dev, "Invalid bus clock rate: 0\n");  in stm32h7_adc_clk_sel()
115 		if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE)  in stm32h7_adc_clk_sel()
123 	/* rate used later by each ADC instance to control BOOST mode */  in stm32h7_adc_clk_sel()
124 	common->rate = rate / div;  in stm32h7_adc_clk_sel()
133 		ckmode ? "bus" : "adc", div, common->rate / 1000);  in stm32h7_adc_clk_sel()