1c0fc1e21SBeniamino Galvani // SPDX-License-Identifier: GPL-2.0+
2c0fc1e21SBeniamino Galvani /*
3c0fc1e21SBeniamino Galvani * (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
4c0fc1e21SBeniamino Galvani * (C) Copyright 2018 - BayLibre, SAS
5c0fc1e21SBeniamino Galvani * Author: Neil Armstrong <narmstrong@baylibre.com>
6c0fc1e21SBeniamino Galvani */
7c0fc1e21SBeniamino Galvani
8c0fc1e21SBeniamino Galvani #include <common.h>
933e33780SJerome Brunet #include <asm/arch/clock-gx.h>
10c0fc1e21SBeniamino Galvani #include <asm/io.h>
11c0fc1e21SBeniamino Galvani #include <clk-uclass.h>
12c0fc1e21SBeniamino Galvani #include <div64.h>
13c0fc1e21SBeniamino Galvani #include <dm.h>
14*8973d816SLoic Devulder #include <regmap.h>
15*8973d816SLoic Devulder #include <syscon.h>
16c0fc1e21SBeniamino Galvani #include <dt-bindings/clock/gxbb-clkc.h>
17c0fc1e21SBeniamino Galvani #include "clk_meson.h"
18c0fc1e21SBeniamino Galvani
19c8e57016SNeil Armstrong /* This driver support only basic clock tree operations :
20c8e57016SNeil Armstrong * - Can calculate clock frequency on a limited tree
21c8e57016SNeil Armstrong * - Can Read muxes and basic dividers (0-based only)
22c8e57016SNeil Armstrong * - Can enable/disable gates with limited propagation
23c8e57016SNeil Armstrong * - Can reparent without propagation, only on muxes
24c8e57016SNeil Armstrong * - Can set rates without reparenting
25c8e57016SNeil Armstrong * This driver is adapted to what is actually supported by U-Boot
26c8e57016SNeil Armstrong */
27c8e57016SNeil Armstrong
28c8e57016SNeil Armstrong /* Only the clocks ids we don't want to expose, such as the internal muxes
29c8e57016SNeil Armstrong * and dividers of composite clocks, will remain defined here.
30c8e57016SNeil Armstrong */
31c8e57016SNeil Armstrong #define CLKID_MPEG_SEL 10
32c8e57016SNeil Armstrong #define CLKID_MPEG_DIV 11
33c8e57016SNeil Armstrong #define CLKID_SAR_ADC_DIV 99
34c8e57016SNeil Armstrong #define CLKID_MALI_0_DIV 101
35c8e57016SNeil Armstrong #define CLKID_MALI_1_DIV 104
36c8e57016SNeil Armstrong #define CLKID_CTS_AMCLK_SEL 108
37c8e57016SNeil Armstrong #define CLKID_CTS_AMCLK_DIV 109
38c8e57016SNeil Armstrong #define CLKID_CTS_MCLK_I958_SEL 111
39c8e57016SNeil Armstrong #define CLKID_CTS_MCLK_I958_DIV 112
40c8e57016SNeil Armstrong #define CLKID_32K_CLK_SEL 115
41c8e57016SNeil Armstrong #define CLKID_32K_CLK_DIV 116
42c8e57016SNeil Armstrong #define CLKID_SD_EMMC_A_CLK0_SEL 117
43c8e57016SNeil Armstrong #define CLKID_SD_EMMC_A_CLK0_DIV 118
44c8e57016SNeil Armstrong #define CLKID_SD_EMMC_B_CLK0_SEL 120
45c8e57016SNeil Armstrong #define CLKID_SD_EMMC_B_CLK0_DIV 121
46c8e57016SNeil Armstrong #define CLKID_SD_EMMC_C_CLK0_SEL 123
47c8e57016SNeil Armstrong #define CLKID_SD_EMMC_C_CLK0_DIV 124
48c8e57016SNeil Armstrong #define CLKID_VPU_0_DIV 127
49c8e57016SNeil Armstrong #define CLKID_VPU_1_DIV 130
50c8e57016SNeil Armstrong #define CLKID_VAPB_0_DIV 134
51c8e57016SNeil Armstrong #define CLKID_VAPB_1_DIV 137
52c8e57016SNeil Armstrong #define CLKID_HDMI_PLL_PRE_MULT 141
53c8e57016SNeil Armstrong #define CLKID_MPLL0_DIV 142
54c8e57016SNeil Armstrong #define CLKID_MPLL1_DIV 143
55c8e57016SNeil Armstrong #define CLKID_MPLL2_DIV 144
56c8e57016SNeil Armstrong #define CLKID_MPLL_PREDIV 145
57c8e57016SNeil Armstrong #define CLKID_FCLK_DIV2_DIV 146
58c8e57016SNeil Armstrong #define CLKID_FCLK_DIV3_DIV 147
59c8e57016SNeil Armstrong #define CLKID_FCLK_DIV4_DIV 148
60c8e57016SNeil Armstrong #define CLKID_FCLK_DIV5_DIV 149
61c8e57016SNeil Armstrong #define CLKID_FCLK_DIV7_DIV 150
62c8e57016SNeil Armstrong #define CLKID_VDEC_1_SEL 151
63c8e57016SNeil Armstrong #define CLKID_VDEC_1_DIV 152
64c8e57016SNeil Armstrong #define CLKID_VDEC_HEVC_SEL 154
65c8e57016SNeil Armstrong #define CLKID_VDEC_HEVC_DIV 155
66c8e57016SNeil Armstrong
67c0fc1e21SBeniamino Galvani #define XTAL_RATE 24000000
68c0fc1e21SBeniamino Galvani
69c0fc1e21SBeniamino Galvani struct meson_clk {
70*8973d816SLoic Devulder struct regmap *map;
71c0fc1e21SBeniamino Galvani };
72c0fc1e21SBeniamino Galvani
73c8e57016SNeil Armstrong static ulong meson_div_get_rate(struct clk *clk, unsigned long id);
74c8e57016SNeil Armstrong static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
75c8e57016SNeil Armstrong ulong current_rate);
76c8e57016SNeil Armstrong static ulong meson_mux_set_parent(struct clk *clk, unsigned long id,
77c8e57016SNeil Armstrong unsigned long parent_id);
78c8e57016SNeil Armstrong static ulong meson_mux_get_rate(struct clk *clk, unsigned long id);
79c8e57016SNeil Armstrong static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
80c8e57016SNeil Armstrong ulong rate, ulong current_rate);
81c8e57016SNeil Armstrong static ulong meson_mux_get_parent(struct clk *clk, unsigned long id);
82c0fc1e21SBeniamino Galvani static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id);
83c0fc1e21SBeniamino Galvani
8419987c39SNeil Armstrong static struct meson_gate gates[] = {
85c0fc1e21SBeniamino Galvani /* Everything Else (EE) domain gates */
86c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_DDR, HHI_GCLK_MPEG0, 0),
87c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_DOS, HHI_GCLK_MPEG0, 1),
88c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_ISA, HHI_GCLK_MPEG0, 5),
89c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_PL301, HHI_GCLK_MPEG0, 6),
90c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_PERIPHS, HHI_GCLK_MPEG0, 7),
91c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_SPICC, HHI_GCLK_MPEG0, 8),
92c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_I2C, HHI_GCLK_MPEG0, 9),
93c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_SAR_ADC, HHI_GCLK_MPEG0, 10),
94c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_SMART_CARD, HHI_GCLK_MPEG0, 11),
95c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_RNG0, HHI_GCLK_MPEG0, 12),
96c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_UART0, HHI_GCLK_MPEG0, 13),
97c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_SDHC, HHI_GCLK_MPEG0, 14),
98c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_STREAM, HHI_GCLK_MPEG0, 15),
99c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_ASYNC_FIFO, HHI_GCLK_MPEG0, 16),
100c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_SDIO, HHI_GCLK_MPEG0, 17),
101c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_ABUF, HHI_GCLK_MPEG0, 18),
102c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_HIU_IFACE, HHI_GCLK_MPEG0, 19),
103c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_ASSIST_MISC, HHI_GCLK_MPEG0, 23),
104c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_SD_EMMC_A, HHI_GCLK_MPEG0, 24),
105c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_SD_EMMC_B, HHI_GCLK_MPEG0, 25),
106c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26),
107c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_SPI, HHI_GCLK_MPEG0, 30),
108c0fc1e21SBeniamino Galvani
109c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_I2S_SPDIF, HHI_GCLK_MPEG1, 2),
110c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_ETH, HHI_GCLK_MPEG1, 3),
111c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_DEMUX, HHI_GCLK_MPEG1, 4),
112c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_AIU_GLUE, HHI_GCLK_MPEG1, 6),
113c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_IEC958, HHI_GCLK_MPEG1, 7),
114c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_I2S_OUT, HHI_GCLK_MPEG1, 8),
115c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_AMCLK, HHI_GCLK_MPEG1, 9),
116c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_AIFIFO2, HHI_GCLK_MPEG1, 10),
117c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_MIXER, HHI_GCLK_MPEG1, 11),
118c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_MIXER_IFACE, HHI_GCLK_MPEG1, 12),
119c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_ADC, HHI_GCLK_MPEG1, 13),
120c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_BLKMV, HHI_GCLK_MPEG1, 14),
121c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_AIU, HHI_GCLK_MPEG1, 15),
122c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_UART1, HHI_GCLK_MPEG1, 16),
123c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_G2D, HHI_GCLK_MPEG1, 20),
124c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_USB0, HHI_GCLK_MPEG1, 21),
125c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_USB1, HHI_GCLK_MPEG1, 22),
126c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_RESET, HHI_GCLK_MPEG1, 23),
127c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_NAND, HHI_GCLK_MPEG1, 24),
128c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_DOS_PARSER, HHI_GCLK_MPEG1, 25),
129c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_USB, HHI_GCLK_MPEG1, 26),
130c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_VDIN1, HHI_GCLK_MPEG1, 28),
131c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_AHB_ARB0, HHI_GCLK_MPEG1, 29),
132c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_EFUSE, HHI_GCLK_MPEG1, 30),
133c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_BOOT_ROM, HHI_GCLK_MPEG1, 31),
134c0fc1e21SBeniamino Galvani
135c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_AHB_DATA_BUS, HHI_GCLK_MPEG2, 1),
136c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_AHB_CTRL_BUS, HHI_GCLK_MPEG2, 2),
137c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_HDMI_INTR_SYNC, HHI_GCLK_MPEG2, 3),
138c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_HDMI_PCLK, HHI_GCLK_MPEG2, 4),
139c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_USB1_DDR_BRIDGE, HHI_GCLK_MPEG2, 8),
140c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_USB0_DDR_BRIDGE, HHI_GCLK_MPEG2, 9),
141c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_MMC_PCLK, HHI_GCLK_MPEG2, 11),
142c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_DVIN, HHI_GCLK_MPEG2, 12),
143c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_UART2, HHI_GCLK_MPEG2, 15),
144c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_SANA, HHI_GCLK_MPEG2, 22),
145c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_VPU_INTR, HHI_GCLK_MPEG2, 25),
146c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_SEC_AHB_AHB3_BRIDGE, HHI_GCLK_MPEG2, 26),
147c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_CLK81_A53, HHI_GCLK_MPEG2, 29),
148c0fc1e21SBeniamino Galvani
149c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_VCLK2_VENCI0, HHI_GCLK_OTHER, 1),
150c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_VCLK2_VENCI1, HHI_GCLK_OTHER, 2),
151c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_VCLK2_VENCP0, HHI_GCLK_OTHER, 3),
152c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_VCLK2_VENCP1, HHI_GCLK_OTHER, 4),
153c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_GCLK_VENCI_INT0, HHI_GCLK_OTHER, 8),
154c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_DAC_CLK, HHI_GCLK_OTHER, 10),
155c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_AOCLK_GATE, HHI_GCLK_OTHER, 14),
156c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_IEC958_GATE, HHI_GCLK_OTHER, 16),
157c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_ENC480P, HHI_GCLK_OTHER, 20),
158c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_RNG1, HHI_GCLK_OTHER, 21),
159c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_GCLK_VENCI_INT1, HHI_GCLK_OTHER, 22),
160c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_VCLK2_VENCLMCC, HHI_GCLK_OTHER, 24),
161c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_VCLK2_VENCL, HHI_GCLK_OTHER, 25),
162c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_VCLK_OTHER, HHI_GCLK_OTHER, 26),
163c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_EDP, HHI_GCLK_OTHER, 31),
164c0fc1e21SBeniamino Galvani
165c0fc1e21SBeniamino Galvani /* Always On (AO) domain gates */
166c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_AO_MEDIA_CPU, HHI_GCLK_AO, 0),
167c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_AO_AHB_SRAM, HHI_GCLK_AO, 1),
168c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_AO_AHB_BUS, HHI_GCLK_AO, 2),
169c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_AO_IFACE, HHI_GCLK_AO, 3),
170c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_AO_I2C, HHI_GCLK_AO, 4),
171c0fc1e21SBeniamino Galvani
172c0fc1e21SBeniamino Galvani /* PLL Gates */
173c0fc1e21SBeniamino Galvani /* CLKID_FCLK_DIV2 is critical for the SCPI Processor */
174c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_FCLK_DIV3, HHI_MPLL_CNTL6, 28),
175c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_FCLK_DIV4, HHI_MPLL_CNTL6, 29),
176c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_FCLK_DIV5, HHI_MPLL_CNTL6, 30),
177c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_FCLK_DIV7, HHI_MPLL_CNTL6, 31),
178c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_MPLL0, HHI_MPLL_CNTL7, 14),
179c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_MPLL1, HHI_MPLL_CNTL8, 14),
180c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_MPLL2, HHI_MPLL_CNTL9, 14),
181c0fc1e21SBeniamino Galvani /* CLKID_CLK81 is critical for the system */
182c0fc1e21SBeniamino Galvani
183c0fc1e21SBeniamino Galvani /* Peripheral Gates */
184c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_SAR_ADC_CLK, HHI_SAR_CLK_CNTL, 8),
185c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_SD_EMMC_A_CLK0, HHI_SD_EMMC_CLK_CNTL, 7),
186c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_SD_EMMC_B_CLK0, HHI_SD_EMMC_CLK_CNTL, 23),
187c0fc1e21SBeniamino Galvani MESON_GATE(CLKID_SD_EMMC_C_CLK0, HHI_NAND_CLK_CNTL, 7),
188c8e57016SNeil Armstrong MESON_GATE(CLKID_VPU_0, HHI_VPU_CLK_CNTL, 8),
189c8e57016SNeil Armstrong MESON_GATE(CLKID_VPU_1, HHI_VPU_CLK_CNTL, 24),
190c8e57016SNeil Armstrong MESON_GATE(CLKID_VAPB_0, HHI_VAPBCLK_CNTL, 8),
191c8e57016SNeil Armstrong MESON_GATE(CLKID_VAPB_1, HHI_VAPBCLK_CNTL, 24),
192c8e57016SNeil Armstrong MESON_GATE(CLKID_VAPB, HHI_VAPBCLK_CNTL, 30),
193c0fc1e21SBeniamino Galvani };
194c0fc1e21SBeniamino Galvani
meson_set_gate_by_id(struct clk * clk,unsigned long id,bool on)195c8e57016SNeil Armstrong static int meson_set_gate_by_id(struct clk *clk, unsigned long id, bool on)
196c0fc1e21SBeniamino Galvani {
197c0fc1e21SBeniamino Galvani struct meson_clk *priv = dev_get_priv(clk->dev);
198c0fc1e21SBeniamino Galvani struct meson_gate *gate;
199c0fc1e21SBeniamino Galvani
200c8e57016SNeil Armstrong debug("%s: %sabling %ld\n", __func__, on ? "en" : "dis", id);
201c8e57016SNeil Armstrong
202c8e57016SNeil Armstrong /* Propagate through muxes */
203c8e57016SNeil Armstrong switch (id) {
204c8e57016SNeil Armstrong case CLKID_VPU:
205c8e57016SNeil Armstrong return meson_set_gate_by_id(clk,
206c8e57016SNeil Armstrong meson_mux_get_parent(clk, CLKID_VPU), on);
207c8e57016SNeil Armstrong case CLKID_VAPB_SEL:
208c8e57016SNeil Armstrong return meson_set_gate_by_id(clk,
209c8e57016SNeil Armstrong meson_mux_get_parent(clk, CLKID_VAPB_SEL), on);
210c8e57016SNeil Armstrong }
211c8e57016SNeil Armstrong
212c8e57016SNeil Armstrong if (id >= ARRAY_SIZE(gates))
213c0fc1e21SBeniamino Galvani return -ENOENT;
214c0fc1e21SBeniamino Galvani
215c8e57016SNeil Armstrong gate = &gates[id];
216c0fc1e21SBeniamino Galvani
217c0fc1e21SBeniamino Galvani if (gate->reg == 0)
218c0fc1e21SBeniamino Galvani return 0;
219c0fc1e21SBeniamino Galvani
220c8e57016SNeil Armstrong debug("%s: really %sabling %ld\n", __func__, on ? "en" : "dis", id);
221c8e57016SNeil Armstrong
222*8973d816SLoic Devulder regmap_update_bits(priv->map, gate->reg,
223c0fc1e21SBeniamino Galvani BIT(gate->bit), on ? BIT(gate->bit) : 0);
224c8e57016SNeil Armstrong
225c8e57016SNeil Armstrong /* Propagate to next gate(s) */
226c8e57016SNeil Armstrong switch (id) {
227c8e57016SNeil Armstrong case CLKID_VAPB:
228c8e57016SNeil Armstrong return meson_set_gate_by_id(clk, CLKID_VAPB_SEL, on);
229c8e57016SNeil Armstrong }
230c8e57016SNeil Armstrong
231c0fc1e21SBeniamino Galvani return 0;
232c0fc1e21SBeniamino Galvani }
233c0fc1e21SBeniamino Galvani
meson_clk_enable(struct clk * clk)234c0fc1e21SBeniamino Galvani static int meson_clk_enable(struct clk *clk)
235c0fc1e21SBeniamino Galvani {
236c8e57016SNeil Armstrong return meson_set_gate_by_id(clk, clk->id, true);
237c0fc1e21SBeniamino Galvani }
238c0fc1e21SBeniamino Galvani
meson_clk_disable(struct clk * clk)239c0fc1e21SBeniamino Galvani static int meson_clk_disable(struct clk *clk)
240c0fc1e21SBeniamino Galvani {
241c8e57016SNeil Armstrong return meson_set_gate_by_id(clk, clk->id, false);
242c8e57016SNeil Armstrong }
243c8e57016SNeil Armstrong
244c8e57016SNeil Armstrong static struct parm meson_vpu_0_div_parm = {
245c8e57016SNeil Armstrong HHI_VPU_CLK_CNTL, 0, 7,
246c8e57016SNeil Armstrong };
247c8e57016SNeil Armstrong
248c8e57016SNeil Armstrong int meson_vpu_0_div_parent = CLKID_VPU_0_SEL;
249c8e57016SNeil Armstrong
250c8e57016SNeil Armstrong static struct parm meson_vpu_1_div_parm = {
251c8e57016SNeil Armstrong HHI_VPU_CLK_CNTL, 16, 7,
252c8e57016SNeil Armstrong };
253c8e57016SNeil Armstrong
254c8e57016SNeil Armstrong int meson_vpu_1_div_parent = CLKID_VPU_1_SEL;
255c8e57016SNeil Armstrong
256c8e57016SNeil Armstrong static struct parm meson_vapb_0_div_parm = {
257c8e57016SNeil Armstrong HHI_VAPBCLK_CNTL, 0, 7,
258c8e57016SNeil Armstrong };
259c8e57016SNeil Armstrong
260c8e57016SNeil Armstrong int meson_vapb_0_div_parent = CLKID_VAPB_0_SEL;
261c8e57016SNeil Armstrong
262c8e57016SNeil Armstrong static struct parm meson_vapb_1_div_parm = {
263c8e57016SNeil Armstrong HHI_VAPBCLK_CNTL, 16, 7,
264c8e57016SNeil Armstrong };
265c8e57016SNeil Armstrong
266c8e57016SNeil Armstrong int meson_vapb_1_div_parent = CLKID_VAPB_1_SEL;
267c8e57016SNeil Armstrong
meson_div_get_rate(struct clk * clk,unsigned long id)268c8e57016SNeil Armstrong static ulong meson_div_get_rate(struct clk *clk, unsigned long id)
269c8e57016SNeil Armstrong {
270c8e57016SNeil Armstrong struct meson_clk *priv = dev_get_priv(clk->dev);
271c8e57016SNeil Armstrong unsigned int rate, parent_rate;
272c8e57016SNeil Armstrong struct parm *parm;
273c8e57016SNeil Armstrong int parent;
274*8973d816SLoic Devulder uint reg;
275c8e57016SNeil Armstrong
276c8e57016SNeil Armstrong switch (id) {
277c8e57016SNeil Armstrong case CLKID_VPU_0_DIV:
278c8e57016SNeil Armstrong parm = &meson_vpu_0_div_parm;
279c8e57016SNeil Armstrong parent = meson_vpu_0_div_parent;
280c8e57016SNeil Armstrong break;
281c8e57016SNeil Armstrong case CLKID_VPU_1_DIV:
282c8e57016SNeil Armstrong parm = &meson_vpu_1_div_parm;
283c8e57016SNeil Armstrong parent = meson_vpu_1_div_parent;
284c8e57016SNeil Armstrong break;
285c8e57016SNeil Armstrong case CLKID_VAPB_0_DIV:
286c8e57016SNeil Armstrong parm = &meson_vapb_0_div_parm;
287c8e57016SNeil Armstrong parent = meson_vapb_0_div_parent;
288c8e57016SNeil Armstrong break;
289c8e57016SNeil Armstrong case CLKID_VAPB_1_DIV:
290c8e57016SNeil Armstrong parm = &meson_vapb_1_div_parm;
291c8e57016SNeil Armstrong parent = meson_vapb_1_div_parent;
292c8e57016SNeil Armstrong break;
293c8e57016SNeil Armstrong default:
294c8e57016SNeil Armstrong return -ENOENT;
295c8e57016SNeil Armstrong }
296c8e57016SNeil Armstrong
297*8973d816SLoic Devulder regmap_read(priv->map, parm->reg_off, ®);
298c8e57016SNeil Armstrong reg = PARM_GET(parm->width, parm->shift, reg);
299c8e57016SNeil Armstrong
300c8e57016SNeil Armstrong debug("%s: div of %ld is %d\n", __func__, id, reg + 1);
301c8e57016SNeil Armstrong
302c8e57016SNeil Armstrong parent_rate = meson_clk_get_rate_by_id(clk, parent);
303c8e57016SNeil Armstrong if (IS_ERR_VALUE(parent_rate))
304c8e57016SNeil Armstrong return parent_rate;
305c8e57016SNeil Armstrong
306c8e57016SNeil Armstrong debug("%s: parent rate of %ld is %d\n", __func__, id, parent_rate);
307c8e57016SNeil Armstrong
308c8e57016SNeil Armstrong rate = parent_rate / (reg + 1);
309c8e57016SNeil Armstrong
310c8e57016SNeil Armstrong debug("%s: rate of %ld is %d\n", __func__, id, rate);
311c8e57016SNeil Armstrong
312c8e57016SNeil Armstrong return rate;
313c8e57016SNeil Armstrong }
314c8e57016SNeil Armstrong
meson_div_set_rate(struct clk * clk,unsigned long id,ulong rate,ulong current_rate)315c8e57016SNeil Armstrong static ulong meson_div_set_rate(struct clk *clk, unsigned long id, ulong rate,
316c8e57016SNeil Armstrong ulong current_rate)
317c8e57016SNeil Armstrong {
318c8e57016SNeil Armstrong struct meson_clk *priv = dev_get_priv(clk->dev);
319c8e57016SNeil Armstrong unsigned int new_div = -EINVAL;
320c8e57016SNeil Armstrong unsigned long parent_rate;
321c8e57016SNeil Armstrong struct parm *parm;
322c8e57016SNeil Armstrong int parent;
323c8e57016SNeil Armstrong int ret;
324c8e57016SNeil Armstrong
325c8e57016SNeil Armstrong if (current_rate == rate)
326c8e57016SNeil Armstrong return 0;
327c8e57016SNeil Armstrong
328c8e57016SNeil Armstrong debug("%s: setting rate of %ld from %ld to %ld\n",
329c8e57016SNeil Armstrong __func__, id, current_rate, rate);
330c8e57016SNeil Armstrong
331c8e57016SNeil Armstrong switch (id) {
332c8e57016SNeil Armstrong case CLKID_VPU_0_DIV:
333c8e57016SNeil Armstrong parm = &meson_vpu_0_div_parm;
334c8e57016SNeil Armstrong parent = meson_vpu_0_div_parent;
335c8e57016SNeil Armstrong break;
336c8e57016SNeil Armstrong case CLKID_VPU_1_DIV:
337c8e57016SNeil Armstrong parm = &meson_vpu_1_div_parm;
338c8e57016SNeil Armstrong parent = meson_vpu_1_div_parent;
339c8e57016SNeil Armstrong break;
340c8e57016SNeil Armstrong case CLKID_VAPB_0_DIV:
341c8e57016SNeil Armstrong parm = &meson_vapb_0_div_parm;
342c8e57016SNeil Armstrong parent = meson_vapb_0_div_parent;
343c8e57016SNeil Armstrong break;
344c8e57016SNeil Armstrong case CLKID_VAPB_1_DIV:
345c8e57016SNeil Armstrong parm = &meson_vapb_1_div_parm;
346c8e57016SNeil Armstrong parent = meson_vapb_1_div_parent;
347c8e57016SNeil Armstrong break;
348c8e57016SNeil Armstrong default:
349c8e57016SNeil Armstrong return -ENOENT;
350c8e57016SNeil Armstrong }
351c8e57016SNeil Armstrong
352c8e57016SNeil Armstrong parent_rate = meson_clk_get_rate_by_id(clk, parent);
353c8e57016SNeil Armstrong if (IS_ERR_VALUE(parent_rate))
354c8e57016SNeil Armstrong return parent_rate;
355c8e57016SNeil Armstrong
356c8e57016SNeil Armstrong debug("%s: parent rate of %ld is %ld\n", __func__, id, parent_rate);
357c8e57016SNeil Armstrong
358c8e57016SNeil Armstrong /* If can't divide, set parent instead */
359c8e57016SNeil Armstrong if (!parent_rate || rate > parent_rate)
360c8e57016SNeil Armstrong return meson_clk_set_rate_by_id(clk, parent, rate,
361c8e57016SNeil Armstrong current_rate);
362c8e57016SNeil Armstrong
363c8e57016SNeil Armstrong new_div = DIV_ROUND_CLOSEST(parent_rate, rate);
364c8e57016SNeil Armstrong
365c8e57016SNeil Armstrong debug("%s: new div of %ld is %d\n", __func__, id, new_div);
366c8e57016SNeil Armstrong
367c8e57016SNeil Armstrong /* If overflow, try to set parent rate and retry */
368c8e57016SNeil Armstrong if (!new_div || new_div > (1 << parm->width)) {
369c8e57016SNeil Armstrong ret = meson_clk_set_rate_by_id(clk, parent, rate, current_rate);
370c8e57016SNeil Armstrong if (IS_ERR_VALUE(ret))
371c8e57016SNeil Armstrong return ret;
372c8e57016SNeil Armstrong
373c8e57016SNeil Armstrong parent_rate = meson_clk_get_rate_by_id(clk, parent);
374c8e57016SNeil Armstrong if (IS_ERR_VALUE(parent_rate))
375c8e57016SNeil Armstrong return parent_rate;
376c8e57016SNeil Armstrong
377c8e57016SNeil Armstrong new_div = DIV_ROUND_CLOSEST(parent_rate, rate);
378c8e57016SNeil Armstrong
379c8e57016SNeil Armstrong debug("%s: new new div of %ld is %d\n", __func__, id, new_div);
380c8e57016SNeil Armstrong
381c8e57016SNeil Armstrong if (!new_div || new_div > (1 << parm->width))
382c8e57016SNeil Armstrong return -EINVAL;
383c8e57016SNeil Armstrong }
384c8e57016SNeil Armstrong
385c8e57016SNeil Armstrong debug("%s: setting div of %ld to %d\n", __func__, id, new_div);
386c8e57016SNeil Armstrong
387*8973d816SLoic Devulder regmap_update_bits(priv->map, parm->reg_off, SETPMASK(parm->width, parm->shift),
388*8973d816SLoic Devulder (new_div - 1) << parm->shift);
389c8e57016SNeil Armstrong
390c8e57016SNeil Armstrong debug("%s: new rate of %ld is %ld\n",
391c8e57016SNeil Armstrong __func__, id, meson_div_get_rate(clk, id));
392c8e57016SNeil Armstrong
393c8e57016SNeil Armstrong return 0;
394c8e57016SNeil Armstrong }
395c8e57016SNeil Armstrong
396c8e57016SNeil Armstrong static struct parm meson_vpu_mux_parm = {
397c8e57016SNeil Armstrong HHI_VPU_CLK_CNTL, 31, 1,
398c8e57016SNeil Armstrong };
399c8e57016SNeil Armstrong
400c8e57016SNeil Armstrong int meson_vpu_mux_parents[] = {
401c8e57016SNeil Armstrong CLKID_VPU_0,
402c8e57016SNeil Armstrong CLKID_VPU_1,
403c8e57016SNeil Armstrong };
404c8e57016SNeil Armstrong
405c8e57016SNeil Armstrong static struct parm meson_vpu_0_mux_parm = {
406c8e57016SNeil Armstrong HHI_VPU_CLK_CNTL, 9, 2,
407c8e57016SNeil Armstrong };
408c8e57016SNeil Armstrong
409c8e57016SNeil Armstrong static struct parm meson_vpu_1_mux_parm = {
410c8e57016SNeil Armstrong HHI_VPU_CLK_CNTL, 25, 2,
411c8e57016SNeil Armstrong };
412c8e57016SNeil Armstrong
413c8e57016SNeil Armstrong static int meson_vpu_0_1_mux_parents[] = {
414c8e57016SNeil Armstrong CLKID_FCLK_DIV4,
415c8e57016SNeil Armstrong CLKID_FCLK_DIV3,
416c8e57016SNeil Armstrong CLKID_FCLK_DIV5,
417c8e57016SNeil Armstrong CLKID_FCLK_DIV7,
418c8e57016SNeil Armstrong };
419c8e57016SNeil Armstrong
420c8e57016SNeil Armstrong static struct parm meson_vapb_sel_mux_parm = {
421c8e57016SNeil Armstrong HHI_VAPBCLK_CNTL, 31, 1,
422c8e57016SNeil Armstrong };
423c8e57016SNeil Armstrong
424c8e57016SNeil Armstrong int meson_vapb_sel_mux_parents[] = {
425c8e57016SNeil Armstrong CLKID_VAPB_0,
426c8e57016SNeil Armstrong CLKID_VAPB_1,
427c8e57016SNeil Armstrong };
428c8e57016SNeil Armstrong
429c8e57016SNeil Armstrong static struct parm meson_vapb_0_mux_parm = {
430c8e57016SNeil Armstrong HHI_VAPBCLK_CNTL, 9, 2,
431c8e57016SNeil Armstrong };
432c8e57016SNeil Armstrong
433c8e57016SNeil Armstrong static struct parm meson_vapb_1_mux_parm = {
434c8e57016SNeil Armstrong HHI_VAPBCLK_CNTL, 25, 2,
435c8e57016SNeil Armstrong };
436c8e57016SNeil Armstrong
437c8e57016SNeil Armstrong static int meson_vapb_0_1_mux_parents[] = {
438c8e57016SNeil Armstrong CLKID_FCLK_DIV4,
439c8e57016SNeil Armstrong CLKID_FCLK_DIV3,
440c8e57016SNeil Armstrong CLKID_FCLK_DIV5,
441c8e57016SNeil Armstrong CLKID_FCLK_DIV7,
442c8e57016SNeil Armstrong };
443c8e57016SNeil Armstrong
meson_mux_get_parent(struct clk * clk,unsigned long id)444c8e57016SNeil Armstrong static ulong meson_mux_get_parent(struct clk *clk, unsigned long id)
445c8e57016SNeil Armstrong {
446c8e57016SNeil Armstrong struct meson_clk *priv = dev_get_priv(clk->dev);
447c8e57016SNeil Armstrong struct parm *parm;
448c8e57016SNeil Armstrong int *parents;
449*8973d816SLoic Devulder uint reg;
450c8e57016SNeil Armstrong
451c8e57016SNeil Armstrong switch (id) {
452c8e57016SNeil Armstrong case CLKID_VPU:
453c8e57016SNeil Armstrong parm = &meson_vpu_mux_parm;
454c8e57016SNeil Armstrong parents = meson_vpu_mux_parents;
455c8e57016SNeil Armstrong break;
456c8e57016SNeil Armstrong case CLKID_VPU_0_SEL:
457c8e57016SNeil Armstrong parm = &meson_vpu_0_mux_parm;
458c8e57016SNeil Armstrong parents = meson_vpu_0_1_mux_parents;
459c8e57016SNeil Armstrong break;
460c8e57016SNeil Armstrong case CLKID_VPU_1_SEL:
461c8e57016SNeil Armstrong parm = &meson_vpu_1_mux_parm;
462c8e57016SNeil Armstrong parents = meson_vpu_0_1_mux_parents;
463c8e57016SNeil Armstrong break;
464c8e57016SNeil Armstrong case CLKID_VAPB_SEL:
465c8e57016SNeil Armstrong parm = &meson_vapb_sel_mux_parm;
466c8e57016SNeil Armstrong parents = meson_vapb_sel_mux_parents;
467c8e57016SNeil Armstrong break;
468c8e57016SNeil Armstrong case CLKID_VAPB_0_SEL:
469c8e57016SNeil Armstrong parm = &meson_vapb_0_mux_parm;
470c8e57016SNeil Armstrong parents = meson_vapb_0_1_mux_parents;
471c8e57016SNeil Armstrong break;
472c8e57016SNeil Armstrong case CLKID_VAPB_1_SEL:
473c8e57016SNeil Armstrong parm = &meson_vapb_1_mux_parm;
474c8e57016SNeil Armstrong parents = meson_vapb_0_1_mux_parents;
475c8e57016SNeil Armstrong break;
476c8e57016SNeil Armstrong default:
477c8e57016SNeil Armstrong return -ENOENT;
478c8e57016SNeil Armstrong }
479c8e57016SNeil Armstrong
480*8973d816SLoic Devulder regmap_read(priv->map, parm->reg_off, ®);
481c8e57016SNeil Armstrong reg = PARM_GET(parm->width, parm->shift, reg);
482c8e57016SNeil Armstrong
483c8e57016SNeil Armstrong debug("%s: parent of %ld is %d (%d)\n",
484c8e57016SNeil Armstrong __func__, id, parents[reg], reg);
485c8e57016SNeil Armstrong
486c8e57016SNeil Armstrong return parents[reg];
487c8e57016SNeil Armstrong }
488c8e57016SNeil Armstrong
meson_mux_set_parent(struct clk * clk,unsigned long id,unsigned long parent_id)489c8e57016SNeil Armstrong static ulong meson_mux_set_parent(struct clk *clk, unsigned long id,
490c8e57016SNeil Armstrong unsigned long parent_id)
491c8e57016SNeil Armstrong {
492c8e57016SNeil Armstrong unsigned long cur_parent = meson_mux_get_parent(clk, id);
493c8e57016SNeil Armstrong struct meson_clk *priv = dev_get_priv(clk->dev);
494c8e57016SNeil Armstrong unsigned int new_index = -EINVAL;
495c8e57016SNeil Armstrong struct parm *parm;
496c8e57016SNeil Armstrong int *parents;
497c8e57016SNeil Armstrong int i;
498c8e57016SNeil Armstrong
499c8e57016SNeil Armstrong if (IS_ERR_VALUE(cur_parent))
500c8e57016SNeil Armstrong return cur_parent;
501c8e57016SNeil Armstrong
502c8e57016SNeil Armstrong debug("%s: setting parent of %ld from %ld to %ld\n",
503c8e57016SNeil Armstrong __func__, id, cur_parent, parent_id);
504c8e57016SNeil Armstrong
505c8e57016SNeil Armstrong if (cur_parent == parent_id)
506c8e57016SNeil Armstrong return 0;
507c8e57016SNeil Armstrong
508c8e57016SNeil Armstrong switch (id) {
509c8e57016SNeil Armstrong case CLKID_VPU:
510c8e57016SNeil Armstrong parm = &meson_vpu_mux_parm;
511c8e57016SNeil Armstrong parents = meson_vpu_mux_parents;
512c8e57016SNeil Armstrong break;
513c8e57016SNeil Armstrong case CLKID_VPU_0_SEL:
514c8e57016SNeil Armstrong parm = &meson_vpu_0_mux_parm;
515c8e57016SNeil Armstrong parents = meson_vpu_0_1_mux_parents;
516c8e57016SNeil Armstrong break;
517c8e57016SNeil Armstrong case CLKID_VPU_1_SEL:
518c8e57016SNeil Armstrong parm = &meson_vpu_1_mux_parm;
519c8e57016SNeil Armstrong parents = meson_vpu_0_1_mux_parents;
520c8e57016SNeil Armstrong break;
521c8e57016SNeil Armstrong case CLKID_VAPB_SEL:
522c8e57016SNeil Armstrong parm = &meson_vapb_sel_mux_parm;
523c8e57016SNeil Armstrong parents = meson_vapb_sel_mux_parents;
524c8e57016SNeil Armstrong break;
525c8e57016SNeil Armstrong case CLKID_VAPB_0_SEL:
526c8e57016SNeil Armstrong parm = &meson_vapb_0_mux_parm;
527c8e57016SNeil Armstrong parents = meson_vapb_0_1_mux_parents;
528c8e57016SNeil Armstrong break;
529c8e57016SNeil Armstrong case CLKID_VAPB_1_SEL:
530c8e57016SNeil Armstrong parm = &meson_vapb_1_mux_parm;
531c8e57016SNeil Armstrong parents = meson_vapb_0_1_mux_parents;
532c8e57016SNeil Armstrong break;
533c8e57016SNeil Armstrong default:
534c8e57016SNeil Armstrong /* Not a mux */
535c8e57016SNeil Armstrong return -ENOENT;
536c8e57016SNeil Armstrong }
537c8e57016SNeil Armstrong
538c8e57016SNeil Armstrong for (i = 0 ; i < (1 << parm->width) ; ++i) {
539c8e57016SNeil Armstrong if (parents[i] == parent_id)
540c8e57016SNeil Armstrong new_index = i;
541c8e57016SNeil Armstrong }
542c8e57016SNeil Armstrong
543c8e57016SNeil Armstrong if (IS_ERR_VALUE(new_index))
544c8e57016SNeil Armstrong return new_index;
545c8e57016SNeil Armstrong
546c8e57016SNeil Armstrong debug("%s: new index of %ld is %d\n", __func__, id, new_index);
547c8e57016SNeil Armstrong
548*8973d816SLoic Devulder regmap_update_bits(priv->map, parm->reg_off, SETPMASK(parm->width, parm->shift),
549*8973d816SLoic Devulder new_index << parm->shift);
550c8e57016SNeil Armstrong
551c8e57016SNeil Armstrong debug("%s: new parent of %ld is %ld\n",
552c8e57016SNeil Armstrong __func__, id, meson_mux_get_parent(clk, id));
553c8e57016SNeil Armstrong
554c8e57016SNeil Armstrong return 0;
555c8e57016SNeil Armstrong }
556c8e57016SNeil Armstrong
meson_mux_get_rate(struct clk * clk,unsigned long id)557c8e57016SNeil Armstrong static ulong meson_mux_get_rate(struct clk *clk, unsigned long id)
558c8e57016SNeil Armstrong {
559c8e57016SNeil Armstrong int parent = meson_mux_get_parent(clk, id);
560c8e57016SNeil Armstrong
561c8e57016SNeil Armstrong if (IS_ERR_VALUE(parent))
562c8e57016SNeil Armstrong return parent;
563c8e57016SNeil Armstrong
564c8e57016SNeil Armstrong return meson_clk_get_rate_by_id(clk, parent);
565c0fc1e21SBeniamino Galvani }
566c0fc1e21SBeniamino Galvani
meson_clk81_get_rate(struct clk * clk)567c0fc1e21SBeniamino Galvani static unsigned long meson_clk81_get_rate(struct clk *clk)
568c0fc1e21SBeniamino Galvani {
569c0fc1e21SBeniamino Galvani struct meson_clk *priv = dev_get_priv(clk->dev);
570c0fc1e21SBeniamino Galvani unsigned long parent_rate;
571*8973d816SLoic Devulder uint reg;
572c0fc1e21SBeniamino Galvani int parents[] = {
573c0fc1e21SBeniamino Galvani -1,
574c0fc1e21SBeniamino Galvani -1,
575c0fc1e21SBeniamino Galvani CLKID_FCLK_DIV7,
576c0fc1e21SBeniamino Galvani CLKID_MPLL1,
577c0fc1e21SBeniamino Galvani CLKID_MPLL2,
578c0fc1e21SBeniamino Galvani CLKID_FCLK_DIV4,
579c0fc1e21SBeniamino Galvani CLKID_FCLK_DIV3,
580c0fc1e21SBeniamino Galvani CLKID_FCLK_DIV5
581c0fc1e21SBeniamino Galvani };
582c0fc1e21SBeniamino Galvani
583c0fc1e21SBeniamino Galvani /* mux */
584*8973d816SLoic Devulder regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®);
585c0fc1e21SBeniamino Galvani reg = (reg >> 12) & 7;
586c0fc1e21SBeniamino Galvani
587c0fc1e21SBeniamino Galvani switch (reg) {
588c0fc1e21SBeniamino Galvani case 0:
589c0fc1e21SBeniamino Galvani parent_rate = XTAL_RATE;
590c0fc1e21SBeniamino Galvani break;
591c0fc1e21SBeniamino Galvani case 1:
592c0fc1e21SBeniamino Galvani return -ENOENT;
593c0fc1e21SBeniamino Galvani default:
594c0fc1e21SBeniamino Galvani parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]);
595c0fc1e21SBeniamino Galvani }
596c0fc1e21SBeniamino Galvani
597c0fc1e21SBeniamino Galvani /* divider */
598*8973d816SLoic Devulder regmap_read(priv->map, HHI_MPEG_CLK_CNTL, ®);
599c0fc1e21SBeniamino Galvani reg = reg & ((1 << 7) - 1);
600c0fc1e21SBeniamino Galvani
6012fa77bd1SJerome Brunet /* clk81 divider is zero based */
6022fa77bd1SJerome Brunet return parent_rate / (reg + 1);
603c0fc1e21SBeniamino Galvani }
604c0fc1e21SBeniamino Galvani
mpll_rate_from_params(unsigned long parent_rate,unsigned long sdm,unsigned long n2)605c0fc1e21SBeniamino Galvani static long mpll_rate_from_params(unsigned long parent_rate,
606c0fc1e21SBeniamino Galvani unsigned long sdm,
607c0fc1e21SBeniamino Galvani unsigned long n2)
608c0fc1e21SBeniamino Galvani {
609c0fc1e21SBeniamino Galvani unsigned long divisor = (SDM_DEN * n2) + sdm;
610c0fc1e21SBeniamino Galvani
611c0fc1e21SBeniamino Galvani if (n2 < N2_MIN)
612c0fc1e21SBeniamino Galvani return -EINVAL;
613c0fc1e21SBeniamino Galvani
614c0fc1e21SBeniamino Galvani return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor);
615c0fc1e21SBeniamino Galvani }
616c0fc1e21SBeniamino Galvani
617c0fc1e21SBeniamino Galvani static struct parm meson_mpll0_parm[3] = {
618c0fc1e21SBeniamino Galvani {HHI_MPLL_CNTL7, 0, 14}, /* psdm */
619c0fc1e21SBeniamino Galvani {HHI_MPLL_CNTL7, 16, 9}, /* pn2 */
620c0fc1e21SBeniamino Galvani };
621c0fc1e21SBeniamino Galvani
622c0fc1e21SBeniamino Galvani static struct parm meson_mpll1_parm[3] = {
623c0fc1e21SBeniamino Galvani {HHI_MPLL_CNTL8, 0, 14}, /* psdm */
624c0fc1e21SBeniamino Galvani {HHI_MPLL_CNTL8, 16, 9}, /* pn2 */
625c0fc1e21SBeniamino Galvani };
626c0fc1e21SBeniamino Galvani
627c0fc1e21SBeniamino Galvani static struct parm meson_mpll2_parm[3] = {
628c0fc1e21SBeniamino Galvani {HHI_MPLL_CNTL9, 0, 14}, /* psdm */
629c0fc1e21SBeniamino Galvani {HHI_MPLL_CNTL9, 16, 9}, /* pn2 */
630c0fc1e21SBeniamino Galvani };
631c0fc1e21SBeniamino Galvani
632c0fc1e21SBeniamino Galvani /*
633c0fc1e21SBeniamino Galvani * MultiPhase Locked Loops are outputs from a PLL with additional frequency
634c0fc1e21SBeniamino Galvani * scaling capabilities. MPLL rates are calculated as:
635c0fc1e21SBeniamino Galvani *
636c0fc1e21SBeniamino Galvani * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
637c0fc1e21SBeniamino Galvani */
meson_mpll_get_rate(struct clk * clk,unsigned long id)638c0fc1e21SBeniamino Galvani static ulong meson_mpll_get_rate(struct clk *clk, unsigned long id)
639c0fc1e21SBeniamino Galvani {
640c0fc1e21SBeniamino Galvani struct meson_clk *priv = dev_get_priv(clk->dev);
641c0fc1e21SBeniamino Galvani struct parm *psdm, *pn2;
642*8973d816SLoic Devulder unsigned long sdm, n2;
643c0fc1e21SBeniamino Galvani unsigned long parent_rate;
644*8973d816SLoic Devulder uint reg;
645c0fc1e21SBeniamino Galvani
646c0fc1e21SBeniamino Galvani switch (id) {
647c0fc1e21SBeniamino Galvani case CLKID_MPLL0:
648c0fc1e21SBeniamino Galvani psdm = &meson_mpll0_parm[0];
649c0fc1e21SBeniamino Galvani pn2 = &meson_mpll0_parm[1];
650c0fc1e21SBeniamino Galvani break;
651c0fc1e21SBeniamino Galvani case CLKID_MPLL1:
652c0fc1e21SBeniamino Galvani psdm = &meson_mpll1_parm[0];
653c0fc1e21SBeniamino Galvani pn2 = &meson_mpll1_parm[1];
654c0fc1e21SBeniamino Galvani break;
655c0fc1e21SBeniamino Galvani case CLKID_MPLL2:
656c0fc1e21SBeniamino Galvani psdm = &meson_mpll2_parm[0];
657c0fc1e21SBeniamino Galvani pn2 = &meson_mpll2_parm[1];
658c0fc1e21SBeniamino Galvani break;
659c0fc1e21SBeniamino Galvani default:
660c0fc1e21SBeniamino Galvani return -ENOENT;
661c0fc1e21SBeniamino Galvani }
662c0fc1e21SBeniamino Galvani
663c0fc1e21SBeniamino Galvani parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL);
664c0fc1e21SBeniamino Galvani if (IS_ERR_VALUE(parent_rate))
665c0fc1e21SBeniamino Galvani return parent_rate;
666c0fc1e21SBeniamino Galvani
667*8973d816SLoic Devulder regmap_read(priv->map, psdm->reg_off, ®);
668c0fc1e21SBeniamino Galvani sdm = PARM_GET(psdm->width, psdm->shift, reg);
669c0fc1e21SBeniamino Galvani
670*8973d816SLoic Devulder regmap_read(priv->map, pn2->reg_off, ®);
671c0fc1e21SBeniamino Galvani n2 = PARM_GET(pn2->width, pn2->shift, reg);
672c0fc1e21SBeniamino Galvani
673c0fc1e21SBeniamino Galvani return mpll_rate_from_params(parent_rate, sdm, n2);
674c0fc1e21SBeniamino Galvani }
675c0fc1e21SBeniamino Galvani
676c0fc1e21SBeniamino Galvani static struct parm meson_fixed_pll_parm[3] = {
677c0fc1e21SBeniamino Galvani {HHI_MPLL_CNTL, 0, 9}, /* pm */
678c0fc1e21SBeniamino Galvani {HHI_MPLL_CNTL, 9, 5}, /* pn */
679c0fc1e21SBeniamino Galvani {HHI_MPLL_CNTL, 16, 2}, /* pod */
680c0fc1e21SBeniamino Galvani };
681c0fc1e21SBeniamino Galvani
682c0fc1e21SBeniamino Galvani static struct parm meson_sys_pll_parm[3] = {
683c0fc1e21SBeniamino Galvani {HHI_SYS_PLL_CNTL, 0, 9}, /* pm */
684c0fc1e21SBeniamino Galvani {HHI_SYS_PLL_CNTL, 9, 5}, /* pn */
685c0fc1e21SBeniamino Galvani {HHI_SYS_PLL_CNTL, 10, 2}, /* pod */
686c0fc1e21SBeniamino Galvani };
687c0fc1e21SBeniamino Galvani
meson_pll_get_rate(struct clk * clk,unsigned long id)688c0fc1e21SBeniamino Galvani static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
689c0fc1e21SBeniamino Galvani {
690c0fc1e21SBeniamino Galvani struct meson_clk *priv = dev_get_priv(clk->dev);
691c0fc1e21SBeniamino Galvani struct parm *pm, *pn, *pod;
692c0fc1e21SBeniamino Galvani unsigned long parent_rate_mhz = XTAL_RATE / 1000000;
693c0fc1e21SBeniamino Galvani u16 n, m, od;
694*8973d816SLoic Devulder uint reg;
695c0fc1e21SBeniamino Galvani
696c0fc1e21SBeniamino Galvani switch (id) {
697c0fc1e21SBeniamino Galvani case CLKID_FIXED_PLL:
698c0fc1e21SBeniamino Galvani pm = &meson_fixed_pll_parm[0];
699c0fc1e21SBeniamino Galvani pn = &meson_fixed_pll_parm[1];
700c0fc1e21SBeniamino Galvani pod = &meson_fixed_pll_parm[2];
701c0fc1e21SBeniamino Galvani break;
702c0fc1e21SBeniamino Galvani case CLKID_SYS_PLL:
703c0fc1e21SBeniamino Galvani pm = &meson_sys_pll_parm[0];
704c0fc1e21SBeniamino Galvani pn = &meson_sys_pll_parm[1];
705c0fc1e21SBeniamino Galvani pod = &meson_sys_pll_parm[2];
706c0fc1e21SBeniamino Galvani break;
707c0fc1e21SBeniamino Galvani default:
708c0fc1e21SBeniamino Galvani return -ENOENT;
709c0fc1e21SBeniamino Galvani }
710c0fc1e21SBeniamino Galvani
711*8973d816SLoic Devulder regmap_read(priv->map, pn->reg_off, ®);
712c0fc1e21SBeniamino Galvani n = PARM_GET(pn->width, pn->shift, reg);
713c0fc1e21SBeniamino Galvani
714*8973d816SLoic Devulder regmap_read(priv->map, pm->reg_off, ®);
715c0fc1e21SBeniamino Galvani m = PARM_GET(pm->width, pm->shift, reg);
716c0fc1e21SBeniamino Galvani
717*8973d816SLoic Devulder regmap_read(priv->map, pod->reg_off, ®);
718c0fc1e21SBeniamino Galvani od = PARM_GET(pod->width, pod->shift, reg);
719c0fc1e21SBeniamino Galvani
720c0fc1e21SBeniamino Galvani return ((parent_rate_mhz * m / n) >> od) * 1000000;
721c0fc1e21SBeniamino Galvani }
722c0fc1e21SBeniamino Galvani
meson_clk_get_rate_by_id(struct clk * clk,unsigned long id)723c0fc1e21SBeniamino Galvani static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id)
724c0fc1e21SBeniamino Galvani {
725c0fc1e21SBeniamino Galvani ulong rate;
726c0fc1e21SBeniamino Galvani
727c0fc1e21SBeniamino Galvani switch (id) {
728c0fc1e21SBeniamino Galvani case CLKID_FIXED_PLL:
729c0fc1e21SBeniamino Galvani case CLKID_SYS_PLL:
730c0fc1e21SBeniamino Galvani rate = meson_pll_get_rate(clk, id);
731c0fc1e21SBeniamino Galvani break;
732c0fc1e21SBeniamino Galvani case CLKID_FCLK_DIV2:
733c0fc1e21SBeniamino Galvani rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2;
734c0fc1e21SBeniamino Galvani break;
735c0fc1e21SBeniamino Galvani case CLKID_FCLK_DIV3:
736c0fc1e21SBeniamino Galvani rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3;
737c0fc1e21SBeniamino Galvani break;
738c0fc1e21SBeniamino Galvani case CLKID_FCLK_DIV4:
739c0fc1e21SBeniamino Galvani rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4;
740c0fc1e21SBeniamino Galvani break;
741c0fc1e21SBeniamino Galvani case CLKID_FCLK_DIV5:
742c0fc1e21SBeniamino Galvani rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5;
743c0fc1e21SBeniamino Galvani break;
744c0fc1e21SBeniamino Galvani case CLKID_FCLK_DIV7:
745c0fc1e21SBeniamino Galvani rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7;
746c0fc1e21SBeniamino Galvani break;
747c0fc1e21SBeniamino Galvani case CLKID_MPLL0:
748c0fc1e21SBeniamino Galvani case CLKID_MPLL1:
749c0fc1e21SBeniamino Galvani case CLKID_MPLL2:
750c0fc1e21SBeniamino Galvani rate = meson_mpll_get_rate(clk, id);
751c0fc1e21SBeniamino Galvani break;
752c0fc1e21SBeniamino Galvani case CLKID_CLK81:
753c0fc1e21SBeniamino Galvani rate = meson_clk81_get_rate(clk);
754c0fc1e21SBeniamino Galvani break;
755c8e57016SNeil Armstrong case CLKID_VPU_0:
756c8e57016SNeil Armstrong rate = meson_div_get_rate(clk, CLKID_VPU_0_DIV);
757c8e57016SNeil Armstrong break;
758c8e57016SNeil Armstrong case CLKID_VPU_1:
759c8e57016SNeil Armstrong rate = meson_div_get_rate(clk, CLKID_VPU_1_DIV);
760c8e57016SNeil Armstrong break;
761c8e57016SNeil Armstrong case CLKID_VAPB:
762c8e57016SNeil Armstrong rate = meson_mux_get_rate(clk, CLKID_VAPB_SEL);
763c8e57016SNeil Armstrong break;
764c8e57016SNeil Armstrong case CLKID_VAPB_0:
765c8e57016SNeil Armstrong rate = meson_div_get_rate(clk, CLKID_VAPB_0_DIV);
766c8e57016SNeil Armstrong break;
767c8e57016SNeil Armstrong case CLKID_VAPB_1:
768c8e57016SNeil Armstrong rate = meson_div_get_rate(clk, CLKID_VAPB_1_DIV);
769c8e57016SNeil Armstrong break;
770c8e57016SNeil Armstrong case CLKID_VPU_0_DIV:
771c8e57016SNeil Armstrong case CLKID_VPU_1_DIV:
772c8e57016SNeil Armstrong case CLKID_VAPB_0_DIV:
773c8e57016SNeil Armstrong case CLKID_VAPB_1_DIV:
774c8e57016SNeil Armstrong rate = meson_div_get_rate(clk, id);
775c8e57016SNeil Armstrong break;
776c8e57016SNeil Armstrong case CLKID_VPU:
777c8e57016SNeil Armstrong case CLKID_VPU_0_SEL:
778c8e57016SNeil Armstrong case CLKID_VPU_1_SEL:
779c8e57016SNeil Armstrong case CLKID_VAPB_SEL:
780c8e57016SNeil Armstrong case CLKID_VAPB_0_SEL:
781c8e57016SNeil Armstrong case CLKID_VAPB_1_SEL:
782c8e57016SNeil Armstrong rate = meson_mux_get_rate(clk, id);
783c8e57016SNeil Armstrong break;
784c0fc1e21SBeniamino Galvani default:
785c0fc1e21SBeniamino Galvani if (gates[id].reg != 0) {
786c0fc1e21SBeniamino Galvani /* a clock gate */
787c0fc1e21SBeniamino Galvani rate = meson_clk81_get_rate(clk);
788c0fc1e21SBeniamino Galvani break;
789c0fc1e21SBeniamino Galvani }
790c0fc1e21SBeniamino Galvani return -ENOENT;
791c0fc1e21SBeniamino Galvani }
792c0fc1e21SBeniamino Galvani
793572aeb53SJerome Brunet debug("clock %lu has rate %lu\n", id, rate);
794c0fc1e21SBeniamino Galvani return rate;
795c0fc1e21SBeniamino Galvani }
796c0fc1e21SBeniamino Galvani
meson_clk_get_rate(struct clk * clk)797c0fc1e21SBeniamino Galvani static ulong meson_clk_get_rate(struct clk *clk)
798c0fc1e21SBeniamino Galvani {
799c0fc1e21SBeniamino Galvani return meson_clk_get_rate_by_id(clk, clk->id);
800c0fc1e21SBeniamino Galvani }
801c0fc1e21SBeniamino Galvani
meson_clk_set_parent(struct clk * clk,struct clk * parent)802c8e57016SNeil Armstrong static int meson_clk_set_parent(struct clk *clk, struct clk *parent)
803c8e57016SNeil Armstrong {
804c8e57016SNeil Armstrong return meson_mux_set_parent(clk, clk->id, parent->id);
805c8e57016SNeil Armstrong }
806c8e57016SNeil Armstrong
meson_clk_set_rate_by_id(struct clk * clk,unsigned long id,ulong rate,ulong current_rate)807c8e57016SNeil Armstrong static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned long id,
808c8e57016SNeil Armstrong ulong rate, ulong current_rate)
809c8e57016SNeil Armstrong {
810c8e57016SNeil Armstrong if (current_rate == rate)
811c8e57016SNeil Armstrong return 0;
812c8e57016SNeil Armstrong
813c8e57016SNeil Armstrong switch (id) {
814c8e57016SNeil Armstrong /* Fixed clocks */
815c8e57016SNeil Armstrong case CLKID_FIXED_PLL:
816c8e57016SNeil Armstrong case CLKID_SYS_PLL:
817c8e57016SNeil Armstrong case CLKID_FCLK_DIV2:
818c8e57016SNeil Armstrong case CLKID_FCLK_DIV3:
819c8e57016SNeil Armstrong case CLKID_FCLK_DIV4:
820c8e57016SNeil Armstrong case CLKID_FCLK_DIV5:
821c8e57016SNeil Armstrong case CLKID_FCLK_DIV7:
822c8e57016SNeil Armstrong case CLKID_MPLL0:
823c8e57016SNeil Armstrong case CLKID_MPLL1:
824c8e57016SNeil Armstrong case CLKID_MPLL2:
825c8e57016SNeil Armstrong case CLKID_CLK81:
826c8e57016SNeil Armstrong if (current_rate != rate)
827c8e57016SNeil Armstrong return -EINVAL;
828c8e57016SNeil Armstrong
829c8e57016SNeil Armstrong return 0;
830c8e57016SNeil Armstrong case CLKID_VPU:
831c8e57016SNeil Armstrong return meson_clk_set_rate_by_id(clk,
832c8e57016SNeil Armstrong meson_mux_get_parent(clk, CLKID_VPU), rate,
833c8e57016SNeil Armstrong current_rate);
834c8e57016SNeil Armstrong case CLKID_VAPB:
835c8e57016SNeil Armstrong case CLKID_VAPB_SEL:
836c8e57016SNeil Armstrong return meson_clk_set_rate_by_id(clk,
837c8e57016SNeil Armstrong meson_mux_get_parent(clk, CLKID_VAPB_SEL),
838c8e57016SNeil Armstrong rate, current_rate);
839c8e57016SNeil Armstrong case CLKID_VPU_0:
840c8e57016SNeil Armstrong return meson_div_set_rate(clk, CLKID_VPU_0_DIV, rate,
841c8e57016SNeil Armstrong current_rate);
842c8e57016SNeil Armstrong case CLKID_VPU_1:
843c8e57016SNeil Armstrong return meson_div_set_rate(clk, CLKID_VPU_1_DIV, rate,
844c8e57016SNeil Armstrong current_rate);
845c8e57016SNeil Armstrong case CLKID_VAPB_0:
846c8e57016SNeil Armstrong return meson_div_set_rate(clk, CLKID_VAPB_0_DIV, rate,
847c8e57016SNeil Armstrong current_rate);
848c8e57016SNeil Armstrong case CLKID_VAPB_1:
849c8e57016SNeil Armstrong return meson_div_set_rate(clk, CLKID_VAPB_1_DIV, rate,
850c8e57016SNeil Armstrong current_rate);
851c8e57016SNeil Armstrong case CLKID_VPU_0_DIV:
852c8e57016SNeil Armstrong case CLKID_VPU_1_DIV:
853c8e57016SNeil Armstrong case CLKID_VAPB_0_DIV:
854c8e57016SNeil Armstrong case CLKID_VAPB_1_DIV:
855c8e57016SNeil Armstrong return meson_div_set_rate(clk, id, rate, current_rate);
856c8e57016SNeil Armstrong default:
857c8e57016SNeil Armstrong return -ENOENT;
858c8e57016SNeil Armstrong }
859c8e57016SNeil Armstrong
860c8e57016SNeil Armstrong return -EINVAL;
861c8e57016SNeil Armstrong }
862c8e57016SNeil Armstrong
meson_clk_set_rate(struct clk * clk,ulong rate)863c8e57016SNeil Armstrong static ulong meson_clk_set_rate(struct clk *clk, ulong rate)
864c8e57016SNeil Armstrong {
865c8e57016SNeil Armstrong ulong current_rate = meson_clk_get_rate_by_id(clk, clk->id);
866c8e57016SNeil Armstrong int ret;
867c8e57016SNeil Armstrong
868c8e57016SNeil Armstrong if (IS_ERR_VALUE(current_rate))
869c8e57016SNeil Armstrong return current_rate;
870c8e57016SNeil Armstrong
871c8e57016SNeil Armstrong debug("%s: setting rate of %ld from %ld to %ld\n",
872c8e57016SNeil Armstrong __func__, clk->id, current_rate, rate);
873c8e57016SNeil Armstrong
874c8e57016SNeil Armstrong ret = meson_clk_set_rate_by_id(clk, clk->id, rate, current_rate);
875c8e57016SNeil Armstrong if (IS_ERR_VALUE(ret))
876c8e57016SNeil Armstrong return ret;
877c8e57016SNeil Armstrong
878*8973d816SLoic Devulder debug("clock %lu has new rate %lu\n", clk->id,
879c8e57016SNeil Armstrong meson_clk_get_rate_by_id(clk, clk->id));
880c8e57016SNeil Armstrong
881c8e57016SNeil Armstrong return 0;
882c8e57016SNeil Armstrong }
883c8e57016SNeil Armstrong
meson_clk_probe(struct udevice * dev)884c0fc1e21SBeniamino Galvani static int meson_clk_probe(struct udevice *dev)
885c0fc1e21SBeniamino Galvani {
886c0fc1e21SBeniamino Galvani struct meson_clk *priv = dev_get_priv(dev);
887c0fc1e21SBeniamino Galvani
888*8973d816SLoic Devulder priv->map = syscon_node_to_regmap(dev_get_parent(dev)->node);
889*8973d816SLoic Devulder if (IS_ERR(priv->map))
890*8973d816SLoic Devulder return PTR_ERR(priv->map);
891c0fc1e21SBeniamino Galvani
892*8973d816SLoic Devulder debug("meson-clk: probed\n");
893c0fc1e21SBeniamino Galvani
894c0fc1e21SBeniamino Galvani return 0;
895c0fc1e21SBeniamino Galvani }
896c0fc1e21SBeniamino Galvani
897c0fc1e21SBeniamino Galvani static struct clk_ops meson_clk_ops = {
898c0fc1e21SBeniamino Galvani .disable = meson_clk_disable,
899c0fc1e21SBeniamino Galvani .enable = meson_clk_enable,
900c0fc1e21SBeniamino Galvani .get_rate = meson_clk_get_rate,
901c8e57016SNeil Armstrong .set_parent = meson_clk_set_parent,
902c8e57016SNeil Armstrong .set_rate = meson_clk_set_rate,
903c0fc1e21SBeniamino Galvani };
904c0fc1e21SBeniamino Galvani
905c0fc1e21SBeniamino Galvani static const struct udevice_id meson_clk_ids[] = {
906c0fc1e21SBeniamino Galvani { .compatible = "amlogic,gxbb-clkc" },
907c0fc1e21SBeniamino Galvani { .compatible = "amlogic,gxl-clkc" },
908c0fc1e21SBeniamino Galvani { }
909c0fc1e21SBeniamino Galvani };
910c0fc1e21SBeniamino Galvani
911c0fc1e21SBeniamino Galvani U_BOOT_DRIVER(meson_clk) = {
912c0fc1e21SBeniamino Galvani .name = "meson_clk",
913c0fc1e21SBeniamino Galvani .id = UCLASS_CLK,
914c0fc1e21SBeniamino Galvani .of_match = meson_clk_ids,
915c0fc1e21SBeniamino Galvani .priv_auto_alloc_size = sizeof(struct meson_clk),
916c0fc1e21SBeniamino Galvani .ops = &meson_clk_ops,
917c0fc1e21SBeniamino Galvani .probe = meson_clk_probe,
918c0fc1e21SBeniamino Galvani };
919