clk/sifive/wrpll-cln28hpc.c

80  * @post_divr_freq: input clock rate after the R divider
142  * __wrpll_calc_divq() - determine DIVQ based on target PLL output clock rate
143  * @target_rate: target PLL output clock rate
144  * @vco_rate: pointer to a u64 to store the computed VCO rate into
147  * target output rate @target_rate for the PLL.  Along with returning the
149  * desired target VCO rate into the variable pointed to by @vco_rate.
184  * __wrpll_update_parent_rate() - update PLL data when parent rate changes
186  * @parent_rate: PLL input refclk rate (pre-R-divider)
189  * the PLL's reference clock rate changes.  The intention is to avoid
190  * computation when the parent rate remains constant - expected to be
193  * Returns: 0 upon success or -1 if the reference clock rate is out of range.
219  * analogbits_wrpll_configure() - compute PLL configuration for a target rate
221  * @target_rate: target PLL output clock rate (post-Q-divider)
222  * @parent_rate: PLL input refclk rate (pre-R-divider)
225  * rate @target_rate, and a reference clock input rate @parent_rate,
272 			pr_err("%s: PLL input rate is out of range\n",  in analogbits_wrpll_configure_for_rate()
280 	/* Put the PLL into bypass if the user requests the parent clock rate */  in analogbits_wrpll_configure_for_rate()
287 	/* Calculate the Q shift and target VCO rate */  in analogbits_wrpll_configure_for_rate()
344  * analogbits_wrpll_calc_output_rate() - calculate the PLL's target output rate
346  * @parent_rate: PLL refclk rate
349  * PLL's input reference clock rate @parent_rate (before the R
350  * pre-divider), calculate the PLL's output clock rate (after the Q
356  * Return: the PLL's output clock rate, in Hz.