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/openbmc/linux/drivers/net/mdio/
H A Dmdio-mscc-miim.c14 #include <linux/mdio/mdio-mscc-miim.h>
75 struct mscc_miim_dev *miim = bus->priv; in mscc_miim_status() local
78 ret = regmap_read(miim->regs, in mscc_miim_status()
79 MSCC_MIIM_REG_STATUS + miim->mii_status_offset, &val); in mscc_miim_status()
81 WARN_ONCE(1, "mscc miim status read error %d\n", ret); in mscc_miim_status()
108 struct mscc_miim_dev *miim = bus->priv; in mscc_miim_read() local
116 ret = regmap_write(miim->regs, in mscc_miim_read()
117 MSCC_MIIM_REG_CMD + miim->mii_status_offset, in mscc_miim_read()
124 WARN_ONCE(1, "mscc miim write cmd reg error %d\n", ret); in mscc_miim_read()
132 ret = regmap_read(miim->regs, in mscc_miim_read()
[all …]
H A DKconfig144 tristate "Microsemi MIIM interface support"
148 This driver supports the MIIM (MDIO) interface found in the network
H A DMakefile19 obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-mscc-miim.o
/openbmc/u-boot/drivers/net/mscc_eswitch/
H A Dmscc_miim.c24 static int mscc_miim_wait_ready(struct mscc_miim_dev *miim) in mscc_miim_wait_ready() argument
26 return wait_for_bit_le32(miim->regs + MIIM_STATUS, MIIM_STAT_BUSY, in mscc_miim_wait_ready()
32 struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv; in mscc_miim_read() local
36 ret = mscc_miim_wait_ready(miim); in mscc_miim_read()
42 miim->regs + MIIM_CMD); in mscc_miim_read()
44 ret = mscc_miim_wait_ready(miim); in mscc_miim_read()
48 val = readl(miim->regs + MIIM_DATA); in mscc_miim_read()
62 struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv; in mscc_miim_write() local
65 ret = mscc_miim_wait_ready(miim); in mscc_miim_write()
71 MIIM_CMD_OPR_WRITE, miim->regs + MIIM_CMD); in mscc_miim_write()
H A Docelot_switch.c113 MIIM, enumerator
143 static struct mscc_miim_dev miim[NUM_PHY]; variable
147 struct mscc_miim_dev *miim = (struct mscc_miim_dev *)bus->priv; in mscc_miim_reset() local
149 if (miim->phy_regs) { in mscc_miim_reset()
150 writel(0, miim->phy_regs + PHY_CFG); in mscc_miim_reset()
152 | PHY_CFG_ENA, miim->phy_regs + PHY_CFG); in mscc_miim_reset()
193 strcpy(bus->name, "miim-internal"); in ocelot_mdiobus_init()
194 miim[INTERNAL].phy_regs = ioremap(phy_base[PHY], phy_size[PHY]); in ocelot_mdiobus_init()
195 miim[INTERNAL].regs = ioremap(phy_base[MIIM], phy_size[MIIM]); in ocelot_mdiobus_init()
196 bus->priv = &miim[INTERNAL]; in ocelot_mdiobus_init()
H A Dluton_switch.c181 MIIM, enumerator
210 static struct mscc_miim_dev miim[NUM_PHY]; variable
246 strcpy(bus->name, "miim-internal"); in luton_mdiobus_init()
247 miim[mdiobus_id].regs = ioremap(phy_base[mdiobus_id], in luton_mdiobus_init()
249 bus->priv = &miim[mdiobus_id]; in luton_mdiobus_init()
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmscc,miim.yaml4 $id: http://devicetree.org/schemas/net/mscc,miim.yaml#
7 title: Microsemi MII Management Controller (MIIM)
18 - mscc,ocelot-miim
19 - microchip,lan966x-miim
52 compatible = "mscc,ocelot-miim";
/openbmc/u-boot/arch/mips/mach-mscc/
H A Dphy.c27 MSCC_F_MII_CMD_MIIM_CMD_PHYAD(miim_addr); /* Miim addr */ in mscc_phy_rd_wr()
29 /* Enqueue MIIM operation to be executed */ in mscc_phy_rd_wr()
32 /* Wait for MIIM operation to finish */ in mscc_phy_rd_wr()
36 debug("Miim timeout"); in mscc_phy_rd_wr()
40 debug("Read status miim(%d): 0x%08x\n", miimdev, data); in mscc_phy_rd_wr()
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dmscc,ocelot.yaml54 $ref: /schemas/net/mscc,miim.yaml
58 - mscc,ocelot-miim
97 compatible = "mscc,ocelot-miim";
108 compatible = "mscc,ocelot-miim";
134 function = "miim";
/openbmc/u-boot/drivers/net/
H A Dpch_gbe.c341 if (readl(&mac_regs->miim) & PCH_GBE_MIIM_OPER_READY) in pch_gbe_mdio_ready()
353 u32 miim; in pch_gbe_mdio_read() local
358 miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) | in pch_gbe_mdio_read()
361 writel(miim, &mac_regs->miim); in pch_gbe_mdio_read()
366 return readl(&mac_regs->miim) & 0xffff; in pch_gbe_mdio_read()
373 u32 miim; in pch_gbe_mdio_write() local
378 miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) | in pch_gbe_mdio_write()
381 writel(miim, &mac_regs->miim); in pch_gbe_mdio_write()
H A Dpch_gbe.h114 /* MIIM */
258 u32 miim; member
/openbmc/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5.dtsi286 function = "miim";
291 function = "miim";
296 function = "miim";
426 compatible = "mscc,ocelot-miim";
434 compatible = "mscc,ocelot-miim";
444 compatible = "mscc,ocelot-miim";
454 compatible = "mscc,ocelot-miim";
/openbmc/linux/arch/mips/boot/dts/mscc/
H A Docelot.dtsi231 function = "miim";
239 compatible = "mscc,ocelot-miim";
261 compatible = "mscc,ocelot-miim";
/openbmc/u-boot/drivers/net/fm/
H A Dtgec_phy.c17 * done through the TSEC1 MIIM regs
59 * TSEC1 MIIM regs
H A Dmemac_phy.c37 * done through the TSEC1 MIIM regs
82 * TSEC1 MIIM regs
/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-ocelot.c239 [FUNC_MIIM] = "miim",
534 OCELOT_P(14, MIIM, TWI_SCL_M, SFP);
535 OCELOT_P(15, MIIM, TWI_SCL_M, SFP);
638 JAGUAR2_P(56, MIIM, SFP);
639 JAGUAR2_P(57, MIIM, SFP);
640 JAGUAR2_P(58, MIIM, SFP);
641 JAGUAR2_P(59, MIIM, SFP);
750 SERVALT_P(22, MIIM, SFP, TWI2);
751 SERVALT_P(23, MIIM, SFP, TWI2);
872 SPARX5_P(52, SFP, MIIM, TWI_SCL_M);
[all …]
/openbmc/linux/drivers/mfd/
H A Docelot-core.c175 .of_compatible = "mscc,ocelot-miim",
182 .of_compatible = "mscc,ocelot-miim",
/openbmc/linux/drivers/net/ethernet/freescale/
H A Dfsl_pq_mdio.c3 * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
4 * Provides Bus interface for MIIM regs
162 /* Reset the MIIM registers, and wait for the bus to free */
H A Dxgmac_mdio.c204 * TSEC1 MIIM regs.
263 * TSEC1 MIIM regs.
/openbmc/u-boot/board/mscc/ocelot/
H A Docelot.c74 /* Enable MIIM */ in do_board_detect()
/openbmc/linux/drivers/net/ethernet/oki-semi/pch_gbe/
H A Dpch_gbe.h63 u32 MIIM; member
104 #define PCH_GBE_INT_MIIM_CMPLT 0x00010000 /* MIIM I/F Read completion */
238 /* MIIM */
/openbmc/u-boot/board/mscc/jr2/
H A Djr2.c79 /* MIIM 1 + 2 MDC/MDIO */ in do_board_detect()
/openbmc/linux/drivers/net/ethernet/xilinx/
H A Dll_temac_mdio.c30 /* Write the PHY address to the MIIM Access Initiator register. in temac_mdio_read()
/openbmc/qemu/hw/net/
H A Dmeson.build58 'fsl_etsec/miim.c',
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dlan966x-kontron-kswitch-d10-mmt.dtsi61 miim_c_pins: miim-c-pins {

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