Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38 |
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#
7dd900ea |
| 02-Jul-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: microchip: minor whitespace cleanup around '='
The DTS code coding style expects exactly one space before and after '=' sign.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@lin
arm64: dts: microchip: minor whitespace cleanup around '='
The DTS code coding style expects exactly one space before and after '=' sign.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230702185108.43959-1-krzysztof.kozlowski@linaro.org [claudiu.beznea: added link] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
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Revision tags: v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3, v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13 |
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#
a34ebb17 |
| 21-Feb-2023 |
Robert Marko <robert.marko@sartura.hr> |
arm64: dts: microchip: sparx5: correct CPU address-cells
There is no reason for CPU node #address-cells to be set at 2, so lets change them to 1 and update the reg property accordingly.
Signed-off-
arm64: dts: microchip: sparx5: correct CPU address-cells
There is no reason for CPU node #address-cells to be set at 2, so lets change them to 1 and update the reg property accordingly.
Signed-off-by: Robert Marko <robert.marko@sartura.hr> Link: https://lore.kernel.org/r/20230221105039.316819-2-robert.marko@sartura.hr Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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#
70be8370 |
| 21-Feb-2023 |
Robert Marko <robert.marko@sartura.hr> |
arm64: dts: microchip: sparx5: do not use PSCI on reference boards
PSCI is not implemented on SparX-5 at all, there is no ATF and U-boot that is shipped does not implement it as well.
I have tried
arm64: dts: microchip: sparx5: do not use PSCI on reference boards
PSCI is not implemented on SparX-5 at all, there is no ATF and U-boot that is shipped does not implement it as well.
I have tried flashing the latest BSP 2022.12 U-boot which did not work. After contacting Microchip, they confirmed that there is no ATF for the SoC nor PSCI implementation which is unfortunate in 2023.
So, disable PSCI as otherwise kernel crashes as soon as it tries probing PSCI with, and the crash is only visible if earlycon is used.
Since PSCI is not implemented, switch core bringup to use spin-tables which are implemented in the vendor U-boot and actually work.
Tested on PCB134 with eMMC (VSC5640EV).
Fixes: 6694aee00a4b ("arm64: dts: sparx5: Add basic cpu support") Signed-off-by: Robert Marko <robert.marko@sartura.hr> Acked-by: Steen Hegelund <Steen.Hegelund@microchip.com> Link: https://lore.kernel.org/r/20230221105039.316819-1-robert.marko@sartura.hr Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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#
f217d94f |
| 21-Apr-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: microchip: add missing cache properties
As all level 2 and level 3 caches are unified, add required cache-unified and cache-level properties to fix warnings like:
sparx5_pcb125.dtb: l
arm64: dts: microchip: add missing cache properties
As all level 2 and level 3 caches are unified, add required cache-unified and cache-level properties to fix warnings like:
sparx5_pcb125.dtb: l2-cache0: 'cache-level' is a required property
Link: https://lore.kernel.org/r/20230421223155.115339-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Revision tags: v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1 |
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#
e76d8a16 |
| 10-Dec-2022 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: microchip: drop 0x from unit address
By coding style, unit address should not start with 0x.
Link: https://lore.kernel.org/r/20221210113343.63864-1-krzysztof.kozlowski@linaro.org Signed
arm64: dts: microchip: drop 0x from unit address
By coding style, unit address should not start with 0x.
Link: https://lore.kernel.org/r/20221210113343.63864-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Revision tags: v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78, v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44, v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35, v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27 |
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#
6015fb90 |
| 04-Mar-2022 |
Horatiu Vultur <horatiu.vultur@microchip.com> |
dts: sparx5: Enable ptp interrupt
Add support for ptp interrupt. This interrupt is used when using 2-step timestamping. For each timestamp that is added in a queue, an interrupt is generated.
Signe
dts: sparx5: Enable ptp interrupt
Add support for ptp interrupt. This interrupt is used when using 2-step timestamping. For each timestamp that is added in a queue, an interrupt is generated.
Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Revision tags: v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61 |
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#
920c293a |
| 19-Aug-2021 |
Steen Hegelund <steen.hegelund@microchip.com> |
arm64: dts: sparx5: Add the Sparx5 switch frame DMA support
This adds the interrupt for the Sparx5 Frame DMA.
If this configuration is present the Sparx5 SwitchDev driver will use the Frame DMA fea
arm64: dts: sparx5: Add the Sparx5 switch frame DMA support
This adds the interrupt for the Sparx5 Frame DMA.
If this configuration is present the Sparx5 SwitchDev driver will use the Frame DMA feature, and if not it will use register based injection and extraction for sending and receiving frames to the CPU.
Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Revision tags: v5.10.60, v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13 |
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#
d0f482bb |
| 24-Jun-2021 |
Steen Hegelund <steen.hegelund@microchip.com> |
arm64: dts: sparx5: Add the Sparx5 switch node
This provides the configuration for the currently available evaluation boards PCB134 and PCB135.
The series depends on the following series currently
arm64: dts: sparx5: Add the Sparx5 switch node
This provides the configuration for the currently available evaluation boards PCB134 and PCB135.
The series depends on the following series currently on its way into the kernel:
- Sparx5 Reset Driver Link: https://lore.kernel.org/r/20210416084054.2922327-1-steen.hegelund@microchip.com/
Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Revision tags: v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40, v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14, v5.10 |
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#
7e1f91cb |
| 13-Nov-2020 |
Lars Povlsen <lars.povlsen@microchip.com> |
arm64: dts: sparx5: Add SGPIO devices
This adds SGPIO devices for the Sparx5 SoC and configures it for the applicable reference boards.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Revi
arm64: dts: sparx5: Add SGPIO devices
This adds SGPIO devices for the Sparx5 SoC and configures it for the applicable reference boards.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20201113145151.68900-4-lars.povlsen@microchip.com
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Revision tags: v5.8.17, v5.8.16, v5.8.15, v5.9, v5.8.14 |
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#
5ef399aa |
| 06-Oct-2020 |
Lars Povlsen <lars.povlsen@microchip.com> |
arm64: dts: sparx5: Add reset support
This adds reset support to the Sparx5 SoC DT.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20201006200316.2261245-4
arm64: dts: sparx5: Add reset support
This adds reset support to the Sparx5 SoC DT.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20201006200316.2261245-4-lars.povlsen@microchip.com
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Revision tags: v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61 |
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#
5df50128 |
| 24-Aug-2020 |
Lars Povlsen <lars.povlsen@microchip.com> |
arm64: dts: sparx5: Add spi-nand devices
This patch add spi-nand DT nodes to the applicable Sparx5 boards.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/2
arm64: dts: sparx5: Add spi-nand devices
This patch add spi-nand DT nodes to the applicable Sparx5 boards.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200824203010.2033-7-lars.povlsen@microchip.com
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#
08ee16e9 |
| 24-Aug-2020 |
Lars Povlsen <lars.povlsen@microchip.com> |
arm64: dts: sparx5: Add SPI controller and associated mmio-mux
This adds a SPI controller to the Microchip Sparx5 SoC, as well as the mmio-mux that is required to select the right SPI interface for
arm64: dts: sparx5: Add SPI controller and associated mmio-mux
This adds a SPI controller to the Microchip Sparx5 SoC, as well as the mmio-mux that is required to select the right SPI interface for a given SPI device.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200824203010.2033-4-lars.povlsen@microchip.com
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Revision tags: v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36 |
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#
d14f6a1a |
| 28-Apr-2020 |
Lars Povlsen <lars.povlsen@microchip.com> |
arm64: dts: sparx5: Add hwmon temperature sensor
This adds a hwmon temperature node sensor to the Sparx5 SoC.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/
arm64: dts: sparx5: Add hwmon temperature sensor
This adds a hwmon temperature node sensor to the Sparx5 SoC.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200618135951.25441-3-lars.povlsen@microchip.com
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#
45145406 |
| 28-Apr-2020 |
Lars Povlsen <lars.povlsen@microchip.com> |
arm64: dts: sparx5: Add Sparx5 eMMC support
This adds eMMC support to the applicable Sparx5 board configuration files.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.ke
arm64: dts: sparx5: Add Sparx5 eMMC support
This adds eMMC support to the applicable Sparx5 board configuration files.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200825081357.32354-4-lars.povlsen@microchip.com
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#
623910f4 |
| 15-Jun-2020 |
Lars Povlsen <lars.povlsen@microchip.com> |
arm64: dts: sparx5: Add i2c devices, i2c muxes
This patch adds i2c devices and muxes to the Sparx5 reference boards.
Link: https://lore.kernel.org/r/20200615133242.24911-11-lars.povlsen@microchip.c
arm64: dts: sparx5: Add i2c devices, i2c muxes
This patch adds i2c devices and muxes to the Sparx5 reference boards.
Link: https://lore.kernel.org/r/20200615133242.24911-11-lars.povlsen@microchip.com Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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#
e4e06a50 |
| 15-Jun-2020 |
Lars Povlsen <lars.povlsen@microchip.com> |
arm64: dts: sparx5: Add Sparx5 SoC DPLL clock
This adds a DPLL clock to the Sparx5 SoC. It is used to generate clock to misc peripherals, specifically the SDHCI/eMMC controller.
Link: https://lore.
arm64: dts: sparx5: Add Sparx5 SoC DPLL clock
This adds a DPLL clock to the Sparx5 SoC. It is used to generate clock to misc peripherals, specifically the SDHCI/eMMC controller.
Link: https://lore.kernel.org/r/20200615133242.24911-10-lars.povlsen@microchip.com Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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#
14bc6703 |
| 15-Jun-2020 |
Lars Povlsen <lars.povlsen@microchip.com> |
arm64: dts: sparx5: Add pinctrl support
This add pinctrl support to the Microchip Sparx5 SoC.
Link: https://lore.kernel.org/r/20200615133242.24911-5-lars.povlsen@microchip.com Reviewed-by: Alexandr
arm64: dts: sparx5: Add pinctrl support
This add pinctrl support to the Microchip Sparx5 SoC.
Link: https://lore.kernel.org/r/20200615133242.24911-5-lars.povlsen@microchip.com Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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#
6694aee0 |
| 15-Jun-2020 |
Lars Povlsen <lars.povlsen@microchip.com> |
arm64: dts: sparx5: Add basic cpu support
This adds the basic DT structure for the Microchip Sparx5 SoC, and the reference boards, pcb125, pcb134 and pcb135. The two latter have a NAND vs a eMMC cen
arm64: dts: sparx5: Add basic cpu support
This adds the basic DT structure for the Microchip Sparx5 SoC, and the reference boards, pcb125, pcb134 and pcb135. The two latter have a NAND vs a eMMC centric variant (as a mount option).
Link: https://lore.kernel.org/r/20200615133242.24911-4-lars.povlsen@microchip.com Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Revision tags: v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8, v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61 |
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#
5df50128 |
| 24-Aug-2020 |
Lars Povlsen <lars.povlsen@microchip.com> |
arm64: dts: sparx5: Add spi-nand devices This patch add spi-nand DT nodes to the applicable Sparx5 boards. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https:/
arm64: dts: sparx5: Add spi-nand devices This patch add spi-nand DT nodes to the applicable Sparx5 boards. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200824203010.2033-7-lars.povlsen@microchip.com
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#
08ee16e9 |
| 24-Aug-2020 |
Lars Povlsen <lars.povlsen@microchip.com> |
arm64: dts: sparx5: Add SPI controller and associated mmio-mux This adds a SPI controller to the Microchip Sparx5 SoC, as well as the mmio-mux that is required to select the right SPI in
arm64: dts: sparx5: Add SPI controller and associated mmio-mux This adds a SPI controller to the Microchip Sparx5 SoC, as well as the mmio-mux that is required to select the right SPI interface for a given SPI device. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200824203010.2033-4-lars.povlsen@microchip.com
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Revision tags: v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51, v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36 |
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#
d14f6a1a |
| 28-Apr-2020 |
Lars Povlsen <lars.povlsen@microchip.com> |
arm64: dts: sparx5: Add hwmon temperature sensor This adds a hwmon temperature node sensor to the Sparx5 SoC. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: http
arm64: dts: sparx5: Add hwmon temperature sensor This adds a hwmon temperature node sensor to the Sparx5 SoC. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200618135951.25441-3-lars.povlsen@microchip.com
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#
45145406 |
| 28-Apr-2020 |
Lars Povlsen <lars.povlsen@microchip.com> |
arm64: dts: sparx5: Add Sparx5 eMMC support This adds eMMC support to the applicable Sparx5 board configuration files. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
arm64: dts: sparx5: Add Sparx5 eMMC support This adds eMMC support to the applicable Sparx5 board configuration files. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Link: https://lore.kernel.org/r/20200825081357.32354-4-lars.povlsen@microchip.com
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623910f4 |
| 15-Jun-2020 |
Lars Povlsen <lars.povlsen@microchip.com> |
arm64: dts: sparx5: Add i2c devices, i2c muxes This patch adds i2c devices and muxes to the Sparx5 reference boards. Link: https://lore.kernel.org/r/20200615133242.24911-11-lars.pov
arm64: dts: sparx5: Add i2c devices, i2c muxes This patch adds i2c devices and muxes to the Sparx5 reference boards. Link: https://lore.kernel.org/r/20200615133242.24911-11-lars.povlsen@microchip.com Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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e4e06a50 |
| 15-Jun-2020 |
Lars Povlsen <lars.povlsen@microchip.com> |
arm64: dts: sparx5: Add Sparx5 SoC DPLL clock This adds a DPLL clock to the Sparx5 SoC. It is used to generate clock to misc peripherals, specifically the SDHCI/eMMC controller.
arm64: dts: sparx5: Add Sparx5 SoC DPLL clock This adds a DPLL clock to the Sparx5 SoC. It is used to generate clock to misc peripherals, specifically the SDHCI/eMMC controller. Link: https://lore.kernel.org/r/20200615133242.24911-10-lars.povlsen@microchip.com Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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14bc6703 |
| 15-Jun-2020 |
Lars Povlsen <lars.povlsen@microchip.com> |
arm64: dts: sparx5: Add pinctrl support This add pinctrl support to the Microchip Sparx5 SoC. Link: https://lore.kernel.org/r/20200615133242.24911-5-lars.povlsen@microchip.com R
arm64: dts: sparx5: Add pinctrl support This add pinctrl support to the Microchip Sparx5 SoC. Link: https://lore.kernel.org/r/20200615133242.24911-5-lars.povlsen@microchip.com Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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