1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2c916d7c9SKumar Gala /*
3c916d7c9SKumar Gala * Copyright 2009-2011 Freescale Semiconductor, Inc.
4b21f87a3SAndy Fleming * Andy Fleming <afleming@gmail.com>
5c916d7c9SKumar Gala * Some part is taken from tsec.c
6c916d7c9SKumar Gala */
7c916d7c9SKumar Gala #include <common.h>
8c916d7c9SKumar Gala #include <miiphy.h>
9c916d7c9SKumar Gala #include <phy.h>
10c916d7c9SKumar Gala #include <asm/io.h>
118225b2fdSShaohui Xie #include <fsl_tgec.h>
12c916d7c9SKumar Gala #include <fm_eth.h>
13c916d7c9SKumar Gala
14c916d7c9SKumar Gala /*
15c916d7c9SKumar Gala * Write value to the PHY for this device to the register at regnum, waiting
16c916d7c9SKumar Gala * until the write is done before it returns. All PHY configuration has to be
17c916d7c9SKumar Gala * done through the TSEC1 MIIM regs
18c916d7c9SKumar Gala */
tgec_mdio_write(struct mii_dev * bus,int port_addr,int dev_addr,int regnum,u16 value)19960d70c6SKim Phillips static int tgec_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
20c916d7c9SKumar Gala int regnum, u16 value)
21c916d7c9SKumar Gala {
22c916d7c9SKumar Gala u32 mdio_ctl;
23c916d7c9SKumar Gala u32 stat_val;
24c916d7c9SKumar Gala struct tgec_mdio_controller *regs = bus->priv;
25c916d7c9SKumar Gala
26c916d7c9SKumar Gala if (dev_addr == MDIO_DEVAD_NONE)
27c916d7c9SKumar Gala return 0;
28c916d7c9SKumar Gala
29c916d7c9SKumar Gala /* Wait till the bus is free */
30c916d7c9SKumar Gala stat_val = MDIO_STAT_CLKDIV(100);
31c916d7c9SKumar Gala out_be32(®s->mdio_stat, stat_val);
32c916d7c9SKumar Gala while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
33c916d7c9SKumar Gala ;
34c916d7c9SKumar Gala
35c916d7c9SKumar Gala /* Set the port and dev addr */
36c916d7c9SKumar Gala mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
37c916d7c9SKumar Gala out_be32(®s->mdio_ctl, mdio_ctl);
38c916d7c9SKumar Gala
39c916d7c9SKumar Gala /* Set the register address */
40c916d7c9SKumar Gala out_be32(®s->mdio_addr, regnum & 0xffff);
41c916d7c9SKumar Gala
42c916d7c9SKumar Gala /* Wait till the bus is free */
43c916d7c9SKumar Gala while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
44c916d7c9SKumar Gala ;
45c916d7c9SKumar Gala
46c916d7c9SKumar Gala /* Write the value to the register */
47c916d7c9SKumar Gala out_be32(®s->mdio_data, MDIO_DATA(value));
48c916d7c9SKumar Gala
49c916d7c9SKumar Gala /* Wait till the MDIO write is complete */
50c916d7c9SKumar Gala while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY)
51c916d7c9SKumar Gala ;
52c916d7c9SKumar Gala
53c916d7c9SKumar Gala return 0;
54c916d7c9SKumar Gala }
55c916d7c9SKumar Gala
56c916d7c9SKumar Gala /*
57c916d7c9SKumar Gala * Reads from register regnum in the PHY for device dev, returning the value.
58c916d7c9SKumar Gala * Clears miimcom first. All PHY configuration has to be done through the
59c916d7c9SKumar Gala * TSEC1 MIIM regs
60c916d7c9SKumar Gala */
tgec_mdio_read(struct mii_dev * bus,int port_addr,int dev_addr,int regnum)61960d70c6SKim Phillips static int tgec_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
62c916d7c9SKumar Gala int regnum)
63c916d7c9SKumar Gala {
64c916d7c9SKumar Gala u32 mdio_ctl;
65c916d7c9SKumar Gala u32 stat_val;
66c916d7c9SKumar Gala struct tgec_mdio_controller *regs = bus->priv;
67c916d7c9SKumar Gala
68c916d7c9SKumar Gala if (dev_addr == MDIO_DEVAD_NONE)
69c916d7c9SKumar Gala return 0xffff;
70c916d7c9SKumar Gala
71c916d7c9SKumar Gala stat_val = MDIO_STAT_CLKDIV(100);
72c916d7c9SKumar Gala out_be32(®s->mdio_stat, stat_val);
73c916d7c9SKumar Gala /* Wait till the bus is free */
74c916d7c9SKumar Gala while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
75c916d7c9SKumar Gala ;
76c916d7c9SKumar Gala
77c916d7c9SKumar Gala /* Set the Port and Device Addrs */
78c916d7c9SKumar Gala mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
79c916d7c9SKumar Gala out_be32(®s->mdio_ctl, mdio_ctl);
80c916d7c9SKumar Gala
81c916d7c9SKumar Gala /* Set the register address */
82c916d7c9SKumar Gala out_be32(®s->mdio_addr, regnum & 0xffff);
83c916d7c9SKumar Gala
84c916d7c9SKumar Gala /* Wait till the bus is free */
85c916d7c9SKumar Gala while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
86c916d7c9SKumar Gala ;
87c916d7c9SKumar Gala
88c916d7c9SKumar Gala /* Initiate the read */
89c916d7c9SKumar Gala mdio_ctl |= MDIO_CTL_READ;
90c916d7c9SKumar Gala out_be32(®s->mdio_ctl, mdio_ctl);
91c916d7c9SKumar Gala
92c916d7c9SKumar Gala /* Wait till the MDIO write is complete */
93c916d7c9SKumar Gala while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY)
94c916d7c9SKumar Gala ;
95c916d7c9SKumar Gala
96c916d7c9SKumar Gala /* Return all Fs if nothing was there */
97c916d7c9SKumar Gala if (in_be32(®s->mdio_stat) & MDIO_STAT_RD_ER)
98c916d7c9SKumar Gala return 0xffff;
99c916d7c9SKumar Gala
100c916d7c9SKumar Gala return in_be32(®s->mdio_data) & 0xffff;
101c916d7c9SKumar Gala }
102c916d7c9SKumar Gala
tgec_mdio_reset(struct mii_dev * bus)103960d70c6SKim Phillips static int tgec_mdio_reset(struct mii_dev *bus)
104c916d7c9SKumar Gala {
105c916d7c9SKumar Gala return 0;
106c916d7c9SKumar Gala }
107c916d7c9SKumar Gala
fm_tgec_mdio_init(bd_t * bis,struct tgec_mdio_info * info)108c916d7c9SKumar Gala int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info)
109c916d7c9SKumar Gala {
110c916d7c9SKumar Gala struct mii_dev *bus = mdio_alloc();
111c916d7c9SKumar Gala
112c916d7c9SKumar Gala if (!bus) {
113c916d7c9SKumar Gala printf("Failed to allocate FM TGEC MDIO bus\n");
114c916d7c9SKumar Gala return -1;
115c916d7c9SKumar Gala }
116c916d7c9SKumar Gala
117c916d7c9SKumar Gala bus->read = tgec_mdio_read;
118c916d7c9SKumar Gala bus->write = tgec_mdio_write;
119c916d7c9SKumar Gala bus->reset = tgec_mdio_reset;
120192bc694SBen Whitten strcpy(bus->name, info->name);
121c916d7c9SKumar Gala
122c916d7c9SKumar Gala bus->priv = info->regs;
123c916d7c9SKumar Gala
124c916d7c9SKumar Gala return mdio_register(bus);
125c916d7c9SKumar Gala }
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