1ed941f65SMichael Walle# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2ed941f65SMichael Walle%YAML 1.2 3ed941f65SMichael Walle--- 4ed941f65SMichael Walle$id: http://devicetree.org/schemas/net/mscc,miim.yaml# 5ed941f65SMichael Walle$schema: http://devicetree.org/meta-schemas/core.yaml# 6ed941f65SMichael Walle 7ed941f65SMichael Walletitle: Microsemi MII Management Controller (MIIM) 8ed941f65SMichael Walle 9ed941f65SMichael Wallemaintainers: 10ed941f65SMichael Walle - Alexandre Belloni <alexandre.belloni@bootlin.com> 11ed941f65SMichael Walle 12ed941f65SMichael WalleallOf: 13*3079bfdbSRob Herring - $ref: mdio.yaml# 14ed941f65SMichael Walle 15ed941f65SMichael Walleproperties: 16ed941f65SMichael Walle compatible: 17ed941f65SMichael Walle enum: 18ed941f65SMichael Walle - mscc,ocelot-miim 19ed941f65SMichael Walle - microchip,lan966x-miim 20ed941f65SMichael Walle 21ed941f65SMichael Walle "#address-cells": 22ed941f65SMichael Walle const: 1 23ed941f65SMichael Walle 24ed941f65SMichael Walle "#size-cells": 25ed941f65SMichael Walle const: 0 26ed941f65SMichael Walle 27ed941f65SMichael Walle reg: 28ed941f65SMichael Walle items: 29ed941f65SMichael Walle - description: base address 30ed941f65SMichael Walle - description: associated reset register for internal PHYs 31ed941f65SMichael Walle minItems: 1 32ed941f65SMichael Walle 33ed941f65SMichael Walle interrupts: 34ed941f65SMichael Walle maxItems: 1 35ed941f65SMichael Walle 36b0385d4cSMichael Walle clocks: 37b0385d4cSMichael Walle maxItems: 1 38b0385d4cSMichael Walle 39b0385d4cSMichael Walle clock-frequency: true 40b0385d4cSMichael Walle 41ed941f65SMichael Wallerequired: 42ed941f65SMichael Walle - compatible 43ed941f65SMichael Walle - reg 44ed941f65SMichael Walle - "#address-cells" 45ed941f65SMichael Walle - "#size-cells" 46ed941f65SMichael Walle 47ed941f65SMichael WalleunevaluatedProperties: false 48ed941f65SMichael Walle 49ed941f65SMichael Walleexamples: 50ed941f65SMichael Walle - | 51ed941f65SMichael Walle mdio@107009c { 52ed941f65SMichael Walle compatible = "mscc,ocelot-miim"; 53ed941f65SMichael Walle reg = <0x107009c 0x36>, <0x10700f0 0x8>; 54ed941f65SMichael Walle interrupts = <14>; 55ed941f65SMichael Walle #address-cells = <1>; 56ed941f65SMichael Walle #size-cells = <0>; 57ed941f65SMichael Walle 58ed941f65SMichael Walle phy0: ethernet-phy@0 { 59ed941f65SMichael Walle reg = <0>; 60ed941f65SMichael Walle }; 61ed941f65SMichael Walle }; 62