19f35a734STimur Tabi /*
29f35a734STimur Tabi * QorIQ 10G MDIO Controller
39f35a734STimur Tabi *
49f35a734STimur Tabi * Copyright 2012 Freescale Semiconductor, Inc.
515e7064eSCalvin Johnson * Copyright 2021 NXP
69f35a734STimur Tabi *
79f35a734STimur Tabi * Authors: Andy Fleming <afleming@freescale.com>
89f35a734STimur Tabi * Timur Tabi <timur@freescale.com>
99f35a734STimur Tabi *
109f35a734STimur Tabi * This file is licensed under the terms of the GNU General Public License
119f35a734STimur Tabi * version 2. This program is licensed "as is" without any warranty of any
129f35a734STimur Tabi * kind, whether express or implied.
139f35a734STimur Tabi */
149f35a734STimur Tabi
1515e7064eSCalvin Johnson #include <linux/acpi.h>
16ac53c264SMarcin Wojtas #include <linux/acpi_mdio.h>
17dd8f467eSTobias Waldekranz #include <linux/clk.h>
189f35a734STimur Tabi #include <linux/interrupt.h>
1915e7064eSCalvin Johnson #include <linux/kernel.h>
209f35a734STimur Tabi #include <linux/mdio.h>
2115e7064eSCalvin Johnson #include <linux/module.h>
22*3d40aed8SRob Herring #include <linux/of.h>
239f35a734STimur Tabi #include <linux/of_mdio.h>
2415e7064eSCalvin Johnson #include <linux/phy.h>
25*3d40aed8SRob Herring #include <linux/platform_device.h>
2615e7064eSCalvin Johnson #include <linux/slab.h>
279f35a734STimur Tabi
289f35a734STimur Tabi /* Number of microseconds to wait for a register to respond */
299f35a734STimur Tabi #define TIMEOUT 1000
309f35a734STimur Tabi
319f35a734STimur Tabi struct tgec_mdio_controller {
329f35a734STimur Tabi __be32 reserved[12];
339f35a734STimur Tabi __be32 mdio_stat; /* MDIO configuration and status */
349f35a734STimur Tabi __be32 mdio_ctl; /* MDIO control */
359f35a734STimur Tabi __be32 mdio_data; /* MDIO data */
369f35a734STimur Tabi __be32 mdio_addr; /* MDIO address */
379f35a734STimur Tabi } __packed;
389f35a734STimur Tabi
391fcf77c8SAndy Fleming #define MDIO_STAT_ENC BIT(6)
40dd8f467eSTobias Waldekranz #define MDIO_STAT_CLKDIV(x) (((x) & 0x1ff) << 7)
4149ff2d3fSShaohui Xie #define MDIO_STAT_BSY BIT(0)
4249ff2d3fSShaohui Xie #define MDIO_STAT_RD_ER BIT(1)
43909bea73STobias Waldekranz #define MDIO_STAT_PRE_DIS BIT(5)
449f35a734STimur Tabi #define MDIO_CTL_DEV_ADDR(x) (x & 0x1f)
459f35a734STimur Tabi #define MDIO_CTL_PORT_ADDR(x) ((x & 0x1f) << 5)
4649ff2d3fSShaohui Xie #define MDIO_CTL_PRE_DIS BIT(10)
4749ff2d3fSShaohui Xie #define MDIO_CTL_SCAN_EN BIT(11)
4849ff2d3fSShaohui Xie #define MDIO_CTL_POST_INC BIT(14)
4949ff2d3fSShaohui Xie #define MDIO_CTL_READ BIT(15)
509f35a734STimur Tabi
519f35a734STimur Tabi #define MDIO_DATA(x) (x & 0xffff)
529f35a734STimur Tabi
5373ee5442SShaohui Xie struct mdio_fsl_priv {
5473ee5442SShaohui Xie struct tgec_mdio_controller __iomem *mdio_base;
55dd8f467eSTobias Waldekranz struct clk *enet_clk;
56dd8f467eSTobias Waldekranz u32 mdc_freq;
5773ee5442SShaohui Xie bool is_little_endian;
586198c722STobias Waldekranz bool has_a009885;
591d3ca681SMadalin Bucur bool has_a011043;
6073ee5442SShaohui Xie };
6173ee5442SShaohui Xie
xgmac_read32(void __iomem * regs,bool is_little_endian)6273ee5442SShaohui Xie static u32 xgmac_read32(void __iomem *regs,
6373ee5442SShaohui Xie bool is_little_endian)
6473ee5442SShaohui Xie {
6573ee5442SShaohui Xie if (is_little_endian)
6673ee5442SShaohui Xie return ioread32(regs);
6773ee5442SShaohui Xie else
6873ee5442SShaohui Xie return ioread32be(regs);
6973ee5442SShaohui Xie }
7073ee5442SShaohui Xie
xgmac_write32(u32 value,void __iomem * regs,bool is_little_endian)7173ee5442SShaohui Xie static void xgmac_write32(u32 value,
7273ee5442SShaohui Xie void __iomem *regs,
7373ee5442SShaohui Xie bool is_little_endian)
7473ee5442SShaohui Xie {
7573ee5442SShaohui Xie if (is_little_endian)
7673ee5442SShaohui Xie iowrite32(value, regs);
7773ee5442SShaohui Xie else
7873ee5442SShaohui Xie iowrite32be(value, regs);
7973ee5442SShaohui Xie }
8073ee5442SShaohui Xie
819f35a734STimur Tabi /*
82c1543d37SMadalin Bucur * Wait until the MDIO bus is free
839f35a734STimur Tabi */
xgmac_wait_until_free(struct device * dev,struct tgec_mdio_controller __iomem * regs,bool is_little_endian)849f35a734STimur Tabi static int xgmac_wait_until_free(struct device *dev,
8573ee5442SShaohui Xie struct tgec_mdio_controller __iomem *regs,
8673ee5442SShaohui Xie bool is_little_endian)
879f35a734STimur Tabi {
8822f6bba7SShaohui Xie unsigned int timeout;
899f35a734STimur Tabi
909f35a734STimur Tabi /* Wait till the bus is free */
9122f6bba7SShaohui Xie timeout = TIMEOUT;
9273ee5442SShaohui Xie while ((xgmac_read32(®s->mdio_stat, is_little_endian) &
9373ee5442SShaohui Xie MDIO_STAT_BSY) && timeout) {
9422f6bba7SShaohui Xie cpu_relax();
9522f6bba7SShaohui Xie timeout--;
9622f6bba7SShaohui Xie }
9722f6bba7SShaohui Xie
9822f6bba7SShaohui Xie if (!timeout) {
999f35a734STimur Tabi dev_err(dev, "timeout waiting for bus to be free\n");
1009f35a734STimur Tabi return -ETIMEDOUT;
1019f35a734STimur Tabi }
1029f35a734STimur Tabi
1039f35a734STimur Tabi return 0;
1049f35a734STimur Tabi }
1059f35a734STimur Tabi
1069f35a734STimur Tabi /*
1079f35a734STimur Tabi * Wait till the MDIO read or write operation is complete
1089f35a734STimur Tabi */
xgmac_wait_until_done(struct device * dev,struct tgec_mdio_controller __iomem * regs,bool is_little_endian)1099f35a734STimur Tabi static int xgmac_wait_until_done(struct device *dev,
11073ee5442SShaohui Xie struct tgec_mdio_controller __iomem *regs,
11173ee5442SShaohui Xie bool is_little_endian)
1129f35a734STimur Tabi {
11322f6bba7SShaohui Xie unsigned int timeout;
1149f35a734STimur Tabi
1159f35a734STimur Tabi /* Wait till the MDIO write is complete */
11622f6bba7SShaohui Xie timeout = TIMEOUT;
11773ee5442SShaohui Xie while ((xgmac_read32(®s->mdio_stat, is_little_endian) &
11873ee5442SShaohui Xie MDIO_STAT_BSY) && timeout) {
11922f6bba7SShaohui Xie cpu_relax();
12022f6bba7SShaohui Xie timeout--;
12122f6bba7SShaohui Xie }
12222f6bba7SShaohui Xie
12322f6bba7SShaohui Xie if (!timeout) {
1249f35a734STimur Tabi dev_err(dev, "timeout waiting for operation to complete\n");
1259f35a734STimur Tabi return -ETIMEDOUT;
1269f35a734STimur Tabi }
1279f35a734STimur Tabi
1289f35a734STimur Tabi return 0;
1299f35a734STimur Tabi }
1309f35a734STimur Tabi
xgmac_mdio_write_c22(struct mii_bus * bus,int phy_id,int regnum,u16 value)131c0fc8e6dSAndrew Lunn static int xgmac_mdio_write_c22(struct mii_bus *bus, int phy_id, int regnum,
132c0fc8e6dSAndrew Lunn u16 value)
1339f35a734STimur Tabi {
13473ee5442SShaohui Xie struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv;
13573ee5442SShaohui Xie struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
136c0fc8e6dSAndrew Lunn bool endian = priv->is_little_endian;
137c0fc8e6dSAndrew Lunn u16 dev_addr = regnum & 0x1f;
1381fcf77c8SAndy Fleming u32 mdio_ctl, mdio_stat;
1399f35a734STimur Tabi int ret;
1409f35a734STimur Tabi
14173ee5442SShaohui Xie mdio_stat = xgmac_read32(®s->mdio_stat, endian);
1421fcf77c8SAndy Fleming mdio_stat &= ~MDIO_STAT_ENC;
143c0fc8e6dSAndrew Lunn xgmac_write32(mdio_stat, ®s->mdio_stat, endian);
144c0fc8e6dSAndrew Lunn
145c0fc8e6dSAndrew Lunn ret = xgmac_wait_until_free(&bus->dev, regs, endian);
146c0fc8e6dSAndrew Lunn if (ret)
147c0fc8e6dSAndrew Lunn return ret;
148c0fc8e6dSAndrew Lunn
149c0fc8e6dSAndrew Lunn /* Set the port and dev addr */
150c0fc8e6dSAndrew Lunn mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
151c0fc8e6dSAndrew Lunn xgmac_write32(mdio_ctl, ®s->mdio_ctl, endian);
152c0fc8e6dSAndrew Lunn
153c0fc8e6dSAndrew Lunn /* Write the value to the register */
154c0fc8e6dSAndrew Lunn xgmac_write32(MDIO_DATA(value), ®s->mdio_data, endian);
155c0fc8e6dSAndrew Lunn
156c0fc8e6dSAndrew Lunn ret = xgmac_wait_until_done(&bus->dev, regs, endian);
157c0fc8e6dSAndrew Lunn if (ret)
158c0fc8e6dSAndrew Lunn return ret;
159c0fc8e6dSAndrew Lunn
160c0fc8e6dSAndrew Lunn return 0;
1611fcf77c8SAndy Fleming }
1621fcf77c8SAndy Fleming
xgmac_mdio_write_c45(struct mii_bus * bus,int phy_id,int dev_addr,int regnum,u16 value)163c0fc8e6dSAndrew Lunn static int xgmac_mdio_write_c45(struct mii_bus *bus, int phy_id, int dev_addr,
164c0fc8e6dSAndrew Lunn int regnum, u16 value)
165c0fc8e6dSAndrew Lunn {
166c0fc8e6dSAndrew Lunn struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv;
167c0fc8e6dSAndrew Lunn struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
168c0fc8e6dSAndrew Lunn bool endian = priv->is_little_endian;
169c0fc8e6dSAndrew Lunn u32 mdio_ctl, mdio_stat;
170c0fc8e6dSAndrew Lunn int ret;
171c0fc8e6dSAndrew Lunn
172c0fc8e6dSAndrew Lunn mdio_stat = xgmac_read32(®s->mdio_stat, endian);
173c0fc8e6dSAndrew Lunn mdio_stat |= MDIO_STAT_ENC;
174c0fc8e6dSAndrew Lunn
17573ee5442SShaohui Xie xgmac_write32(mdio_stat, ®s->mdio_stat, endian);
1761fcf77c8SAndy Fleming
17773ee5442SShaohui Xie ret = xgmac_wait_until_free(&bus->dev, regs, endian);
1781fcf77c8SAndy Fleming if (ret)
1791fcf77c8SAndy Fleming return ret;
1801fcf77c8SAndy Fleming
1819f35a734STimur Tabi /* Set the port and dev addr */
1821fcf77c8SAndy Fleming mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
18373ee5442SShaohui Xie xgmac_write32(mdio_ctl, ®s->mdio_ctl, endian);
1849f35a734STimur Tabi
1859f35a734STimur Tabi /* Set the register address */
18673ee5442SShaohui Xie xgmac_write32(regnum & 0xffff, ®s->mdio_addr, endian);
1879f35a734STimur Tabi
18873ee5442SShaohui Xie ret = xgmac_wait_until_free(&bus->dev, regs, endian);
1899f35a734STimur Tabi if (ret)
1909f35a734STimur Tabi return ret;
1919f35a734STimur Tabi
1929f35a734STimur Tabi /* Write the value to the register */
19373ee5442SShaohui Xie xgmac_write32(MDIO_DATA(value), ®s->mdio_data, endian);
1949f35a734STimur Tabi
19573ee5442SShaohui Xie ret = xgmac_wait_until_done(&bus->dev, regs, endian);
1969f35a734STimur Tabi if (ret)
1979f35a734STimur Tabi return ret;
1989f35a734STimur Tabi
1999f35a734STimur Tabi return 0;
2009f35a734STimur Tabi }
2019f35a734STimur Tabi
202c0fc8e6dSAndrew Lunn /* Reads from register regnum in the PHY for device dev, returning the value.
2039f35a734STimur Tabi * Clears miimcom first. All PHY configuration has to be done through the
2049f35a734STimur Tabi * TSEC1 MIIM regs.
2059f35a734STimur Tabi */
xgmac_mdio_read_c22(struct mii_bus * bus,int phy_id,int regnum)206c0fc8e6dSAndrew Lunn static int xgmac_mdio_read_c22(struct mii_bus *bus, int phy_id, int regnum)
2079f35a734STimur Tabi {
20873ee5442SShaohui Xie struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv;
20973ee5442SShaohui Xie struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
210c0fc8e6dSAndrew Lunn bool endian = priv->is_little_endian;
211c0fc8e6dSAndrew Lunn u16 dev_addr = regnum & 0x1f;
2126198c722STobias Waldekranz unsigned long flags;
2131fcf77c8SAndy Fleming uint32_t mdio_stat;
2149f35a734STimur Tabi uint32_t mdio_ctl;
2159f35a734STimur Tabi int ret;
2169f35a734STimur Tabi
21773ee5442SShaohui Xie mdio_stat = xgmac_read32(®s->mdio_stat, endian);
218e54bfe9dSShaohui Xie mdio_stat &= ~MDIO_STAT_ENC;
219c0fc8e6dSAndrew Lunn xgmac_write32(mdio_stat, ®s->mdio_stat, endian);
220c0fc8e6dSAndrew Lunn
221c0fc8e6dSAndrew Lunn ret = xgmac_wait_until_free(&bus->dev, regs, endian);
222c0fc8e6dSAndrew Lunn if (ret)
223c0fc8e6dSAndrew Lunn return ret;
224c0fc8e6dSAndrew Lunn
225c0fc8e6dSAndrew Lunn /* Set the Port and Device Addrs */
226c0fc8e6dSAndrew Lunn mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
227c0fc8e6dSAndrew Lunn xgmac_write32(mdio_ctl, ®s->mdio_ctl, endian);
228c0fc8e6dSAndrew Lunn
229c0fc8e6dSAndrew Lunn if (priv->has_a009885)
230c0fc8e6dSAndrew Lunn /* Once the operation completes, i.e. MDIO_STAT_BSY clears, we
231c0fc8e6dSAndrew Lunn * must read back the data register within 16 MDC cycles.
232c0fc8e6dSAndrew Lunn */
233c0fc8e6dSAndrew Lunn local_irq_save(flags);
234c0fc8e6dSAndrew Lunn
235c0fc8e6dSAndrew Lunn /* Initiate the read */
236c0fc8e6dSAndrew Lunn xgmac_write32(mdio_ctl | MDIO_CTL_READ, ®s->mdio_ctl, endian);
237c0fc8e6dSAndrew Lunn
238c0fc8e6dSAndrew Lunn ret = xgmac_wait_until_done(&bus->dev, regs, endian);
239c0fc8e6dSAndrew Lunn if (ret)
240c0fc8e6dSAndrew Lunn goto irq_restore;
241c0fc8e6dSAndrew Lunn
242c0fc8e6dSAndrew Lunn /* Return all Fs if nothing was there */
243c0fc8e6dSAndrew Lunn if ((xgmac_read32(®s->mdio_stat, endian) & MDIO_STAT_RD_ER) &&
244c0fc8e6dSAndrew Lunn !priv->has_a011043) {
245c0fc8e6dSAndrew Lunn dev_dbg(&bus->dev,
246c0fc8e6dSAndrew Lunn "Error while reading PHY%d reg at %d.%d\n",
247c0fc8e6dSAndrew Lunn phy_id, dev_addr, regnum);
248c0fc8e6dSAndrew Lunn ret = 0xffff;
249c0fc8e6dSAndrew Lunn } else {
250c0fc8e6dSAndrew Lunn ret = xgmac_read32(®s->mdio_data, endian) & 0xffff;
251c0fc8e6dSAndrew Lunn dev_dbg(&bus->dev, "read %04x\n", ret);
2521fcf77c8SAndy Fleming }
2531fcf77c8SAndy Fleming
254c0fc8e6dSAndrew Lunn irq_restore:
255c0fc8e6dSAndrew Lunn if (priv->has_a009885)
256c0fc8e6dSAndrew Lunn local_irq_restore(flags);
257c0fc8e6dSAndrew Lunn
258c0fc8e6dSAndrew Lunn return ret;
259c0fc8e6dSAndrew Lunn }
260c0fc8e6dSAndrew Lunn
261c0fc8e6dSAndrew Lunn /* Reads from register regnum in the PHY for device dev, returning the value.
262c0fc8e6dSAndrew Lunn * Clears miimcom first. All PHY configuration has to be done through the
263c0fc8e6dSAndrew Lunn * TSEC1 MIIM regs.
264c0fc8e6dSAndrew Lunn */
xgmac_mdio_read_c45(struct mii_bus * bus,int phy_id,int dev_addr,int regnum)265c0fc8e6dSAndrew Lunn static int xgmac_mdio_read_c45(struct mii_bus *bus, int phy_id, int dev_addr,
266c0fc8e6dSAndrew Lunn int regnum)
267c0fc8e6dSAndrew Lunn {
268c0fc8e6dSAndrew Lunn struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv;
269c0fc8e6dSAndrew Lunn struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
270c0fc8e6dSAndrew Lunn bool endian = priv->is_little_endian;
271c0fc8e6dSAndrew Lunn u32 mdio_stat, mdio_ctl;
272c0fc8e6dSAndrew Lunn unsigned long flags;
273c0fc8e6dSAndrew Lunn int ret;
274c0fc8e6dSAndrew Lunn
275c0fc8e6dSAndrew Lunn mdio_stat = xgmac_read32(®s->mdio_stat, endian);
276c0fc8e6dSAndrew Lunn mdio_stat |= MDIO_STAT_ENC;
277c0fc8e6dSAndrew Lunn
27873ee5442SShaohui Xie xgmac_write32(mdio_stat, ®s->mdio_stat, endian);
2791fcf77c8SAndy Fleming
28073ee5442SShaohui Xie ret = xgmac_wait_until_free(&bus->dev, regs, endian);
2811fcf77c8SAndy Fleming if (ret)
2821fcf77c8SAndy Fleming return ret;
2831fcf77c8SAndy Fleming
2849f35a734STimur Tabi /* Set the Port and Device Addrs */
2859f35a734STimur Tabi mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
28673ee5442SShaohui Xie xgmac_write32(mdio_ctl, ®s->mdio_ctl, endian);
2879f35a734STimur Tabi
2889f35a734STimur Tabi /* Set the register address */
28973ee5442SShaohui Xie xgmac_write32(regnum & 0xffff, ®s->mdio_addr, endian);
2909f35a734STimur Tabi
29173ee5442SShaohui Xie ret = xgmac_wait_until_free(&bus->dev, regs, endian);
2929f35a734STimur Tabi if (ret)
2939f35a734STimur Tabi return ret;
2949f35a734STimur Tabi
2956198c722STobias Waldekranz if (priv->has_a009885)
2966198c722STobias Waldekranz /* Once the operation completes, i.e. MDIO_STAT_BSY clears, we
2976198c722STobias Waldekranz * must read back the data register within 16 MDC cycles.
2986198c722STobias Waldekranz */
2996198c722STobias Waldekranz local_irq_save(flags);
3006198c722STobias Waldekranz
3019f35a734STimur Tabi /* Initiate the read */
30273ee5442SShaohui Xie xgmac_write32(mdio_ctl | MDIO_CTL_READ, ®s->mdio_ctl, endian);
3039f35a734STimur Tabi
30473ee5442SShaohui Xie ret = xgmac_wait_until_done(&bus->dev, regs, endian);
3059f35a734STimur Tabi if (ret)
3066198c722STobias Waldekranz goto irq_restore;
3079f35a734STimur Tabi
3089f35a734STimur Tabi /* Return all Fs if nothing was there */
3091d3ca681SMadalin Bucur if ((xgmac_read32(®s->mdio_stat, endian) & MDIO_STAT_RD_ER) &&
3101d3ca681SMadalin Bucur !priv->has_a011043) {
3111ec8e748SJamie Iles dev_dbg(&bus->dev,
312c011072cSBill Wendling "Error while reading PHY%d reg at %d.%d\n",
31355fd3641SShruti Kanetkar phy_id, dev_addr, regnum);
3146198c722STobias Waldekranz ret = 0xffff;
3156198c722STobias Waldekranz } else {
3166198c722STobias Waldekranz ret = xgmac_read32(®s->mdio_data, endian) & 0xffff;
3176198c722STobias Waldekranz dev_dbg(&bus->dev, "read %04x\n", ret);
3189f35a734STimur Tabi }
3199f35a734STimur Tabi
3206198c722STobias Waldekranz irq_restore:
3216198c722STobias Waldekranz if (priv->has_a009885)
3226198c722STobias Waldekranz local_irq_restore(flags);
3239f35a734STimur Tabi
3246198c722STobias Waldekranz return ret;
3259f35a734STimur Tabi }
3269f35a734STimur Tabi
xgmac_mdio_set_mdc_freq(struct mii_bus * bus)327dd8f467eSTobias Waldekranz static int xgmac_mdio_set_mdc_freq(struct mii_bus *bus)
328dd8f467eSTobias Waldekranz {
329dd8f467eSTobias Waldekranz struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv;
330dd8f467eSTobias Waldekranz struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
331dd8f467eSTobias Waldekranz struct device *dev = bus->parent;
332dd8f467eSTobias Waldekranz u32 mdio_stat, div;
333dd8f467eSTobias Waldekranz
334dd8f467eSTobias Waldekranz if (device_property_read_u32(dev, "clock-frequency", &priv->mdc_freq))
335dd8f467eSTobias Waldekranz return 0;
336dd8f467eSTobias Waldekranz
337dd8f467eSTobias Waldekranz priv->enet_clk = devm_clk_get(dev, NULL);
338dd8f467eSTobias Waldekranz if (IS_ERR(priv->enet_clk)) {
339dd8f467eSTobias Waldekranz dev_err(dev, "Input clock unknown, not changing MDC frequency");
340dd8f467eSTobias Waldekranz return PTR_ERR(priv->enet_clk);
341dd8f467eSTobias Waldekranz }
342dd8f467eSTobias Waldekranz
343dd8f467eSTobias Waldekranz div = ((clk_get_rate(priv->enet_clk) / priv->mdc_freq) - 1) / 2;
344dd8f467eSTobias Waldekranz if (div < 5 || div > 0x1ff) {
34534a79c5dSColin Ian King dev_err(dev, "Requested MDC frequency is out of range, ignoring");
346dd8f467eSTobias Waldekranz return -EINVAL;
347dd8f467eSTobias Waldekranz }
348dd8f467eSTobias Waldekranz
349dd8f467eSTobias Waldekranz mdio_stat = xgmac_read32(®s->mdio_stat, priv->is_little_endian);
350dd8f467eSTobias Waldekranz mdio_stat &= ~MDIO_STAT_CLKDIV(0x1ff);
351dd8f467eSTobias Waldekranz mdio_stat |= MDIO_STAT_CLKDIV(div);
352dd8f467eSTobias Waldekranz xgmac_write32(mdio_stat, ®s->mdio_stat, priv->is_little_endian);
353dd8f467eSTobias Waldekranz return 0;
354dd8f467eSTobias Waldekranz }
355dd8f467eSTobias Waldekranz
xgmac_mdio_set_suppress_preamble(struct mii_bus * bus)356909bea73STobias Waldekranz static void xgmac_mdio_set_suppress_preamble(struct mii_bus *bus)
357909bea73STobias Waldekranz {
358909bea73STobias Waldekranz struct mdio_fsl_priv *priv = (struct mdio_fsl_priv *)bus->priv;
359909bea73STobias Waldekranz struct tgec_mdio_controller __iomem *regs = priv->mdio_base;
360909bea73STobias Waldekranz struct device *dev = bus->parent;
361909bea73STobias Waldekranz u32 mdio_stat;
362909bea73STobias Waldekranz
363909bea73STobias Waldekranz if (!device_property_read_bool(dev, "suppress-preamble"))
364909bea73STobias Waldekranz return;
365909bea73STobias Waldekranz
366909bea73STobias Waldekranz mdio_stat = xgmac_read32(®s->mdio_stat, priv->is_little_endian);
367909bea73STobias Waldekranz mdio_stat |= MDIO_STAT_PRE_DIS;
368909bea73STobias Waldekranz xgmac_write32(mdio_stat, ®s->mdio_stat, priv->is_little_endian);
369909bea73STobias Waldekranz }
370909bea73STobias Waldekranz
xgmac_mdio_probe(struct platform_device * pdev)37133897cc8SBill Pemberton static int xgmac_mdio_probe(struct platform_device *pdev)
3729f35a734STimur Tabi {
373ac53c264SMarcin Wojtas struct fwnode_handle *fwnode;
37473ee5442SShaohui Xie struct mdio_fsl_priv *priv;
37515e7064eSCalvin Johnson struct resource *res;
37615e7064eSCalvin Johnson struct mii_bus *bus;
3779f35a734STimur Tabi int ret;
3789f35a734STimur Tabi
379229f4bb4SCalvin Johnson /* In DPAA-1, MDIO is one of the many FMan sub-devices. The FMan
380229f4bb4SCalvin Johnson * defines a register space that spans a large area, covering all the
381229f4bb4SCalvin Johnson * subdevice areas. Therefore, MDIO cannot claim exclusive access to
382229f4bb4SCalvin Johnson * this register area.
383229f4bb4SCalvin Johnson */
384229f4bb4SCalvin Johnson res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
385229f4bb4SCalvin Johnson if (!res) {
3869f35a734STimur Tabi dev_err(&pdev->dev, "could not obtain address\n");
387229f4bb4SCalvin Johnson return -EINVAL;
3889f35a734STimur Tabi }
3899f35a734STimur Tabi
3901d14eb15STobias Waldekranz bus = devm_mdiobus_alloc_size(&pdev->dev, sizeof(struct mdio_fsl_priv));
3919f35a734STimur Tabi if (!bus)
3929f35a734STimur Tabi return -ENOMEM;
3939f35a734STimur Tabi
3949f35a734STimur Tabi bus->name = "Freescale XGMAC MDIO Bus";
395c0fc8e6dSAndrew Lunn bus->read = xgmac_mdio_read_c22;
396c0fc8e6dSAndrew Lunn bus->write = xgmac_mdio_write_c22;
397c0fc8e6dSAndrew Lunn bus->read_c45 = xgmac_mdio_read_c45;
398c0fc8e6dSAndrew Lunn bus->write_c45 = xgmac_mdio_write_c45;
3999f35a734STimur Tabi bus->parent = &pdev->dev;
400229f4bb4SCalvin Johnson snprintf(bus->id, MII_BUS_ID_SIZE, "%pa", &res->start);
4019f35a734STimur Tabi
40273ee5442SShaohui Xie priv = bus->priv;
4031d14eb15STobias Waldekranz priv->mdio_base = devm_ioremap(&pdev->dev, res->start,
4041d14eb15STobias Waldekranz resource_size(res));
405cc4598cfSWei Yongjun if (!priv->mdio_base)
406cc4598cfSWei Yongjun return -ENOMEM;
4079f35a734STimur Tabi
40815e7064eSCalvin Johnson /* For both ACPI and DT cases, endianness of MDIO controller
40915e7064eSCalvin Johnson * needs to be specified using "little-endian" property.
41015e7064eSCalvin Johnson */
411229f4bb4SCalvin Johnson priv->is_little_endian = device_property_read_bool(&pdev->dev,
41207bf2e11SJulia Lawall "little-endian");
41373ee5442SShaohui Xie
4146198c722STobias Waldekranz priv->has_a009885 = device_property_read_bool(&pdev->dev,
4156198c722STobias Waldekranz "fsl,erratum-a009885");
416229f4bb4SCalvin Johnson priv->has_a011043 = device_property_read_bool(&pdev->dev,
4171d3ca681SMadalin Bucur "fsl,erratum-a011043");
4181d3ca681SMadalin Bucur
419909bea73STobias Waldekranz xgmac_mdio_set_suppress_preamble(bus);
420909bea73STobias Waldekranz
421dd8f467eSTobias Waldekranz ret = xgmac_mdio_set_mdc_freq(bus);
422dd8f467eSTobias Waldekranz if (ret)
423dd8f467eSTobias Waldekranz return ret;
424dd8f467eSTobias Waldekranz
425105b0468Szhaoxiao fwnode = dev_fwnode(&pdev->dev);
426ac53c264SMarcin Wojtas if (is_of_node(fwnode))
427ac53c264SMarcin Wojtas ret = of_mdiobus_register(bus, to_of_node(fwnode));
428ac53c264SMarcin Wojtas else if (is_acpi_node(fwnode))
429ac53c264SMarcin Wojtas ret = acpi_mdiobus_register(bus, fwnode);
430ac53c264SMarcin Wojtas else
431ac53c264SMarcin Wojtas ret = -EINVAL;
4329f35a734STimur Tabi if (ret) {
4339f35a734STimur Tabi dev_err(&pdev->dev, "cannot register MDIO bus\n");
4349f35a734STimur Tabi return ret;
4359f35a734STimur Tabi }
4369f35a734STimur Tabi
4371d14eb15STobias Waldekranz platform_set_drvdata(pdev, bus);
4389f35a734STimur Tabi
4399f35a734STimur Tabi return 0;
4409f35a734STimur Tabi }
4419f35a734STimur Tabi
44294e5a2a8SFabian Frederick static const struct of_device_id xgmac_mdio_match[] = {
4439f35a734STimur Tabi {
4449f35a734STimur Tabi .compatible = "fsl,fman-xmdio",
4459f35a734STimur Tabi },
4461fcf77c8SAndy Fleming {
4471fcf77c8SAndy Fleming .compatible = "fsl,fman-memac-mdio",
4481fcf77c8SAndy Fleming },
4499f35a734STimur Tabi {},
4509f35a734STimur Tabi };
4519f35a734STimur Tabi MODULE_DEVICE_TABLE(of, xgmac_mdio_match);
4529f35a734STimur Tabi
453229f4bb4SCalvin Johnson static const struct acpi_device_id xgmac_acpi_match[] = {
454229f4bb4SCalvin Johnson { "NXP0006" },
455229f4bb4SCalvin Johnson { }
456229f4bb4SCalvin Johnson };
457229f4bb4SCalvin Johnson MODULE_DEVICE_TABLE(acpi, xgmac_acpi_match);
458229f4bb4SCalvin Johnson
4599f35a734STimur Tabi static struct platform_driver xgmac_mdio_driver = {
4609f35a734STimur Tabi .driver = {
4619f35a734STimur Tabi .name = "fsl-fman_xmdio",
4629f35a734STimur Tabi .of_match_table = xgmac_mdio_match,
463229f4bb4SCalvin Johnson .acpi_match_table = xgmac_acpi_match,
4649f35a734STimur Tabi },
4659f35a734STimur Tabi .probe = xgmac_mdio_probe,
4669f35a734STimur Tabi };
4679f35a734STimur Tabi
4689f35a734STimur Tabi module_platform_driver(xgmac_mdio_driver);
4699f35a734STimur Tabi
4709f35a734STimur Tabi MODULE_DESCRIPTION("Freescale QorIQ 10G MDIO Controller");
4719f35a734STimur Tabi MODULE_LICENSE("GPL v2");
472