12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
2ec21e2ecSJeff Kirsher /*
3ec21e2ecSJeff Kirsher * Freescale PowerQUICC Ethernet Driver -- MIIM bus implementation
4ec21e2ecSJeff Kirsher * Provides Bus interface for MIIM regs
5ec21e2ecSJeff Kirsher *
6ec21e2ecSJeff Kirsher * Author: Andy Fleming <afleming@freescale.com>
7ec21e2ecSJeff Kirsher * Modifier: Sandeep Gopalpet <sandeep.kumar@freescale.com>
8ec21e2ecSJeff Kirsher *
9ec21e2ecSJeff Kirsher * Copyright 2002-2004, 2008-2009 Freescale Semiconductor, Inc.
10ec21e2ecSJeff Kirsher *
11ec21e2ecSJeff Kirsher * Based on gianfar_mii.c and ucc_geth_mii.c (Li Yang, Kim Phillips)
12ec21e2ecSJeff Kirsher */
13ec21e2ecSJeff Kirsher
14ec21e2ecSJeff Kirsher #include <linux/kernel.h>
15*3d40aed8SRob Herring #include <linux/platform_device.h>
16ec21e2ecSJeff Kirsher #include <linux/string.h>
17ec21e2ecSJeff Kirsher #include <linux/errno.h>
18ec21e2ecSJeff Kirsher #include <linux/slab.h>
19ec21e2ecSJeff Kirsher #include <linux/delay.h>
20ec21e2ecSJeff Kirsher #include <linux/module.h>
21ec21e2ecSJeff Kirsher #include <linux/mii.h>
22ec21e2ecSJeff Kirsher #include <linux/of_address.h>
23ec21e2ecSJeff Kirsher #include <linux/of_mdio.h>
24afae5ad7STimur Tabi #include <linux/of_device.h>
25ec21e2ecSJeff Kirsher
26ec21e2ecSJeff Kirsher #include <asm/io.h>
279a4cbd53SClaudiu Manoil #if IS_ENABLED(CONFIG_UCC_GETH)
287aa1aa6eSZhao Qiang #include <soc/fsl/qe/ucc.h>
299a4cbd53SClaudiu Manoil #endif
30ec21e2ecSJeff Kirsher
31ec21e2ecSJeff Kirsher #include "gianfar.h"
3219bcd6c6STimur Tabi
3319bcd6c6STimur Tabi #define MIIMIND_BUSY 0x00000001
3419bcd6c6STimur Tabi #define MIIMIND_NOTVALID 0x00000004
3519bcd6c6STimur Tabi #define MIIMCFG_INIT_VALUE 0x00000007
3619bcd6c6STimur Tabi #define MIIMCFG_RESET 0x80000000
3719bcd6c6STimur Tabi
3819bcd6c6STimur Tabi #define MII_READ_COMMAND 0x00000001
3919bcd6c6STimur Tabi
40afae5ad7STimur Tabi struct fsl_pq_mii {
41afae5ad7STimur Tabi u32 miimcfg; /* MII management configuration reg */
42afae5ad7STimur Tabi u32 miimcom; /* MII management command reg */
43afae5ad7STimur Tabi u32 miimadd; /* MII management address reg */
44afae5ad7STimur Tabi u32 miimcon; /* MII management control reg */
45afae5ad7STimur Tabi u32 miimstat; /* MII management status reg */
46afae5ad7STimur Tabi u32 miimind; /* MII management indication reg */
47afae5ad7STimur Tabi };
48afae5ad7STimur Tabi
4919bcd6c6STimur Tabi struct fsl_pq_mdio {
5019bcd6c6STimur Tabi u8 res1[16];
5119bcd6c6STimur Tabi u32 ieventm; /* MDIO Interrupt event register (for etsec2)*/
5219bcd6c6STimur Tabi u32 imaskm; /* MDIO Interrupt mask register (for etsec2)*/
5319bcd6c6STimur Tabi u8 res2[4];
5419bcd6c6STimur Tabi u32 emapm; /* MDIO Event mapping register (for etsec2)*/
5519bcd6c6STimur Tabi u8 res3[1280];
56afae5ad7STimur Tabi struct fsl_pq_mii mii;
5719bcd6c6STimur Tabi u8 res4[28];
5819bcd6c6STimur Tabi u32 utbipar; /* TBI phy address reg (only on UCC) */
5919bcd6c6STimur Tabi u8 res5[2728];
6019bcd6c6STimur Tabi } __packed;
61ec21e2ecSJeff Kirsher
6259399c59STimur Tabi /* Number of microseconds to wait for an MII register to respond */
6359399c59STimur Tabi #define MII_TIMEOUT 1000
6459399c59STimur Tabi
65ec21e2ecSJeff Kirsher struct fsl_pq_mdio_priv {
66ec21e2ecSJeff Kirsher void __iomem *map;
67afae5ad7STimur Tabi struct fsl_pq_mii __iomem *regs;
68afae5ad7STimur Tabi };
69afae5ad7STimur Tabi
70afae5ad7STimur Tabi /*
71afae5ad7STimur Tabi * Per-device-type data. Each type of device tree node that we support gets
72afae5ad7STimur Tabi * one of these.
73afae5ad7STimur Tabi *
74afae5ad7STimur Tabi * @mii_offset: the offset of the MII registers within the memory map of the
75afae5ad7STimur Tabi * node. Some nodes define only the MII registers, and some define the whole
76afae5ad7STimur Tabi * MAC (which includes the MII registers).
77afae5ad7STimur Tabi *
78afae5ad7STimur Tabi * @get_tbipa: determines the address of the TBIPA register
79afae5ad7STimur Tabi *
80afae5ad7STimur Tabi * @ucc_configure: a special function for extra QE configuration
81afae5ad7STimur Tabi */
82afae5ad7STimur Tabi struct fsl_pq_mdio_data {
83afae5ad7STimur Tabi unsigned int mii_offset; /* offset of the MII registers */
84afae5ad7STimur Tabi uint32_t __iomem * (*get_tbipa)(void __iomem *p);
85afae5ad7STimur Tabi void (*ucc_configure)(phys_addr_t start, phys_addr_t end);
86ec21e2ecSJeff Kirsher };
87ec21e2ecSJeff Kirsher
88ec21e2ecSJeff Kirsher /*
8969cfb419STimur Tabi * Write value to the PHY at mii_id at register regnum, on the bus attached
9069cfb419STimur Tabi * to the local interface, which may be different from the generic mdio bus
9169cfb419STimur Tabi * (tied to a single interface), waiting until the write is done before
9269cfb419STimur Tabi * returning. This is helpful in programming interfaces like the TBI which
9369cfb419STimur Tabi * control interfaces like onchip SERDES and are always tied to the local
9469cfb419STimur Tabi * mdio pins, which may not be the same as system mdio bus, used for
95ec21e2ecSJeff Kirsher * controlling the external PHYs, for example.
96ec21e2ecSJeff Kirsher */
fsl_pq_mdio_write(struct mii_bus * bus,int mii_id,int regnum,u16 value)9769cfb419STimur Tabi static int fsl_pq_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
9869cfb419STimur Tabi u16 value)
99ec21e2ecSJeff Kirsher {
10069cfb419STimur Tabi struct fsl_pq_mdio_priv *priv = bus->priv;
101afae5ad7STimur Tabi struct fsl_pq_mii __iomem *regs = priv->regs;
102e4b081f5SClaudiu Manoil unsigned int timeout;
10359399c59STimur Tabi
104ec21e2ecSJeff Kirsher /* Set the PHY address and the register address we want to write */
105f5bbd262SClaudiu Manoil iowrite32be((mii_id << 8) | regnum, ®s->miimadd);
106ec21e2ecSJeff Kirsher
107ec21e2ecSJeff Kirsher /* Write out the value we want */
108f5bbd262SClaudiu Manoil iowrite32be(value, ®s->miimcon);
109ec21e2ecSJeff Kirsher
110ec21e2ecSJeff Kirsher /* Wait for the transaction to finish */
111e4b081f5SClaudiu Manoil timeout = MII_TIMEOUT;
112e4b081f5SClaudiu Manoil while ((ioread32be(®s->miimind) & MIIMIND_BUSY) && timeout) {
113e4b081f5SClaudiu Manoil cpu_relax();
114e4b081f5SClaudiu Manoil timeout--;
115e4b081f5SClaudiu Manoil }
116ec21e2ecSJeff Kirsher
117e4b081f5SClaudiu Manoil return timeout ? 0 : -ETIMEDOUT;
118ec21e2ecSJeff Kirsher }
119ec21e2ecSJeff Kirsher
120ec21e2ecSJeff Kirsher /*
12169cfb419STimur Tabi * Read the bus for PHY at addr mii_id, register regnum, and return the value.
12269cfb419STimur Tabi * Clears miimcom first.
12369cfb419STimur Tabi *
12469cfb419STimur Tabi * All PHY operation done on the bus attached to the local interface, which
12569cfb419STimur Tabi * may be different from the generic mdio bus. This is helpful in programming
12669cfb419STimur Tabi * interfaces like the TBI which, in turn, control interfaces like on-chip
12769cfb419STimur Tabi * SERDES and are always tied to the local mdio pins, which may not be the
128ec21e2ecSJeff Kirsher * same as system mdio bus, used for controlling the external PHYs, for eg.
129ec21e2ecSJeff Kirsher */
fsl_pq_mdio_read(struct mii_bus * bus,int mii_id,int regnum)13069cfb419STimur Tabi static int fsl_pq_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
131ec21e2ecSJeff Kirsher {
13269cfb419STimur Tabi struct fsl_pq_mdio_priv *priv = bus->priv;
133afae5ad7STimur Tabi struct fsl_pq_mii __iomem *regs = priv->regs;
134e4b081f5SClaudiu Manoil unsigned int timeout;
13569cfb419STimur Tabi u16 value;
136ec21e2ecSJeff Kirsher
137ec21e2ecSJeff Kirsher /* Set the PHY address and the register address we want to read */
138f5bbd262SClaudiu Manoil iowrite32be((mii_id << 8) | regnum, ®s->miimadd);
139ec21e2ecSJeff Kirsher
140ec21e2ecSJeff Kirsher /* Clear miimcom, and then initiate a read */
141f5bbd262SClaudiu Manoil iowrite32be(0, ®s->miimcom);
142f5bbd262SClaudiu Manoil iowrite32be(MII_READ_COMMAND, ®s->miimcom);
143ec21e2ecSJeff Kirsher
14459399c59STimur Tabi /* Wait for the transaction to finish, normally less than 100us */
145e4b081f5SClaudiu Manoil timeout = MII_TIMEOUT;
146e4b081f5SClaudiu Manoil while ((ioread32be(®s->miimind) &
147e4b081f5SClaudiu Manoil (MIIMIND_NOTVALID | MIIMIND_BUSY)) && timeout) {
148e4b081f5SClaudiu Manoil cpu_relax();
149e4b081f5SClaudiu Manoil timeout--;
150e4b081f5SClaudiu Manoil }
151e4b081f5SClaudiu Manoil
152e4b081f5SClaudiu Manoil if (!timeout)
15359399c59STimur Tabi return -ETIMEDOUT;
154ec21e2ecSJeff Kirsher
155ec21e2ecSJeff Kirsher /* Grab the value of the register from miimstat */
156f5bbd262SClaudiu Manoil value = ioread32be(®s->miimstat);
157ec21e2ecSJeff Kirsher
158afae5ad7STimur Tabi dev_dbg(&bus->dev, "read %04x from address %x/%x\n", value, mii_id, regnum);
159ec21e2ecSJeff Kirsher return value;
160ec21e2ecSJeff Kirsher }
161ec21e2ecSJeff Kirsher
162ec21e2ecSJeff Kirsher /* Reset the MIIM registers, and wait for the bus to free */
fsl_pq_mdio_reset(struct mii_bus * bus)163ec21e2ecSJeff Kirsher static int fsl_pq_mdio_reset(struct mii_bus *bus)
164ec21e2ecSJeff Kirsher {
16569cfb419STimur Tabi struct fsl_pq_mdio_priv *priv = bus->priv;
166afae5ad7STimur Tabi struct fsl_pq_mii __iomem *regs = priv->regs;
167e4b081f5SClaudiu Manoil unsigned int timeout;
168ec21e2ecSJeff Kirsher
169ec21e2ecSJeff Kirsher mutex_lock(&bus->mdio_lock);
170ec21e2ecSJeff Kirsher
171ec21e2ecSJeff Kirsher /* Reset the management interface */
172f5bbd262SClaudiu Manoil iowrite32be(MIIMCFG_RESET, ®s->miimcfg);
173ec21e2ecSJeff Kirsher
174ec21e2ecSJeff Kirsher /* Setup the MII Mgmt clock speed */
175f5bbd262SClaudiu Manoil iowrite32be(MIIMCFG_INIT_VALUE, ®s->miimcfg);
176ec21e2ecSJeff Kirsher
177ec21e2ecSJeff Kirsher /* Wait until the bus is free */
178e4b081f5SClaudiu Manoil timeout = MII_TIMEOUT;
179e4b081f5SClaudiu Manoil while ((ioread32be(®s->miimind) & MIIMIND_BUSY) && timeout) {
180e4b081f5SClaudiu Manoil cpu_relax();
181e4b081f5SClaudiu Manoil timeout--;
182e4b081f5SClaudiu Manoil }
183ec21e2ecSJeff Kirsher
184ec21e2ecSJeff Kirsher mutex_unlock(&bus->mdio_lock);
185ec21e2ecSJeff Kirsher
186e4b081f5SClaudiu Manoil if (!timeout) {
1875078ac79STimur Tabi dev_err(&bus->dev, "timeout waiting for MII bus\n");
188ec21e2ecSJeff Kirsher return -EBUSY;
189ec21e2ecSJeff Kirsher }
190ec21e2ecSJeff Kirsher
191ec21e2ecSJeff Kirsher return 0;
192ec21e2ecSJeff Kirsher }
193ec21e2ecSJeff Kirsher
194504e76e5SJavier Martinez Canillas #if IS_ENABLED(CONFIG_GIANFAR)
195ec21e2ecSJeff Kirsher /*
1963bb35ac4SGerlando Falauto * Return the TBIPA address, starting from the address
1973bb35ac4SGerlando Falauto * of the mapped GFAR MDIO registers (struct gfar)
198ec21e2ecSJeff Kirsher * This is mildly evil, but so is our hardware for doing this.
199ec21e2ecSJeff Kirsher * Also, we have to cast back to struct gfar because of
200ec21e2ecSJeff Kirsher * definition weirdness done in gianfar.h.
201ec21e2ecSJeff Kirsher */
get_gfar_tbipa_from_mdio(void __iomem * p)2023bb35ac4SGerlando Falauto static uint32_t __iomem *get_gfar_tbipa_from_mdio(void __iomem *p)
203afae5ad7STimur Tabi {
204afae5ad7STimur Tabi struct gfar __iomem *enet_regs = p;
205afae5ad7STimur Tabi
206ec21e2ecSJeff Kirsher return &enet_regs->tbipa;
207afae5ad7STimur Tabi }
208afae5ad7STimur Tabi
209afae5ad7STimur Tabi /*
2103bb35ac4SGerlando Falauto * Return the TBIPA address, starting from the address
2113bb35ac4SGerlando Falauto * of the mapped GFAR MII registers (gfar_mii_regs[] within struct gfar)
2123bb35ac4SGerlando Falauto */
get_gfar_tbipa_from_mii(void __iomem * p)2133bb35ac4SGerlando Falauto static uint32_t __iomem *get_gfar_tbipa_from_mii(void __iomem *p)
2143bb35ac4SGerlando Falauto {
2153bb35ac4SGerlando Falauto return get_gfar_tbipa_from_mdio(container_of(p, struct gfar, gfar_mii_regs));
2163bb35ac4SGerlando Falauto }
2173bb35ac4SGerlando Falauto
2183bb35ac4SGerlando Falauto /*
219afae5ad7STimur Tabi * Return the TBIPAR address for an eTSEC2 node
220afae5ad7STimur Tabi */
get_etsec_tbipa(void __iomem * p)221afae5ad7STimur Tabi static uint32_t __iomem *get_etsec_tbipa(void __iomem *p)
222afae5ad7STimur Tabi {
223afae5ad7STimur Tabi return p;
224ec21e2ecSJeff Kirsher }
225ec21e2ecSJeff Kirsher #endif
226afae5ad7STimur Tabi
227504e76e5SJavier Martinez Canillas #if IS_ENABLED(CONFIG_UCC_GETH)
228afae5ad7STimur Tabi /*
2293bb35ac4SGerlando Falauto * Return the TBIPAR address for a QE MDIO node, starting from the address
2303bb35ac4SGerlando Falauto * of the mapped MII registers (struct fsl_pq_mii)
231afae5ad7STimur Tabi */
get_ucc_tbipa(void __iomem * p)232afae5ad7STimur Tabi static uint32_t __iomem *get_ucc_tbipa(void __iomem *p)
233afae5ad7STimur Tabi {
2343bb35ac4SGerlando Falauto struct fsl_pq_mdio __iomem *mdio = container_of(p, struct fsl_pq_mdio, mii);
235afae5ad7STimur Tabi
236afae5ad7STimur Tabi return &mdio->utbipar;
237952c5ca1SAndy Fleming }
238ec21e2ecSJeff Kirsher
239afae5ad7STimur Tabi /*
240afae5ad7STimur Tabi * Find the UCC node that controls the given MDIO node
241afae5ad7STimur Tabi *
242afae5ad7STimur Tabi * For some reason, the QE MDIO nodes are not children of the UCC devices
243afae5ad7STimur Tabi * that control them. Therefore, we need to scan all UCC nodes looking for
244afae5ad7STimur Tabi * the one that encompases the given MDIO node. We do this by comparing
245afae5ad7STimur Tabi * physical addresses. The 'start' and 'end' addresses of the MDIO node are
246afae5ad7STimur Tabi * passed, and the correct UCC node will cover the entire address range.
247afae5ad7STimur Tabi *
248afae5ad7STimur Tabi * This assumes that there is only one QE MDIO node in the entire device tree.
249afae5ad7STimur Tabi */
ucc_configure(phys_addr_t start,phys_addr_t end)250afae5ad7STimur Tabi static void ucc_configure(phys_addr_t start, phys_addr_t end)
251ec21e2ecSJeff Kirsher {
252afae5ad7STimur Tabi static bool found_mii_master;
253ec21e2ecSJeff Kirsher struct device_node *np = NULL;
254afae5ad7STimur Tabi
255afae5ad7STimur Tabi if (found_mii_master)
256afae5ad7STimur Tabi return;
257ec21e2ecSJeff Kirsher
258ec21e2ecSJeff Kirsher for_each_compatible_node(np, NULL, "ucc_geth") {
259afae5ad7STimur Tabi struct resource res;
260afae5ad7STimur Tabi const uint32_t *iprop;
261afae5ad7STimur Tabi uint32_t id;
262afae5ad7STimur Tabi int ret;
263ec21e2ecSJeff Kirsher
264afae5ad7STimur Tabi ret = of_address_to_resource(np, 0, &res);
265afae5ad7STimur Tabi if (ret < 0) {
266f7ce9103SRob Herring pr_debug("fsl-pq-mdio: no address range in node %pOF\n",
267f7ce9103SRob Herring np);
268ec21e2ecSJeff Kirsher continue;
269afae5ad7STimur Tabi }
270ec21e2ecSJeff Kirsher
271ec21e2ecSJeff Kirsher /* if our mdio regs fall within this UCC regs range */
272afae5ad7STimur Tabi if ((start < res.start) || (end > res.end))
273afae5ad7STimur Tabi continue;
274ec21e2ecSJeff Kirsher
275afae5ad7STimur Tabi iprop = of_get_property(np, "cell-index", NULL);
276afae5ad7STimur Tabi if (!iprop) {
277afae5ad7STimur Tabi iprop = of_get_property(np, "device-id", NULL);
278afae5ad7STimur Tabi if (!iprop) {
279f7ce9103SRob Herring pr_debug("fsl-pq-mdio: no UCC ID in node %pOF\n",
280f7ce9103SRob Herring np);
281afae5ad7STimur Tabi continue;
282afae5ad7STimur Tabi }
283afae5ad7STimur Tabi }
284afae5ad7STimur Tabi
285afae5ad7STimur Tabi id = be32_to_cpup(iprop);
286afae5ad7STimur Tabi
287afae5ad7STimur Tabi /*
288afae5ad7STimur Tabi * cell-index and device-id for QE nodes are
289afae5ad7STimur Tabi * numbered from 1, not 0.
290afae5ad7STimur Tabi */
291afae5ad7STimur Tabi if (ucc_set_qe_mux_mii_mng(id - 1) < 0) {
292f7ce9103SRob Herring pr_debug("fsl-pq-mdio: invalid UCC ID in node %pOF\n",
293f7ce9103SRob Herring np);
294ec21e2ecSJeff Kirsher continue;
295ec21e2ecSJeff Kirsher }
296ec21e2ecSJeff Kirsher
297afae5ad7STimur Tabi pr_debug("fsl-pq-mdio: setting node UCC%u to MII master\n", id);
298afae5ad7STimur Tabi found_mii_master = true;
299ec21e2ecSJeff Kirsher }
300ec21e2ecSJeff Kirsher }
301ec21e2ecSJeff Kirsher
302ec21e2ecSJeff Kirsher #endif
303afae5ad7STimur Tabi
30494e5a2a8SFabian Frederick static const struct of_device_id fsl_pq_mdio_match[] = {
305504e76e5SJavier Martinez Canillas #if IS_ENABLED(CONFIG_GIANFAR)
306afae5ad7STimur Tabi {
307afae5ad7STimur Tabi .compatible = "fsl,gianfar-tbi",
308afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) {
309afae5ad7STimur Tabi .mii_offset = 0,
3103bb35ac4SGerlando Falauto .get_tbipa = get_gfar_tbipa_from_mii,
311afae5ad7STimur Tabi },
312afae5ad7STimur Tabi },
313afae5ad7STimur Tabi {
314afae5ad7STimur Tabi .compatible = "fsl,gianfar-mdio",
315afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) {
316afae5ad7STimur Tabi .mii_offset = 0,
3173bb35ac4SGerlando Falauto .get_tbipa = get_gfar_tbipa_from_mii,
318afae5ad7STimur Tabi },
319afae5ad7STimur Tabi },
320afae5ad7STimur Tabi {
321afae5ad7STimur Tabi .type = "mdio",
322afae5ad7STimur Tabi .compatible = "gianfar",
323afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) {
324afae5ad7STimur Tabi .mii_offset = offsetof(struct fsl_pq_mdio, mii),
3253bb35ac4SGerlando Falauto .get_tbipa = get_gfar_tbipa_from_mdio,
326afae5ad7STimur Tabi },
327afae5ad7STimur Tabi },
328afae5ad7STimur Tabi {
329afae5ad7STimur Tabi .compatible = "fsl,etsec2-tbi",
330afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) {
331afae5ad7STimur Tabi .mii_offset = offsetof(struct fsl_pq_mdio, mii),
332afae5ad7STimur Tabi .get_tbipa = get_etsec_tbipa,
333afae5ad7STimur Tabi },
334afae5ad7STimur Tabi },
335afae5ad7STimur Tabi {
336afae5ad7STimur Tabi .compatible = "fsl,etsec2-mdio",
337afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) {
338afae5ad7STimur Tabi .mii_offset = offsetof(struct fsl_pq_mdio, mii),
339afae5ad7STimur Tabi .get_tbipa = get_etsec_tbipa,
340afae5ad7STimur Tabi },
341afae5ad7STimur Tabi },
342afae5ad7STimur Tabi #endif
343504e76e5SJavier Martinez Canillas #if IS_ENABLED(CONFIG_UCC_GETH)
344afae5ad7STimur Tabi {
345afae5ad7STimur Tabi .compatible = "fsl,ucc-mdio",
346afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) {
347afae5ad7STimur Tabi .mii_offset = 0,
348afae5ad7STimur Tabi .get_tbipa = get_ucc_tbipa,
349afae5ad7STimur Tabi .ucc_configure = ucc_configure,
350afae5ad7STimur Tabi },
351afae5ad7STimur Tabi },
352afae5ad7STimur Tabi {
353afae5ad7STimur Tabi /* Legacy UCC MDIO node */
354afae5ad7STimur Tabi .type = "mdio",
355afae5ad7STimur Tabi .compatible = "ucc_geth_phy",
356afae5ad7STimur Tabi .data = &(struct fsl_pq_mdio_data) {
357afae5ad7STimur Tabi .mii_offset = 0,
358afae5ad7STimur Tabi .get_tbipa = get_ucc_tbipa,
359afae5ad7STimur Tabi .ucc_configure = ucc_configure,
360afae5ad7STimur Tabi },
361afae5ad7STimur Tabi },
362afae5ad7STimur Tabi #endif
363761743ebSTimur Tabi /* No Kconfig option for Fman support yet */
364761743ebSTimur Tabi {
365761743ebSTimur Tabi .compatible = "fsl,fman-mdio",
366761743ebSTimur Tabi .data = &(struct fsl_pq_mdio_data) {
367761743ebSTimur Tabi .mii_offset = 0,
368761743ebSTimur Tabi /* Fman TBI operations are handled elsewhere */
369761743ebSTimur Tabi },
370761743ebSTimur Tabi },
371761743ebSTimur Tabi
372afae5ad7STimur Tabi {},
373afae5ad7STimur Tabi };
374afae5ad7STimur Tabi MODULE_DEVICE_TABLE(of, fsl_pq_mdio_match);
375ec21e2ecSJeff Kirsher
set_tbipa(const u32 tbipa_val,struct platform_device * pdev,uint32_t __iomem * (* get_tbipa)(void __iomem *),void __iomem * reg_map,struct resource * reg_res)37621481189SEsben Haabendal static void set_tbipa(const u32 tbipa_val, struct platform_device *pdev,
37721481189SEsben Haabendal uint32_t __iomem * (*get_tbipa)(void __iomem *),
37821481189SEsben Haabendal void __iomem *reg_map, struct resource *reg_res)
37921481189SEsben Haabendal {
38021481189SEsben Haabendal struct device_node *np = pdev->dev.of_node;
38121481189SEsben Haabendal uint32_t __iomem *tbipa;
38221481189SEsben Haabendal bool tbipa_mapped;
38321481189SEsben Haabendal
38421481189SEsben Haabendal tbipa = of_iomap(np, 1);
38521481189SEsben Haabendal if (tbipa) {
38621481189SEsben Haabendal tbipa_mapped = true;
38721481189SEsben Haabendal } else {
38821481189SEsben Haabendal tbipa_mapped = false;
38921481189SEsben Haabendal tbipa = (*get_tbipa)(reg_map);
39021481189SEsben Haabendal
39121481189SEsben Haabendal /*
39221481189SEsben Haabendal * Add consistency check to make sure TBI is contained within
39321481189SEsben Haabendal * the mapped range (not because we would get a segfault,
39421481189SEsben Haabendal * rather to catch bugs in computing TBI address). Print error
39521481189SEsben Haabendal * message but continue anyway.
39621481189SEsben Haabendal */
39721481189SEsben Haabendal if ((void *)tbipa > reg_map + resource_size(reg_res) - 4)
39821481189SEsben Haabendal dev_err(&pdev->dev, "invalid register map (should be at least 0x%04zx to contain TBI address)\n",
39921481189SEsben Haabendal ((void *)tbipa - reg_map) + 4);
40021481189SEsben Haabendal }
40121481189SEsben Haabendal
40221481189SEsben Haabendal iowrite32be(be32_to_cpu(tbipa_val), tbipa);
40321481189SEsben Haabendal
40421481189SEsben Haabendal if (tbipa_mapped)
40521481189SEsben Haabendal iounmap(tbipa);
40621481189SEsben Haabendal }
40721481189SEsben Haabendal
fsl_pq_mdio_probe(struct platform_device * pdev)4085078ac79STimur Tabi static int fsl_pq_mdio_probe(struct platform_device *pdev)
409ec21e2ecSJeff Kirsher {
410afae5ad7STimur Tabi const struct of_device_id *id =
411afae5ad7STimur Tabi of_match_device(fsl_pq_mdio_match, &pdev->dev);
41206d2d643SGustavo A. R. Silva const struct fsl_pq_mdio_data *data;
4135078ac79STimur Tabi struct device_node *np = pdev->dev.of_node;
414afae5ad7STimur Tabi struct resource res;
415ec21e2ecSJeff Kirsher struct device_node *tbi;
416ec21e2ecSJeff Kirsher struct fsl_pq_mdio_priv *priv;
417ec21e2ecSJeff Kirsher struct mii_bus *new_bus;
418ec21e2ecSJeff Kirsher int err;
419ec21e2ecSJeff Kirsher
42006d2d643SGustavo A. R. Silva if (!id) {
42106d2d643SGustavo A. R. Silva dev_err(&pdev->dev, "Failed to match device\n");
42206d2d643SGustavo A. R. Silva return -ENODEV;
42306d2d643SGustavo A. R. Silva }
42406d2d643SGustavo A. R. Silva
42506d2d643SGustavo A. R. Silva data = id->data;
42606d2d643SGustavo A. R. Silva
427afae5ad7STimur Tabi dev_dbg(&pdev->dev, "found %s compatible node\n", id->compatible);
428afae5ad7STimur Tabi
429dd3b8a32STimur Tabi new_bus = mdiobus_alloc_size(sizeof(*priv));
430dd3b8a32STimur Tabi if (!new_bus)
431ec21e2ecSJeff Kirsher return -ENOMEM;
432ec21e2ecSJeff Kirsher
433dd3b8a32STimur Tabi priv = new_bus->priv;
434af89784eSZheng Yongjun new_bus->name = "Freescale PowerQUICC MII Bus";
4355078ac79STimur Tabi new_bus->read = &fsl_pq_mdio_read;
4365078ac79STimur Tabi new_bus->write = &fsl_pq_mdio_write;
4375078ac79STimur Tabi new_bus->reset = &fsl_pq_mdio_reset;
438ec21e2ecSJeff Kirsher
439afae5ad7STimur Tabi err = of_address_to_resource(np, 0, &res);
440afae5ad7STimur Tabi if (err < 0) {
441afae5ad7STimur Tabi dev_err(&pdev->dev, "could not obtain address information\n");
442dd3b8a32STimur Tabi goto error;
443ec21e2ecSJeff Kirsher }
444ec21e2ecSJeff Kirsher
44521c328dcSRob Herring snprintf(new_bus->id, MII_BUS_ID_SIZE, "%pOFn@%llx", np,
446afae5ad7STimur Tabi (unsigned long long)res.start);
44769cfb419STimur Tabi
448afae5ad7STimur Tabi priv->map = of_iomap(np, 0);
449afae5ad7STimur Tabi if (!priv->map) {
450ec21e2ecSJeff Kirsher err = -ENOMEM;
451dd3b8a32STimur Tabi goto error;
452ec21e2ecSJeff Kirsher }
453ec21e2ecSJeff Kirsher
454afae5ad7STimur Tabi /*
455afae5ad7STimur Tabi * Some device tree nodes represent only the MII registers, and
456afae5ad7STimur Tabi * others represent the MAC and MII registers. The 'mii_offset' field
457afae5ad7STimur Tabi * contains the offset of the MII registers inside the mapped register
458afae5ad7STimur Tabi * space.
459afae5ad7STimur Tabi */
460afae5ad7STimur Tabi if (data->mii_offset > resource_size(&res)) {
461afae5ad7STimur Tabi dev_err(&pdev->dev, "invalid register map\n");
462afae5ad7STimur Tabi err = -EINVAL;
463dd3b8a32STimur Tabi goto error;
464afae5ad7STimur Tabi }
465afae5ad7STimur Tabi priv->regs = priv->map + data->mii_offset;
466ec21e2ecSJeff Kirsher
4675078ac79STimur Tabi new_bus->parent = &pdev->dev;
468a0e18600SLibo Chen platform_set_drvdata(pdev, new_bus);
469ec21e2ecSJeff Kirsher
470afae5ad7STimur Tabi if (data->get_tbipa) {
471ec21e2ecSJeff Kirsher for_each_child_of_node(np, tbi) {
472d7b4a2f2SRob Herring if (of_node_is_type(tbi, "tbi-phy")) {
473f7ce9103SRob Herring dev_dbg(&pdev->dev, "found TBI PHY node %pOFP\n",
474f7ce9103SRob Herring tbi);
475ec21e2ecSJeff Kirsher break;
476ec21e2ecSJeff Kirsher }
477afae5ad7STimur Tabi }
478ec21e2ecSJeff Kirsher
479ec21e2ecSJeff Kirsher if (tbi) {
480ec21e2ecSJeff Kirsher const u32 *prop = of_get_property(tbi, "reg", NULL);
481afae5ad7STimur Tabi if (!prop) {
482afae5ad7STimur Tabi dev_err(&pdev->dev,
483f7ce9103SRob Herring "missing 'reg' property in node %pOF\n",
484f7ce9103SRob Herring tbi);
485ec21e2ecSJeff Kirsher err = -EBUSY;
486afae5ad7STimur Tabi goto error;
487afae5ad7STimur Tabi }
48821481189SEsben Haabendal set_tbipa(*prop, pdev,
48921481189SEsben Haabendal data->get_tbipa, priv->map, &res);
490c3e072f8SBaruch Siach }
491464b57daSKenth Eriksson }
492ec21e2ecSJeff Kirsher
493afae5ad7STimur Tabi if (data->ucc_configure)
494afae5ad7STimur Tabi data->ucc_configure(res.start, res.end);
495afae5ad7STimur Tabi
496ec21e2ecSJeff Kirsher err = of_mdiobus_register(new_bus, np);
497ec21e2ecSJeff Kirsher if (err) {
4985078ac79STimur Tabi dev_err(&pdev->dev, "cannot register %s as MDIO bus\n",
499ec21e2ecSJeff Kirsher new_bus->name);
500dd3b8a32STimur Tabi goto error;
501ec21e2ecSJeff Kirsher }
502ec21e2ecSJeff Kirsher
503ec21e2ecSJeff Kirsher return 0;
504ec21e2ecSJeff Kirsher
505dd3b8a32STimur Tabi error:
506dd3b8a32STimur Tabi if (priv->map)
507ec21e2ecSJeff Kirsher iounmap(priv->map);
508dd3b8a32STimur Tabi
509ec21e2ecSJeff Kirsher kfree(new_bus);
510dd3b8a32STimur Tabi
511ec21e2ecSJeff Kirsher return err;
512ec21e2ecSJeff Kirsher }
513ec21e2ecSJeff Kirsher
514ec21e2ecSJeff Kirsher
fsl_pq_mdio_remove(struct platform_device * pdev)515f8336355SUwe Kleine-König static void fsl_pq_mdio_remove(struct platform_device *pdev)
516ec21e2ecSJeff Kirsher {
5175078ac79STimur Tabi struct device *device = &pdev->dev;
518ec21e2ecSJeff Kirsher struct mii_bus *bus = dev_get_drvdata(device);
519ec21e2ecSJeff Kirsher struct fsl_pq_mdio_priv *priv = bus->priv;
520ec21e2ecSJeff Kirsher
521ec21e2ecSJeff Kirsher mdiobus_unregister(bus);
522ec21e2ecSJeff Kirsher
523ec21e2ecSJeff Kirsher iounmap(priv->map);
524ec21e2ecSJeff Kirsher mdiobus_free(bus);
525ec21e2ecSJeff Kirsher }
526ec21e2ecSJeff Kirsher
527ec21e2ecSJeff Kirsher static struct platform_driver fsl_pq_mdio_driver = {
528ec21e2ecSJeff Kirsher .driver = {
529ec21e2ecSJeff Kirsher .name = "fsl-pq_mdio",
530ec21e2ecSJeff Kirsher .of_match_table = fsl_pq_mdio_match,
531ec21e2ecSJeff Kirsher },
532ec21e2ecSJeff Kirsher .probe = fsl_pq_mdio_probe,
533f8336355SUwe Kleine-König .remove_new = fsl_pq_mdio_remove,
534ec21e2ecSJeff Kirsher };
535ec21e2ecSJeff Kirsher
536db62f684SAxel Lin module_platform_driver(fsl_pq_mdio_driver);
537ec21e2ecSJeff Kirsher
538ec21e2ecSJeff Kirsher MODULE_LICENSE("GPL");
539