183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
28ee443b8SBin Meng /*
38ee443b8SBin Meng * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
48ee443b8SBin Meng *
58ee443b8SBin Meng * Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver
68ee443b8SBin Meng */
78ee443b8SBin Meng
88ee443b8SBin Meng #include <common.h>
9ca19a793SBin Meng #include <dm.h>
108ee443b8SBin Meng #include <errno.h>
118ee443b8SBin Meng #include <asm/io.h>
128ee443b8SBin Meng #include <pci.h>
138ee443b8SBin Meng #include <miiphy.h>
148ee443b8SBin Meng #include "pch_gbe.h"
158ee443b8SBin Meng
168ee443b8SBin Meng #if !defined(CONFIG_PHYLIB)
178ee443b8SBin Meng # error "PCH Gigabit Ethernet driver requires PHYLIB - missing CONFIG_PHYLIB"
188ee443b8SBin Meng #endif
198ee443b8SBin Meng
208ee443b8SBin Meng static struct pci_device_id supported[] = {
21ca19a793SBin Meng { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_GBE) },
228ee443b8SBin Meng { }
238ee443b8SBin Meng };
248ee443b8SBin Meng
pch_gbe_mac_read(struct pch_gbe_regs * mac_regs,u8 * addr)258ee443b8SBin Meng static void pch_gbe_mac_read(struct pch_gbe_regs *mac_regs, u8 *addr)
268ee443b8SBin Meng {
278ee443b8SBin Meng u32 macid_hi, macid_lo;
288ee443b8SBin Meng
298ee443b8SBin Meng macid_hi = readl(&mac_regs->mac_adr[0].high);
308ee443b8SBin Meng macid_lo = readl(&mac_regs->mac_adr[0].low) & 0xffff;
318ee443b8SBin Meng debug("pch_gbe: macid_hi %#x macid_lo %#x\n", macid_hi, macid_lo);
328ee443b8SBin Meng
338ee443b8SBin Meng addr[0] = (u8)(macid_hi & 0xff);
348ee443b8SBin Meng addr[1] = (u8)((macid_hi >> 8) & 0xff);
358ee443b8SBin Meng addr[2] = (u8)((macid_hi >> 16) & 0xff);
368ee443b8SBin Meng addr[3] = (u8)((macid_hi >> 24) & 0xff);
378ee443b8SBin Meng addr[4] = (u8)(macid_lo & 0xff);
388ee443b8SBin Meng addr[5] = (u8)((macid_lo >> 8) & 0xff);
398ee443b8SBin Meng }
408ee443b8SBin Meng
pch_gbe_mac_write(struct pch_gbe_regs * mac_regs,u8 * addr)418ee443b8SBin Meng static int pch_gbe_mac_write(struct pch_gbe_regs *mac_regs, u8 *addr)
428ee443b8SBin Meng {
438ee443b8SBin Meng u32 macid_hi, macid_lo;
448ee443b8SBin Meng ulong start;
458ee443b8SBin Meng
468ee443b8SBin Meng macid_hi = addr[0] + (addr[1] << 8) + (addr[2] << 16) + (addr[3] << 24);
478ee443b8SBin Meng macid_lo = addr[4] + (addr[5] << 8);
488ee443b8SBin Meng
498ee443b8SBin Meng writel(macid_hi, &mac_regs->mac_adr[0].high);
508ee443b8SBin Meng writel(macid_lo, &mac_regs->mac_adr[0].low);
518ee443b8SBin Meng writel(0xfffe, &mac_regs->addr_mask);
528ee443b8SBin Meng
538ee443b8SBin Meng start = get_timer(0);
548ee443b8SBin Meng while (get_timer(start) < PCH_GBE_TIMEOUT) {
558ee443b8SBin Meng if (!(readl(&mac_regs->addr_mask) & PCH_GBE_BUSY))
568ee443b8SBin Meng return 0;
578ee443b8SBin Meng
588ee443b8SBin Meng udelay(10);
598ee443b8SBin Meng }
608ee443b8SBin Meng
618ee443b8SBin Meng return -ETIME;
628ee443b8SBin Meng }
638ee443b8SBin Meng
pch_gbe_reset(struct udevice * dev)64ca19a793SBin Meng static int pch_gbe_reset(struct udevice *dev)
658ee443b8SBin Meng {
66ca19a793SBin Meng struct pch_gbe_priv *priv = dev_get_priv(dev);
67ca19a793SBin Meng struct eth_pdata *plat = dev_get_platdata(dev);
688ee443b8SBin Meng struct pch_gbe_regs *mac_regs = priv->mac_regs;
698ee443b8SBin Meng ulong start;
708ee443b8SBin Meng
718ee443b8SBin Meng priv->rx_idx = 0;
728ee443b8SBin Meng priv->tx_idx = 0;
738ee443b8SBin Meng
748ee443b8SBin Meng writel(PCH_GBE_ALL_RST, &mac_regs->reset);
758ee443b8SBin Meng
768ee443b8SBin Meng /*
778ee443b8SBin Meng * Configure the MAC to RGMII mode after reset
788ee443b8SBin Meng *
798ee443b8SBin Meng * For some unknown reason, we must do the configuration here right
808ee443b8SBin Meng * after resetting the whole MAC, otherwise the reset bit in the RESET
818ee443b8SBin Meng * register will never be cleared by the hardware. And there is another
828ee443b8SBin Meng * way of having the same magic, that is to configure the MODE register
838ee443b8SBin Meng * to have the MAC work in MII/GMII mode, which is how current Linux
848ee443b8SBin Meng * pch_gbe driver does. Since anyway we need program the MAC to RGMII
858ee443b8SBin Meng * mode in the driver, we just do it here.
868ee443b8SBin Meng *
878ee443b8SBin Meng * Note: this behavior is not documented in the hardware manual.
888ee443b8SBin Meng */
898ee443b8SBin Meng writel(PCH_GBE_RGMII_MODE_RGMII | PCH_GBE_CHIP_TYPE_INTERNAL,
908ee443b8SBin Meng &mac_regs->rgmii_ctrl);
918ee443b8SBin Meng
928ee443b8SBin Meng start = get_timer(0);
938ee443b8SBin Meng while (get_timer(start) < PCH_GBE_TIMEOUT) {
948ee443b8SBin Meng if (!(readl(&mac_regs->reset) & PCH_GBE_ALL_RST)) {
958ee443b8SBin Meng /*
968ee443b8SBin Meng * Soft reset clears hardware MAC address registers,
978ee443b8SBin Meng * so we have to reload MAC address here in order to
988ee443b8SBin Meng * make linux pch_gbe driver happy.
998ee443b8SBin Meng */
100ca19a793SBin Meng return pch_gbe_mac_write(mac_regs, plat->enetaddr);
1018ee443b8SBin Meng }
1028ee443b8SBin Meng
1038ee443b8SBin Meng udelay(10);
1048ee443b8SBin Meng }
1058ee443b8SBin Meng
1068ee443b8SBin Meng debug("pch_gbe: reset timeout\n");
1078ee443b8SBin Meng return -ETIME;
1088ee443b8SBin Meng }
1098ee443b8SBin Meng
pch_gbe_rx_descs_init(struct udevice * dev)110ca19a793SBin Meng static void pch_gbe_rx_descs_init(struct udevice *dev)
1118ee443b8SBin Meng {
112ca19a793SBin Meng struct pch_gbe_priv *priv = dev_get_priv(dev);
1138ee443b8SBin Meng struct pch_gbe_regs *mac_regs = priv->mac_regs;
1148ee443b8SBin Meng struct pch_gbe_rx_desc *rx_desc = &priv->rx_desc[0];
1158ee443b8SBin Meng int i;
1168ee443b8SBin Meng
1178ee443b8SBin Meng memset(rx_desc, 0, sizeof(struct pch_gbe_rx_desc) * PCH_GBE_DESC_NUM);
1188ee443b8SBin Meng for (i = 0; i < PCH_GBE_DESC_NUM; i++)
11952e727c8SPaul Burton rx_desc[i].buffer_addr = dm_pci_virt_to_mem(priv->dev,
120db225f11SPaul Burton priv->rx_buff[i]);
1218ee443b8SBin Meng
1222303bff7SPaul Burton flush_dcache_range((ulong)rx_desc, (ulong)&rx_desc[PCH_GBE_DESC_NUM]);
1232303bff7SPaul Burton
12452e727c8SPaul Burton writel(dm_pci_virt_to_mem(priv->dev, rx_desc),
1258ee443b8SBin Meng &mac_regs->rx_dsc_base);
1268ee443b8SBin Meng writel(sizeof(struct pch_gbe_rx_desc) * (PCH_GBE_DESC_NUM - 1),
1278ee443b8SBin Meng &mac_regs->rx_dsc_size);
1288ee443b8SBin Meng
12952e727c8SPaul Burton writel(dm_pci_virt_to_mem(priv->dev, rx_desc + 1),
1308ee443b8SBin Meng &mac_regs->rx_dsc_sw_p);
1318ee443b8SBin Meng }
1328ee443b8SBin Meng
pch_gbe_tx_descs_init(struct udevice * dev)133ca19a793SBin Meng static void pch_gbe_tx_descs_init(struct udevice *dev)
1348ee443b8SBin Meng {
135ca19a793SBin Meng struct pch_gbe_priv *priv = dev_get_priv(dev);
1368ee443b8SBin Meng struct pch_gbe_regs *mac_regs = priv->mac_regs;
1378ee443b8SBin Meng struct pch_gbe_tx_desc *tx_desc = &priv->tx_desc[0];
1388ee443b8SBin Meng
1398ee443b8SBin Meng memset(tx_desc, 0, sizeof(struct pch_gbe_tx_desc) * PCH_GBE_DESC_NUM);
1408ee443b8SBin Meng
1412303bff7SPaul Burton flush_dcache_range((ulong)tx_desc, (ulong)&tx_desc[PCH_GBE_DESC_NUM]);
1422303bff7SPaul Burton
14352e727c8SPaul Burton writel(dm_pci_virt_to_mem(priv->dev, tx_desc),
1448ee443b8SBin Meng &mac_regs->tx_dsc_base);
1458ee443b8SBin Meng writel(sizeof(struct pch_gbe_tx_desc) * (PCH_GBE_DESC_NUM - 1),
1468ee443b8SBin Meng &mac_regs->tx_dsc_size);
14752e727c8SPaul Burton writel(dm_pci_virt_to_mem(priv->dev, tx_desc + 1),
1488ee443b8SBin Meng &mac_regs->tx_dsc_sw_p);
1498ee443b8SBin Meng }
1508ee443b8SBin Meng
pch_gbe_adjust_link(struct pch_gbe_regs * mac_regs,struct phy_device * phydev)1518ee443b8SBin Meng static void pch_gbe_adjust_link(struct pch_gbe_regs *mac_regs,
1528ee443b8SBin Meng struct phy_device *phydev)
1538ee443b8SBin Meng {
1548ee443b8SBin Meng if (!phydev->link) {
1558ee443b8SBin Meng printf("%s: No link.\n", phydev->dev->name);
1568ee443b8SBin Meng return;
1578ee443b8SBin Meng }
1588ee443b8SBin Meng
1598ee443b8SBin Meng clrbits_le32(&mac_regs->rgmii_ctrl,
1608ee443b8SBin Meng PCH_GBE_RGMII_RATE_2_5M | PCH_GBE_CRS_SEL);
1618ee443b8SBin Meng clrbits_le32(&mac_regs->mode,
1628ee443b8SBin Meng PCH_GBE_MODE_GMII_ETHER | PCH_GBE_MODE_FULL_DUPLEX);
1638ee443b8SBin Meng
1648ee443b8SBin Meng switch (phydev->speed) {
1658ee443b8SBin Meng case 1000:
1668ee443b8SBin Meng setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_125M);
1678ee443b8SBin Meng setbits_le32(&mac_regs->mode, PCH_GBE_MODE_GMII_ETHER);
1688ee443b8SBin Meng break;
1698ee443b8SBin Meng case 100:
1708ee443b8SBin Meng setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_25M);
1718ee443b8SBin Meng setbits_le32(&mac_regs->mode, PCH_GBE_MODE_MII_ETHER);
1728ee443b8SBin Meng break;
1738ee443b8SBin Meng case 10:
1748ee443b8SBin Meng setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_2_5M);
1758ee443b8SBin Meng setbits_le32(&mac_regs->mode, PCH_GBE_MODE_MII_ETHER);
1768ee443b8SBin Meng break;
1778ee443b8SBin Meng }
1788ee443b8SBin Meng
1798ee443b8SBin Meng if (phydev->duplex) {
1808ee443b8SBin Meng setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_CRS_SEL);
1818ee443b8SBin Meng setbits_le32(&mac_regs->mode, PCH_GBE_MODE_FULL_DUPLEX);
1828ee443b8SBin Meng }
1838ee443b8SBin Meng
1848ee443b8SBin Meng printf("Speed: %d, %s duplex\n", phydev->speed,
1858ee443b8SBin Meng (phydev->duplex) ? "full" : "half");
1868ee443b8SBin Meng
1878ee443b8SBin Meng return;
1888ee443b8SBin Meng }
1898ee443b8SBin Meng
pch_gbe_start(struct udevice * dev)190ca19a793SBin Meng static int pch_gbe_start(struct udevice *dev)
1918ee443b8SBin Meng {
192ca19a793SBin Meng struct pch_gbe_priv *priv = dev_get_priv(dev);
1938ee443b8SBin Meng struct pch_gbe_regs *mac_regs = priv->mac_regs;
1948ee443b8SBin Meng
1958ee443b8SBin Meng if (pch_gbe_reset(dev))
1968ee443b8SBin Meng return -1;
1978ee443b8SBin Meng
1988ee443b8SBin Meng pch_gbe_rx_descs_init(dev);
1998ee443b8SBin Meng pch_gbe_tx_descs_init(dev);
2008ee443b8SBin Meng
2018ee443b8SBin Meng /* Enable frame bursting */
2028ee443b8SBin Meng writel(PCH_GBE_MODE_FR_BST, &mac_regs->mode);
2038ee443b8SBin Meng /* Disable TCP/IP accelerator */
2048ee443b8SBin Meng writel(PCH_GBE_RX_TCPIPACC_OFF, &mac_regs->tcpip_acc);
2058ee443b8SBin Meng /* Disable RX flow control */
2068ee443b8SBin Meng writel(0, &mac_regs->rx_fctrl);
2078ee443b8SBin Meng /* Configure RX/TX mode */
2088ee443b8SBin Meng writel(PCH_GBE_RH_ALM_EMP_16 | PCH_GBE_RH_ALM_FULL_16 |
2098ee443b8SBin Meng PCH_GBE_RH_RD_TRG_32, &mac_regs->rx_mode);
2108ee443b8SBin Meng writel(PCH_GBE_TM_TH_TX_STRT_32 | PCH_GBE_TM_TH_ALM_EMP_16 |
2118ee443b8SBin Meng PCH_GBE_TM_TH_ALM_FULL_32 | PCH_GBE_TM_ST_AND_FD |
2128ee443b8SBin Meng PCH_GBE_TM_SHORT_PKT, &mac_regs->tx_mode);
2138ee443b8SBin Meng
2148ee443b8SBin Meng /* Start up the PHY */
2158ee443b8SBin Meng if (phy_startup(priv->phydev)) {
2168ee443b8SBin Meng printf("Could not initialize PHY %s\n",
2178ee443b8SBin Meng priv->phydev->dev->name);
2188ee443b8SBin Meng return -1;
2198ee443b8SBin Meng }
2208ee443b8SBin Meng
2218ee443b8SBin Meng pch_gbe_adjust_link(mac_regs, priv->phydev);
2228ee443b8SBin Meng
2238ee443b8SBin Meng if (!priv->phydev->link)
2248ee443b8SBin Meng return -1;
2258ee443b8SBin Meng
2268ee443b8SBin Meng /* Enable TX & RX */
2278ee443b8SBin Meng writel(PCH_GBE_RX_DMA_EN | PCH_GBE_TX_DMA_EN, &mac_regs->dma_ctrl);
2288ee443b8SBin Meng writel(PCH_GBE_MRE_MAC_RX_EN, &mac_regs->mac_rx_en);
2298ee443b8SBin Meng
2308ee443b8SBin Meng return 0;
2318ee443b8SBin Meng }
2328ee443b8SBin Meng
pch_gbe_stop(struct udevice * dev)233ca19a793SBin Meng static void pch_gbe_stop(struct udevice *dev)
2348ee443b8SBin Meng {
235ca19a793SBin Meng struct pch_gbe_priv *priv = dev_get_priv(dev);
2368ee443b8SBin Meng
2378ee443b8SBin Meng pch_gbe_reset(dev);
2388ee443b8SBin Meng
2398ee443b8SBin Meng phy_shutdown(priv->phydev);
2408ee443b8SBin Meng }
2418ee443b8SBin Meng
pch_gbe_send(struct udevice * dev,void * packet,int length)242ca19a793SBin Meng static int pch_gbe_send(struct udevice *dev, void *packet, int length)
2438ee443b8SBin Meng {
244ca19a793SBin Meng struct pch_gbe_priv *priv = dev_get_priv(dev);
2458ee443b8SBin Meng struct pch_gbe_regs *mac_regs = priv->mac_regs;
2468ee443b8SBin Meng struct pch_gbe_tx_desc *tx_head, *tx_desc;
2478ee443b8SBin Meng u16 frame_ctrl = 0;
2488ee443b8SBin Meng u32 int_st;
2498ee443b8SBin Meng ulong start;
2508ee443b8SBin Meng
2512303bff7SPaul Burton flush_dcache_range((ulong)packet, (ulong)packet + length);
2522303bff7SPaul Burton
2538ee443b8SBin Meng tx_head = &priv->tx_desc[0];
2548ee443b8SBin Meng tx_desc = &priv->tx_desc[priv->tx_idx];
2558ee443b8SBin Meng
2568ee443b8SBin Meng if (length < 64)
2578ee443b8SBin Meng frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
2588ee443b8SBin Meng
25952e727c8SPaul Burton tx_desc->buffer_addr = dm_pci_virt_to_mem(priv->dev, packet);
2608ee443b8SBin Meng tx_desc->length = length;
2618ee443b8SBin Meng tx_desc->tx_words_eob = length + 3;
2628ee443b8SBin Meng tx_desc->tx_frame_ctrl = frame_ctrl;
2638ee443b8SBin Meng tx_desc->dma_status = 0;
2648ee443b8SBin Meng tx_desc->gbec_status = 0;
2658ee443b8SBin Meng
2662303bff7SPaul Burton flush_dcache_range((ulong)tx_desc, (ulong)&tx_desc[1]);
2672303bff7SPaul Burton
2688ee443b8SBin Meng /* Test the wrap-around condition */
2698ee443b8SBin Meng if (++priv->tx_idx >= PCH_GBE_DESC_NUM)
2708ee443b8SBin Meng priv->tx_idx = 0;
2718ee443b8SBin Meng
27252e727c8SPaul Burton writel(dm_pci_virt_to_mem(priv->dev, tx_head + priv->tx_idx),
2738ee443b8SBin Meng &mac_regs->tx_dsc_sw_p);
2748ee443b8SBin Meng
2758ee443b8SBin Meng start = get_timer(0);
2768ee443b8SBin Meng while (get_timer(start) < PCH_GBE_TIMEOUT) {
2778ee443b8SBin Meng int_st = readl(&mac_regs->int_st);
2788ee443b8SBin Meng if (int_st & PCH_GBE_INT_TX_CMPLT)
2798ee443b8SBin Meng return 0;
2808ee443b8SBin Meng
2818ee443b8SBin Meng udelay(10);
2828ee443b8SBin Meng }
2838ee443b8SBin Meng
2848ee443b8SBin Meng debug("pch_gbe: sent failed\n");
2858ee443b8SBin Meng return -ETIME;
2868ee443b8SBin Meng }
2878ee443b8SBin Meng
pch_gbe_recv(struct udevice * dev,int flags,uchar ** packetp)288ca19a793SBin Meng static int pch_gbe_recv(struct udevice *dev, int flags, uchar **packetp)
2898ee443b8SBin Meng {
290ca19a793SBin Meng struct pch_gbe_priv *priv = dev_get_priv(dev);
2918ee443b8SBin Meng struct pch_gbe_regs *mac_regs = priv->mac_regs;
292ca19a793SBin Meng struct pch_gbe_rx_desc *rx_desc;
29352e727c8SPaul Burton ulong hw_desc, length;
29452e727c8SPaul Burton void *buffer;
2958ee443b8SBin Meng
2968ee443b8SBin Meng rx_desc = &priv->rx_desc[priv->rx_idx];
2978ee443b8SBin Meng
2988ee443b8SBin Meng readl(&mac_regs->int_st);
2998ee443b8SBin Meng hw_desc = readl(&mac_regs->rx_dsc_hw_p_hld);
3008ee443b8SBin Meng
3018ee443b8SBin Meng /* Just return if not receiving any packet */
30252e727c8SPaul Burton if (virt_to_phys(rx_desc) == hw_desc)
303ca19a793SBin Meng return -EAGAIN;
3048ee443b8SBin Meng
3052303bff7SPaul Burton /* Invalidate the descriptor */
3062303bff7SPaul Burton invalidate_dcache_range((ulong)rx_desc, (ulong)&rx_desc[1]);
3072303bff7SPaul Burton
3088ee443b8SBin Meng length = rx_desc->rx_words_eob - 3 - ETH_FCS_LEN;
30952e727c8SPaul Burton buffer = dm_pci_mem_to_virt(priv->dev, rx_desc->buffer_addr, length, 0);
3102303bff7SPaul Burton invalidate_dcache_range((ulong)buffer, (ulong)buffer + length);
31152e727c8SPaul Burton *packetp = (uchar *)buffer;
312ca19a793SBin Meng
313ca19a793SBin Meng return length;
314ca19a793SBin Meng }
315ca19a793SBin Meng
pch_gbe_free_pkt(struct udevice * dev,uchar * packet,int length)316ca19a793SBin Meng static int pch_gbe_free_pkt(struct udevice *dev, uchar *packet, int length)
317ca19a793SBin Meng {
318ca19a793SBin Meng struct pch_gbe_priv *priv = dev_get_priv(dev);
319ca19a793SBin Meng struct pch_gbe_regs *mac_regs = priv->mac_regs;
320ca19a793SBin Meng struct pch_gbe_rx_desc *rx_head = &priv->rx_desc[0];
321ca19a793SBin Meng int rx_swp;
3228ee443b8SBin Meng
3238ee443b8SBin Meng /* Test the wrap-around condition */
3248ee443b8SBin Meng if (++priv->rx_idx >= PCH_GBE_DESC_NUM)
3258ee443b8SBin Meng priv->rx_idx = 0;
3268ee443b8SBin Meng rx_swp = priv->rx_idx;
3278ee443b8SBin Meng if (++rx_swp >= PCH_GBE_DESC_NUM)
3288ee443b8SBin Meng rx_swp = 0;
3298ee443b8SBin Meng
33052e727c8SPaul Burton writel(dm_pci_virt_to_mem(priv->dev, rx_head + rx_swp),
3318ee443b8SBin Meng &mac_regs->rx_dsc_sw_p);
3328ee443b8SBin Meng
333ca19a793SBin Meng return 0;
3348ee443b8SBin Meng }
3358ee443b8SBin Meng
pch_gbe_mdio_ready(struct pch_gbe_regs * mac_regs)3368ee443b8SBin Meng static int pch_gbe_mdio_ready(struct pch_gbe_regs *mac_regs)
3378ee443b8SBin Meng {
3388ee443b8SBin Meng ulong start = get_timer(0);
3398ee443b8SBin Meng
3408ee443b8SBin Meng while (get_timer(start) < PCH_GBE_TIMEOUT) {
3418ee443b8SBin Meng if (readl(&mac_regs->miim) & PCH_GBE_MIIM_OPER_READY)
3428ee443b8SBin Meng return 0;
3438ee443b8SBin Meng
3448ee443b8SBin Meng udelay(10);
3458ee443b8SBin Meng }
3468ee443b8SBin Meng
3478ee443b8SBin Meng return -ETIME;
3488ee443b8SBin Meng }
3498ee443b8SBin Meng
pch_gbe_mdio_read(struct mii_dev * bus,int addr,int devad,int reg)3508ee443b8SBin Meng static int pch_gbe_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
3518ee443b8SBin Meng {
3528ee443b8SBin Meng struct pch_gbe_regs *mac_regs = bus->priv;
3538ee443b8SBin Meng u32 miim;
3548ee443b8SBin Meng
3558ee443b8SBin Meng if (pch_gbe_mdio_ready(mac_regs))
3568ee443b8SBin Meng return -ETIME;
3578ee443b8SBin Meng
3588ee443b8SBin Meng miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
3598ee443b8SBin Meng (reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
3608ee443b8SBin Meng PCH_GBE_MIIM_OPER_READ;
3618ee443b8SBin Meng writel(miim, &mac_regs->miim);
3628ee443b8SBin Meng
3638ee443b8SBin Meng if (pch_gbe_mdio_ready(mac_regs))
3648ee443b8SBin Meng return -ETIME;
3658ee443b8SBin Meng
3668ee443b8SBin Meng return readl(&mac_regs->miim) & 0xffff;
3678ee443b8SBin Meng }
3688ee443b8SBin Meng
pch_gbe_mdio_write(struct mii_dev * bus,int addr,int devad,int reg,u16 val)3698ee443b8SBin Meng static int pch_gbe_mdio_write(struct mii_dev *bus, int addr, int devad,
3708ee443b8SBin Meng int reg, u16 val)
3718ee443b8SBin Meng {
3728ee443b8SBin Meng struct pch_gbe_regs *mac_regs = bus->priv;
3738ee443b8SBin Meng u32 miim;
3748ee443b8SBin Meng
3758ee443b8SBin Meng if (pch_gbe_mdio_ready(mac_regs))
3768ee443b8SBin Meng return -ETIME;
3778ee443b8SBin Meng
3788ee443b8SBin Meng miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
3798ee443b8SBin Meng (reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
3808ee443b8SBin Meng PCH_GBE_MIIM_OPER_WRITE | val;
3818ee443b8SBin Meng writel(miim, &mac_regs->miim);
3828ee443b8SBin Meng
3838ee443b8SBin Meng if (pch_gbe_mdio_ready(mac_regs))
3848ee443b8SBin Meng return -ETIME;
3858ee443b8SBin Meng else
3868ee443b8SBin Meng return 0;
3878ee443b8SBin Meng }
3888ee443b8SBin Meng
pch_gbe_mdio_init(const char * name,struct pch_gbe_regs * mac_regs)389ca19a793SBin Meng static int pch_gbe_mdio_init(const char *name, struct pch_gbe_regs *mac_regs)
3908ee443b8SBin Meng {
3918ee443b8SBin Meng struct mii_dev *bus;
3928ee443b8SBin Meng
3938ee443b8SBin Meng bus = mdio_alloc();
3948ee443b8SBin Meng if (!bus) {
3958ee443b8SBin Meng debug("pch_gbe: failed to allocate MDIO bus\n");
3968ee443b8SBin Meng return -ENOMEM;
3978ee443b8SBin Meng }
3988ee443b8SBin Meng
3998ee443b8SBin Meng bus->read = pch_gbe_mdio_read;
4008ee443b8SBin Meng bus->write = pch_gbe_mdio_write;
401192bc694SBen Whitten strcpy(bus->name, name);
4028ee443b8SBin Meng
4038ee443b8SBin Meng bus->priv = (void *)mac_regs;
4048ee443b8SBin Meng
4058ee443b8SBin Meng return mdio_register(bus);
4068ee443b8SBin Meng }
4078ee443b8SBin Meng
pch_gbe_phy_init(struct udevice * dev)408ca19a793SBin Meng static int pch_gbe_phy_init(struct udevice *dev)
4098ee443b8SBin Meng {
410ca19a793SBin Meng struct pch_gbe_priv *priv = dev_get_priv(dev);
411ca19a793SBin Meng struct eth_pdata *plat = dev_get_platdata(dev);
4128ee443b8SBin Meng struct phy_device *phydev;
4138ee443b8SBin Meng int mask = 0xffffffff;
4148ee443b8SBin Meng
415ca19a793SBin Meng phydev = phy_find_by_mask(priv->bus, mask, plat->phy_interface);
4168ee443b8SBin Meng if (!phydev) {
4178ee443b8SBin Meng printf("pch_gbe: cannot find the phy\n");
4188ee443b8SBin Meng return -1;
4198ee443b8SBin Meng }
4208ee443b8SBin Meng
4218ee443b8SBin Meng phy_connect_dev(phydev, dev);
4228ee443b8SBin Meng
4238ee443b8SBin Meng phydev->supported &= PHY_GBIT_FEATURES;
4248ee443b8SBin Meng phydev->advertising = phydev->supported;
4258ee443b8SBin Meng
4268ee443b8SBin Meng priv->phydev = phydev;
4278ee443b8SBin Meng phy_config(phydev);
4288ee443b8SBin Meng
429ca19a793SBin Meng return 0;
4308ee443b8SBin Meng }
4318ee443b8SBin Meng
pch_gbe_probe(struct udevice * dev)432*339613ebSBin Meng static int pch_gbe_probe(struct udevice *dev)
4338ee443b8SBin Meng {
4348ee443b8SBin Meng struct pch_gbe_priv *priv;
435ca19a793SBin Meng struct eth_pdata *plat = dev_get_platdata(dev);
436154bf12fSPaul Burton void *iobase;
43743979cbaSPaul Burton int err;
4388ee443b8SBin Meng
4398ee443b8SBin Meng /*
4408ee443b8SBin Meng * The priv structure contains the descriptors and frame buffers which
441ca19a793SBin Meng * need a strict buswidth alignment (64 bytes). This is guaranteed by
442ca19a793SBin Meng * DM_FLAG_ALLOC_PRIV_DMA flag in the U_BOOT_DRIVER.
4438ee443b8SBin Meng */
444ca19a793SBin Meng priv = dev_get_priv(dev);
4458ee443b8SBin Meng
446c52ac3f9SBin Meng priv->dev = dev;
4478ee443b8SBin Meng
448154bf12fSPaul Burton iobase = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_1, PCI_REGION_MEM);
4498ee443b8SBin Meng
450154bf12fSPaul Burton plat->iobase = (ulong)iobase;
4518ee443b8SBin Meng priv->mac_regs = (struct pch_gbe_regs *)iobase;
4528ee443b8SBin Meng
4538ee443b8SBin Meng /* Read MAC address from SROM and initialize dev->enetaddr with it */
454ca19a793SBin Meng pch_gbe_mac_read(priv->mac_regs, plat->enetaddr);
4558ee443b8SBin Meng
456ca19a793SBin Meng plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
4578ee443b8SBin Meng pch_gbe_mdio_init(dev->name, priv->mac_regs);
4588ee443b8SBin Meng priv->bus = miiphy_get_dev_by_name(dev->name);
4598ee443b8SBin Meng
46043979cbaSPaul Burton err = pch_gbe_reset(dev);
46143979cbaSPaul Burton if (err)
46243979cbaSPaul Burton return err;
46343979cbaSPaul Burton
4648ee443b8SBin Meng return pch_gbe_phy_init(dev);
4658ee443b8SBin Meng }
466ca19a793SBin Meng
pch_gbe_remove(struct udevice * dev)467*339613ebSBin Meng static int pch_gbe_remove(struct udevice *dev)
4683f616b60SBin Meng {
4693f616b60SBin Meng struct pch_gbe_priv *priv = dev_get_priv(dev);
4703f616b60SBin Meng
4713f616b60SBin Meng free(priv->phydev);
4723f616b60SBin Meng mdio_unregister(priv->bus);
4733f616b60SBin Meng mdio_free(priv->bus);
4743f616b60SBin Meng
4753f616b60SBin Meng return 0;
4763f616b60SBin Meng }
4773f616b60SBin Meng
478ca19a793SBin Meng static const struct eth_ops pch_gbe_ops = {
479ca19a793SBin Meng .start = pch_gbe_start,
480ca19a793SBin Meng .send = pch_gbe_send,
481ca19a793SBin Meng .recv = pch_gbe_recv,
482ca19a793SBin Meng .free_pkt = pch_gbe_free_pkt,
483ca19a793SBin Meng .stop = pch_gbe_stop,
484ca19a793SBin Meng };
485ca19a793SBin Meng
486ca19a793SBin Meng static const struct udevice_id pch_gbe_ids[] = {
487ca19a793SBin Meng { .compatible = "intel,pch-gbe" },
488ca19a793SBin Meng { }
489ca19a793SBin Meng };
490ca19a793SBin Meng
491ca19a793SBin Meng U_BOOT_DRIVER(eth_pch_gbe) = {
492ca19a793SBin Meng .name = "pch_gbe",
493ca19a793SBin Meng .id = UCLASS_ETH,
494ca19a793SBin Meng .of_match = pch_gbe_ids,
495ca19a793SBin Meng .probe = pch_gbe_probe,
4963f616b60SBin Meng .remove = pch_gbe_remove,
497ca19a793SBin Meng .ops = &pch_gbe_ops,
498ca19a793SBin Meng .priv_auto_alloc_size = sizeof(struct pch_gbe_priv),
499ca19a793SBin Meng .platdata_auto_alloc_size = sizeof(struct eth_pdata),
500ca19a793SBin Meng .flags = DM_FLAG_ALLOC_PRIV_DMA,
501ca19a793SBin Meng };
502ca19a793SBin Meng
503ca19a793SBin Meng U_BOOT_PCI_DEVICE(eth_pch_gbe, supported);
504