1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 28ee443b8SBin Meng /* 38ee443b8SBin Meng * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 48ee443b8SBin Meng * 58ee443b8SBin Meng * Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver 68ee443b8SBin Meng * Adapted from linux drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h 78ee443b8SBin Meng */ 88ee443b8SBin Meng 98ee443b8SBin Meng #ifndef _PCH_GBE_H_ 108ee443b8SBin Meng #define _PCH_GBE_H_ 118ee443b8SBin Meng 128ee443b8SBin Meng #define PCH_GBE_TIMEOUT (3 * CONFIG_SYS_HZ) 138ee443b8SBin Meng 148ee443b8SBin Meng #define PCH_GBE_DESC_NUM 4 158ee443b8SBin Meng #define PCH_GBE_ALIGN_SIZE 64 168ee443b8SBin Meng 178ee443b8SBin Meng /* 188ee443b8SBin Meng * Topcliff GBE MAC supports receiving ethernet frames with normal frame size 198ee443b8SBin Meng * (64-1518 bytes) as well as up to 10318 bytes, however it does not have a 208ee443b8SBin Meng * register bit to turn off receiving 'jumbo frame', so we have to allocate 218ee443b8SBin Meng * our own buffer to store the received frames instead of using U-Boot's own. 228ee443b8SBin Meng */ 238ee443b8SBin Meng #define PCH_GBE_RX_FRAME_LEN ROUND(10318, PCH_GBE_ALIGN_SIZE) 248ee443b8SBin Meng 258ee443b8SBin Meng /* Interrupt Status */ 268ee443b8SBin Meng /* Interrupt Status Hold */ 278ee443b8SBin Meng /* Interrupt Enable */ 288ee443b8SBin Meng #define PCH_GBE_INT_RX_DMA_CMPLT 0x00000001 298ee443b8SBin Meng #define PCH_GBE_INT_RX_VALID 0x00000002 308ee443b8SBin Meng #define PCH_GBE_INT_RX_FRAME_ERR 0x00000004 318ee443b8SBin Meng #define PCH_GBE_INT_RX_FIFO_ERR 0x00000008 328ee443b8SBin Meng #define PCH_GBE_INT_RX_DMA_ERR 0x00000010 338ee443b8SBin Meng #define PCH_GBE_INT_RX_DSC_EMP 0x00000020 348ee443b8SBin Meng #define PCH_GBE_INT_TX_CMPLT 0x00000100 358ee443b8SBin Meng #define PCH_GBE_INT_TX_DMA_CMPLT 0x00000200 368ee443b8SBin Meng #define PCH_GBE_INT_TX_FIFO_ERR 0x00000400 378ee443b8SBin Meng #define PCH_GBE_INT_TX_DMA_ERR 0x00000800 388ee443b8SBin Meng #define PCH_GBE_INT_PAUSE_CMPLT 0x00001000 398ee443b8SBin Meng #define PCH_GBE_INT_MIIM_CMPLT 0x00010000 408ee443b8SBin Meng #define PCH_GBE_INT_PHY_INT 0x00100000 418ee443b8SBin Meng #define PCH_GBE_INT_WOL_DET 0x01000000 428ee443b8SBin Meng #define PCH_GBE_INT_TCPIP_ERR 0x10000000 438ee443b8SBin Meng 448ee443b8SBin Meng /* Mode */ 458ee443b8SBin Meng #define PCH_GBE_MODE_MII_ETHER 0x00000000 468ee443b8SBin Meng #define PCH_GBE_MODE_GMII_ETHER 0x80000000 478ee443b8SBin Meng #define PCH_GBE_MODE_HALF_DUPLEX 0x00000000 488ee443b8SBin Meng #define PCH_GBE_MODE_FULL_DUPLEX 0x40000000 498ee443b8SBin Meng #define PCH_GBE_MODE_FR_BST 0x04000000 508ee443b8SBin Meng 518ee443b8SBin Meng /* Reset */ 528ee443b8SBin Meng #define PCH_GBE_ALL_RST 0x80000000 538ee443b8SBin Meng #define PCH_GBE_TX_RST 0x00008000 548ee443b8SBin Meng #define PCH_GBE_RX_RST 0x00004000 558ee443b8SBin Meng 568ee443b8SBin Meng /* TCP/IP Accelerator Control */ 578ee443b8SBin Meng #define PCH_GBE_EX_LIST_EN 0x00000008 588ee443b8SBin Meng #define PCH_GBE_RX_TCPIPACC_OFF 0x00000004 598ee443b8SBin Meng #define PCH_GBE_TX_TCPIPACC_EN 0x00000002 608ee443b8SBin Meng #define PCH_GBE_RX_TCPIPACC_EN 0x00000001 618ee443b8SBin Meng 628ee443b8SBin Meng /* MAC RX Enable */ 638ee443b8SBin Meng #define PCH_GBE_MRE_MAC_RX_EN 0x00000001 648ee443b8SBin Meng 658ee443b8SBin Meng /* RX Flow Control */ 668ee443b8SBin Meng #define PCH_GBE_FL_CTRL_EN 0x80000000 678ee443b8SBin Meng 688ee443b8SBin Meng /* RX Mode */ 698ee443b8SBin Meng #define PCH_GBE_ADD_FIL_EN 0x80000000 708ee443b8SBin Meng #define PCH_GBE_MLT_FIL_EN 0x40000000 718ee443b8SBin Meng #define PCH_GBE_RH_ALM_EMP_4 0x00000000 728ee443b8SBin Meng #define PCH_GBE_RH_ALM_EMP_8 0x00004000 738ee443b8SBin Meng #define PCH_GBE_RH_ALM_EMP_16 0x00008000 748ee443b8SBin Meng #define PCH_GBE_RH_ALM_EMP_32 0x0000c000 758ee443b8SBin Meng #define PCH_GBE_RH_ALM_FULL_4 0x00000000 768ee443b8SBin Meng #define PCH_GBE_RH_ALM_FULL_8 0x00001000 778ee443b8SBin Meng #define PCH_GBE_RH_ALM_FULL_16 0x00002000 788ee443b8SBin Meng #define PCH_GBE_RH_ALM_FULL_32 0x00003000 798ee443b8SBin Meng #define PCH_GBE_RH_RD_TRG_4 0x00000000 808ee443b8SBin Meng #define PCH_GBE_RH_RD_TRG_8 0x00000200 818ee443b8SBin Meng #define PCH_GBE_RH_RD_TRG_16 0x00000400 828ee443b8SBin Meng #define PCH_GBE_RH_RD_TRG_32 0x00000600 838ee443b8SBin Meng #define PCH_GBE_RH_RD_TRG_64 0x00000800 848ee443b8SBin Meng #define PCH_GBE_RH_RD_TRG_128 0x00000a00 858ee443b8SBin Meng #define PCH_GBE_RH_RD_TRG_256 0x00000c00 868ee443b8SBin Meng #define PCH_GBE_RH_RD_TRG_512 0x00000e00 878ee443b8SBin Meng 888ee443b8SBin Meng /* TX Mode */ 898ee443b8SBin Meng #define PCH_GBE_TM_NO_RTRY 0x80000000 908ee443b8SBin Meng #define PCH_GBE_TM_LONG_PKT 0x40000000 918ee443b8SBin Meng #define PCH_GBE_TM_ST_AND_FD 0x20000000 928ee443b8SBin Meng #define PCH_GBE_TM_SHORT_PKT 0x10000000 938ee443b8SBin Meng #define PCH_GBE_TM_LTCOL_RETX 0x08000000 948ee443b8SBin Meng #define PCH_GBE_TM_TH_TX_STRT_4 0x00000000 958ee443b8SBin Meng #define PCH_GBE_TM_TH_TX_STRT_8 0x00004000 968ee443b8SBin Meng #define PCH_GBE_TM_TH_TX_STRT_16 0x00008000 978ee443b8SBin Meng #define PCH_GBE_TM_TH_TX_STRT_32 0x0000c000 988ee443b8SBin Meng #define PCH_GBE_TM_TH_ALM_EMP_4 0x00000000 998ee443b8SBin Meng #define PCH_GBE_TM_TH_ALM_EMP_8 0x00000800 1008ee443b8SBin Meng #define PCH_GBE_TM_TH_ALM_EMP_16 0x00001000 1018ee443b8SBin Meng #define PCH_GBE_TM_TH_ALM_EMP_32 0x00001800 1028ee443b8SBin Meng #define PCH_GBE_TM_TH_ALM_EMP_64 0x00002000 1038ee443b8SBin Meng #define PCH_GBE_TM_TH_ALM_EMP_128 0x00002800 1048ee443b8SBin Meng #define PCH_GBE_TM_TH_ALM_EMP_256 0x00003000 1058ee443b8SBin Meng #define PCH_GBE_TM_TH_ALM_EMP_512 0x00003800 1068ee443b8SBin Meng #define PCH_GBE_TM_TH_ALM_FULL_4 0x00000000 1078ee443b8SBin Meng #define PCH_GBE_TM_TH_ALM_FULL_8 0x00000200 1088ee443b8SBin Meng #define PCH_GBE_TM_TH_ALM_FULL_16 0x00000400 1098ee443b8SBin Meng #define PCH_GBE_TM_TH_ALM_FULL_32 0x00000600 1108ee443b8SBin Meng 1118ee443b8SBin Meng /* MAC Address Mask */ 1128ee443b8SBin Meng #define PCH_GBE_BUSY 0x80000000 1138ee443b8SBin Meng 1148ee443b8SBin Meng /* MIIM */ 1158ee443b8SBin Meng #define PCH_GBE_MIIM_OPER_WRITE 0x04000000 1168ee443b8SBin Meng #define PCH_GBE_MIIM_OPER_READ 0x00000000 1178ee443b8SBin Meng #define PCH_GBE_MIIM_OPER_READY 0x04000000 1188ee443b8SBin Meng #define PCH_GBE_MIIM_PHY_ADDR_SHIFT 21 1198ee443b8SBin Meng #define PCH_GBE_MIIM_REG_ADDR_SHIFT 16 1208ee443b8SBin Meng 1218ee443b8SBin Meng /* RGMII Control */ 1228ee443b8SBin Meng #define PCH_GBE_CRS_SEL 0x00000010 1238ee443b8SBin Meng #define PCH_GBE_RGMII_RATE_125M 0x00000000 1248ee443b8SBin Meng #define PCH_GBE_RGMII_RATE_25M 0x00000008 1258ee443b8SBin Meng #define PCH_GBE_RGMII_RATE_2_5M 0x0000000c 1268ee443b8SBin Meng #define PCH_GBE_RGMII_MODE_GMII 0x00000000 1278ee443b8SBin Meng #define PCH_GBE_RGMII_MODE_RGMII 0x00000002 1288ee443b8SBin Meng #define PCH_GBE_CHIP_TYPE_EXTERNAL 0x00000000 1298ee443b8SBin Meng #define PCH_GBE_CHIP_TYPE_INTERNAL 0x00000001 1308ee443b8SBin Meng 1318ee443b8SBin Meng /* DMA Control */ 1328ee443b8SBin Meng #define PCH_GBE_RX_DMA_EN 0x00000002 1338ee443b8SBin Meng #define PCH_GBE_TX_DMA_EN 0x00000001 1348ee443b8SBin Meng 1358ee443b8SBin Meng /* Receive Descriptor bit definitions */ 1368ee443b8SBin Meng #define PCH_GBE_RXD_ACC_STAT_BCAST 0x00000400 1378ee443b8SBin Meng #define PCH_GBE_RXD_ACC_STAT_MCAST 0x00000200 1388ee443b8SBin Meng #define PCH_GBE_RXD_ACC_STAT_UCAST 0x00000100 1398ee443b8SBin Meng #define PCH_GBE_RXD_ACC_STAT_TCPIPOK 0x000000c0 1408ee443b8SBin Meng #define PCH_GBE_RXD_ACC_STAT_IPOK 0x00000080 1418ee443b8SBin Meng #define PCH_GBE_RXD_ACC_STAT_TCPOK 0x00000040 1428ee443b8SBin Meng #define PCH_GBE_RXD_ACC_STAT_IP6ERR 0x00000020 1438ee443b8SBin Meng #define PCH_GBE_RXD_ACC_STAT_OFLIST 0x00000010 1448ee443b8SBin Meng #define PCH_GBE_RXD_ACC_STAT_TYPEIP 0x00000008 1458ee443b8SBin Meng #define PCH_GBE_RXD_ACC_STAT_MACL 0x00000004 1468ee443b8SBin Meng #define PCH_GBE_RXD_ACC_STAT_PPPOE 0x00000002 1478ee443b8SBin Meng #define PCH_GBE_RXD_ACC_STAT_VTAGT 0x00000001 1488ee443b8SBin Meng #define PCH_GBE_RXD_GMAC_STAT_PAUSE 0x0200 1498ee443b8SBin Meng #define PCH_GBE_RXD_GMAC_STAT_MARBR 0x0100 1508ee443b8SBin Meng #define PCH_GBE_RXD_GMAC_STAT_MARMLT 0x0080 1518ee443b8SBin Meng #define PCH_GBE_RXD_GMAC_STAT_MARIND 0x0040 1528ee443b8SBin Meng #define PCH_GBE_RXD_GMAC_STAT_MARNOTMT 0x0020 1538ee443b8SBin Meng #define PCH_GBE_RXD_GMAC_STAT_TLONG 0x0010 1548ee443b8SBin Meng #define PCH_GBE_RXD_GMAC_STAT_TSHRT 0x0008 1558ee443b8SBin Meng #define PCH_GBE_RXD_GMAC_STAT_NOTOCTAL 0x0004 1568ee443b8SBin Meng #define PCH_GBE_RXD_GMAC_STAT_NBLERR 0x0002 1578ee443b8SBin Meng #define PCH_GBE_RXD_GMAC_STAT_CRCERR 0x0001 1588ee443b8SBin Meng 1598ee443b8SBin Meng /* Transmit Descriptor bit definitions */ 1608ee443b8SBin Meng #define PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF 0x0008 1618ee443b8SBin Meng #define PCH_GBE_TXD_CTRL_ITAG 0x0004 1628ee443b8SBin Meng #define PCH_GBE_TXD_CTRL_ICRC 0x0002 1638ee443b8SBin Meng #define PCH_GBE_TXD_CTRL_APAD 0x0001 1648ee443b8SBin Meng #define PCH_GBE_TXD_WORDS_SHIFT 2 1658ee443b8SBin Meng #define PCH_GBE_TXD_GMAC_STAT_CMPLT 0x2000 1668ee443b8SBin Meng #define PCH_GBE_TXD_GMAC_STAT_ABT 0x1000 1678ee443b8SBin Meng #define PCH_GBE_TXD_GMAC_STAT_EXCOL 0x0800 1688ee443b8SBin Meng #define PCH_GBE_TXD_GMAC_STAT_SNGCOL 0x0400 1698ee443b8SBin Meng #define PCH_GBE_TXD_GMAC_STAT_MLTCOL 0x0200 1708ee443b8SBin Meng #define PCH_GBE_TXD_GMAC_STAT_CRSER 0x0100 1718ee443b8SBin Meng #define PCH_GBE_TXD_GMAC_STAT_TLNG 0x0080 1728ee443b8SBin Meng #define PCH_GBE_TXD_GMAC_STAT_TSHRT 0x0040 1738ee443b8SBin Meng #define PCH_GBE_TXD_GMAC_STAT_LTCOL 0x0020 1748ee443b8SBin Meng #define PCH_GBE_TXD_GMAC_STAT_TFUNDFLW 0x0010 1758ee443b8SBin Meng 1768ee443b8SBin Meng /** 1778ee443b8SBin Meng * struct pch_gbe_rx_desc - Receive Descriptor 1788ee443b8SBin Meng * @buffer_addr: RX Frame Buffer Address 1798ee443b8SBin Meng * @tcp_ip_status: TCP/IP Accelerator Status 1808ee443b8SBin Meng * @rx_words_eob: RX word count and Byte position 1818ee443b8SBin Meng * @gbec_status: GMAC Status 1828ee443b8SBin Meng * @dma_status: DMA Status 1838ee443b8SBin Meng * @reserved1: Reserved 1848ee443b8SBin Meng * @reserved2: Reserved 1858ee443b8SBin Meng */ 1868ee443b8SBin Meng struct pch_gbe_rx_desc { 1878ee443b8SBin Meng u32 buffer_addr; 1888ee443b8SBin Meng u32 tcp_ip_status; 1898ee443b8SBin Meng u16 rx_words_eob; 1908ee443b8SBin Meng u16 gbec_status; 1918ee443b8SBin Meng u8 dma_status; 1928ee443b8SBin Meng u8 reserved1; 1938ee443b8SBin Meng u16 reserved2; 1948ee443b8SBin Meng }; 1958ee443b8SBin Meng 1968ee443b8SBin Meng /** 1978ee443b8SBin Meng * struct pch_gbe_tx_desc - Transmit Descriptor 1988ee443b8SBin Meng * @buffer_addr: TX Frame Buffer Address 1998ee443b8SBin Meng * @length: Data buffer length 2008ee443b8SBin Meng * @reserved1: Reserved 2018ee443b8SBin Meng * @tx_words_eob: TX word count and Byte position 2028ee443b8SBin Meng * @tx_frame_ctrl: TX Frame Control 2038ee443b8SBin Meng * @dma_status: DMA Status 2048ee443b8SBin Meng * @reserved2: Reserved 2058ee443b8SBin Meng * @gbec_status: GMAC Status 2068ee443b8SBin Meng */ 2078ee443b8SBin Meng struct pch_gbe_tx_desc { 2088ee443b8SBin Meng u32 buffer_addr; 2098ee443b8SBin Meng u16 length; 2108ee443b8SBin Meng u16 reserved1; 2118ee443b8SBin Meng u16 tx_words_eob; 2128ee443b8SBin Meng u16 tx_frame_ctrl; 2138ee443b8SBin Meng u8 dma_status; 2148ee443b8SBin Meng u8 reserved2; 2158ee443b8SBin Meng u16 gbec_status; 2168ee443b8SBin Meng }; 2178ee443b8SBin Meng 2188ee443b8SBin Meng /** 2198ee443b8SBin Meng * pch_gbe_regs_mac_adr - structure holding values of mac address registers 2208ee443b8SBin Meng * 2218ee443b8SBin Meng * @high Denotes the 1st to 4th byte from the initial of MAC address 2228ee443b8SBin Meng * @low Denotes the 5th to 6th byte from the initial of MAC address 2238ee443b8SBin Meng */ 2248ee443b8SBin Meng struct pch_gbe_regs_mac_adr { 2258ee443b8SBin Meng u32 high; 2268ee443b8SBin Meng u32 low; 2278ee443b8SBin Meng }; 2288ee443b8SBin Meng 2298ee443b8SBin Meng /** 2308ee443b8SBin Meng * pch_gbe_regs - structure holding values of MAC registers 2318ee443b8SBin Meng */ 2328ee443b8SBin Meng struct pch_gbe_regs { 2338ee443b8SBin Meng u32 int_st; 2348ee443b8SBin Meng u32 int_en; 2358ee443b8SBin Meng u32 mode; 2368ee443b8SBin Meng u32 reset; 2378ee443b8SBin Meng u32 tcpip_acc; 2388ee443b8SBin Meng u32 ex_list; 2398ee443b8SBin Meng u32 int_st_hold; 2408ee443b8SBin Meng u32 phy_int_ctrl; 2418ee443b8SBin Meng u32 mac_rx_en; 2428ee443b8SBin Meng u32 rx_fctrl; 2438ee443b8SBin Meng u32 pause_req; 2448ee443b8SBin Meng u32 rx_mode; 2458ee443b8SBin Meng u32 tx_mode; 2468ee443b8SBin Meng u32 rx_fifo_st; 2478ee443b8SBin Meng u32 tx_fifo_st; 2488ee443b8SBin Meng u32 tx_fid; 2498ee443b8SBin Meng u32 tx_result; 2508ee443b8SBin Meng u32 pause_pkt1; 2518ee443b8SBin Meng u32 pause_pkt2; 2528ee443b8SBin Meng u32 pause_pkt3; 2538ee443b8SBin Meng u32 pause_pkt4; 2548ee443b8SBin Meng u32 pause_pkt5; 2558ee443b8SBin Meng u32 reserve[2]; 2568ee443b8SBin Meng struct pch_gbe_regs_mac_adr mac_adr[16]; 2578ee443b8SBin Meng u32 addr_mask; 2588ee443b8SBin Meng u32 miim; 2598ee443b8SBin Meng u32 mac_addr_load; 2608ee443b8SBin Meng u32 rgmii_st; 2618ee443b8SBin Meng u32 rgmii_ctrl; 2628ee443b8SBin Meng u32 reserve3[3]; 2638ee443b8SBin Meng u32 dma_ctrl; 2648ee443b8SBin Meng u32 reserve4[3]; 2658ee443b8SBin Meng u32 rx_dsc_base; 2668ee443b8SBin Meng u32 rx_dsc_size; 2678ee443b8SBin Meng u32 rx_dsc_hw_p; 2688ee443b8SBin Meng u32 rx_dsc_hw_p_hld; 2698ee443b8SBin Meng u32 rx_dsc_sw_p; 2708ee443b8SBin Meng u32 reserve5[3]; 2718ee443b8SBin Meng u32 tx_dsc_base; 2728ee443b8SBin Meng u32 tx_dsc_size; 2738ee443b8SBin Meng u32 tx_dsc_hw_p; 2748ee443b8SBin Meng u32 tx_dsc_hw_p_hld; 2758ee443b8SBin Meng u32 tx_dsc_sw_p; 2768ee443b8SBin Meng u32 reserve6[3]; 2778ee443b8SBin Meng u32 rx_dma_st; 2788ee443b8SBin Meng u32 tx_dma_st; 2798ee443b8SBin Meng u32 reserve7[2]; 2808ee443b8SBin Meng u32 wol_st; 2818ee443b8SBin Meng u32 wol_ctrl; 2828ee443b8SBin Meng u32 wol_addr_mask; 2838ee443b8SBin Meng }; 2848ee443b8SBin Meng 2858ee443b8SBin Meng struct pch_gbe_priv { 2868ee443b8SBin Meng struct pch_gbe_rx_desc rx_desc[PCH_GBE_DESC_NUM]; 2878ee443b8SBin Meng struct pch_gbe_tx_desc tx_desc[PCH_GBE_DESC_NUM]; 2888ee443b8SBin Meng char rx_buff[PCH_GBE_DESC_NUM][PCH_GBE_RX_FRAME_LEN]; 2898ee443b8SBin Meng struct phy_device *phydev; 2908ee443b8SBin Meng struct mii_dev *bus; 2918ee443b8SBin Meng struct pch_gbe_regs *mac_regs; 292c52ac3f9SBin Meng struct udevice *dev; 2938ee443b8SBin Meng int rx_idx; 2948ee443b8SBin Meng int tx_idx; 2958ee443b8SBin Meng }; 2968ee443b8SBin Meng 2978ee443b8SBin Meng #endif /* _PCH_GBE_H_ */ 298