cache\-unified (full) in projects: openbmc

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/openbmc/linux/tools/perf/pmu-events/arch/arm64/
H A D	recommended.json	3 "PublicDescription": "Attributable Level 1 data cache access, read", 6 "BriefDescription": "L1D cache access, read" 9 "PublicDescription": "Attributable Level 1 data cache access, write", 12 "BriefDescription": "L1D cache access, write" 15 "PublicDescription": "Attributable Level 1 data cache refill, read", 18 "BriefDescription": "L1D cache refill, read" 21 "PublicDescription": "Attributable Level 1 data cache refill, write", 24 "BriefDescription": "L1D cache refill, write" 27 "PublicDescription": "Attributable Level 1 data cache refill, inner", 30 "BriefDescription": "L1D cache refill, inner" [all …]
H A D	common-and-microarch.json	9 "PublicDescription": "Level 1 instruction cache refill", 12 "BriefDescription": "Level 1 instruction cache refill" 21 "PublicDescription": "Level 1 data cache refill", 24 "BriefDescription": "Level 1 data cache refill" 27 "PublicDescription": "Level 1 data cache access", 30 "BriefDescription": "Level 1 data cache access" 123 "PublicDescription": "Attributable Level 1 instruction cache access", 126 "BriefDescription": "Attributable Level 1 instruction cache access" 129 "PublicDescription": "Attributable Level 1 data cache write-back", 132 "BriefDescription": "Attributable Level 1 data cache write-back" [all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/
H A D	l2_cache.json	4 …cache accesses. level 2 cache is a unified cache for data and instruction accesses. Accesses are f… 8 …"PublicDescription": "Counts cache line refills into the level 2 cache. level 2 cache is a unified… 12 …-backs of data from the L2 cache to outside the CPU. This includes snoops to the L2 (from other CP… 20 …"PublicDescription": "Counts level 2 cache accesses due to memory read operations. level 2 cache i… 24 …"PublicDescription": "Counts level 2 cache accesses due to memory write operations. level 2 cache … 28 …s due to memory read operation counted by L2D_CACHE_RD. level 2 cache is a unified cache for data … 32 … due to memory write operation counted by L2D_CACHE_WR. level 2 cache is a unified cache for data … 36 …escription": "Counts evictions from the level 2 cache because of a line being allocated into the L… 40 …s write-backs from the level 2 cache that are a result of either:\n\n1. Cache maintenance operatio… 44 …cache line in the level 2 cache by cache maintenance operations that operate by a virtual address,… [all …]
H A D	metrics.json	4 …"MetricExpr": "(100 * ((STALL_SLOT_BACKEND / (CPU_CYCLES * #slots)) - ((BR_MIS_PRED * 3) / CPU_CYC… 15 …0 * (((1 - (OP_RETIRED / OP_SPEC)) * (1 - (((STALL_SLOT) if (strcmp_cpuid_str(0x410fd493) \| strcmp… 61 …mp_cpuid_str(0x410fd490) ^ 1) else (STALL_SLOT_FRONTEND - CPU_CYCLES)) / (CPU_CYCLES * #slots)) - … 101 …ata cache accesses missed to the total number of level 1 data cache accesses. This gives an indica… 103 "ScaleUnit": "1per cache access" 108 …"BriefDescription": "This metric measures the number of level 1 data cache accesses missed per tho… 129 …cache accesses missed to the total number of level 1 instruction cache accesses. This gives an ind… 131 "ScaleUnit": "1per cache access" 136 …"BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed … 157 …cache accesses missed to the total number of level 2 cache accesses. This gives an indication of t… [all …]
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
H A D	l2_cache.json	4 …cache accesses. level 2 cache is a unified cache for data and instruction accesses. Accesses are f… 8 …"PublicDescription": "Counts cache line refills into the level 2 cache. level 2 cache is a unified… 12 …-backs of data from the L2 cache to outside the CPU. This includes snoops to the L2 (from other CP… 20 …"PublicDescription": "Counts level 2 cache accesses due to memory read operations. level 2 cache i… 24 …"PublicDescription": "Counts level 2 cache accesses due to memory write operations. level 2 cache … 28 …s due to memory read operation counted by L2D_CACHE_RD. level 2 cache is a unified cache for data … 32 … due to memory write operation counted by L2D_CACHE_WR. level 2 cache is a unified cache for data … 36 …escription": "Counts evictions from the level 2 cache because of a line being allocated into the L… 40 …s write-backs from the level 2 cache that are a result of either:\n\n1. Cache maintenance operatio… 44 …cache line in the level 2 cache by cache maintenance operations that operate by a virtual address,…
H A D	metrics.json	89 …ata cache accesses missed to the total number of level 1 data cache accesses. This gives an indica… 91 "ScaleUnit": "1per cache access" 96 …"BriefDescription": "This metric measures the number of level 1 data cache accesses missed per tho… 117 …cache accesses missed to the total number of level 1 instruction cache accesses. This gives an ind… 119 "ScaleUnit": "1per cache access" 124 …"BriefDescription": "This metric measures the number of level 1 instruction cache accesses missed … 145 …cache accesses missed to the total number of level 2 cache accesses. This gives an indication of t… 147 "ScaleUnit": "1per cache access" 152 …unified cache accesses missed per thousand instructions executed. Note that cache accesses in this… 159 …"This metric measures the ratio of level 2 unified TLB accesses missed to the total number of leve… [all …]
/openbmc/linux/Documentation/devicetree/bindings/cache/
H A D	socionext,uniphier-system-cache.yaml	1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: UniPhier outer cache controller 10 UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache 11 controller system. All of them have a level 2 cache controller, and some 12 have a level 3 cache controller as well. 15 - Masahiro Yamada <yamada.masahiro@socionext.com> 19 const: socionext,uniphier-system-cache [all …]
H A D	andestech,ax45mp-cache.yaml	1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Andestech AX45MP L2 Cache Controller 11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> 14 A level-2 cache (L2C) is used to improve the system performance by providing 15 a large amount of cache line entries and reasonable access delays. The L2C 16 is shared between cores, and a non-inclusive non-exclusive policy is used. 23 - andestech,ax45mp-cache [all …]
H A D	sifive,ccache0.yaml	1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/cache/sifive,ccache0.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: SiFive Composable Cache Controller 11 - Paul Walmsley <paul.walmsley@sifive.com> 14 The SiFive Composable Cache Controller is used to provide access to fast copies 15 of memory for masters in a Core Complex. The Composable Cache Controller also 16 acts as directory-based coherency manager. 24 - sifive,ccache0 [all …]
/openbmc/linux/Documentation/devicetree/bindings/cpufreq/
H A D	cpufreq-qcom-hw.yaml	`1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 21 - description: v1 of CPUFREQ HW 23 - enum: 24 - qcom,qcm2290-cpufreq-hw 25 - qcom,sc7180-cpufreq-hw 26 - qcom,sdm845-cpufreq-hw [all …]`
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A D	sm4450.dtsi	`1 // SPDX-License-Identifier: BSD-3-Clause 6 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 interrupt-parent = <&intc>; 12 #address-cells = <2>; 13 #size-cells = <2>; 18 xo_board: xo-board { 19 compatible = "fixed-clock"; 20 clock-frequency = <76800000>; 21 #clock-cells = <0>; [all …]`
/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z10/
H A D	basic.json	3 "Unit": "CPU-M-CF", 10 "Unit": "CPU-M-CF", 17 "Unit": "CPU-M-CF", 20 "BriefDescription": "Level-1 I-Cache Directory Write Count", 21 …scription": "This counter counts the total number of level-1 instruction-cache or unified-cache di… 24 "Unit": "CPU-M-CF", 27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", 28 …: "This counter counts the total number of cache penalty cycles for level-1 instruction cache or u… 31 "Unit": "CPU-M-CF", 34 "BriefDescription": "Level-1 D-Cache Directory Write Count", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z13/
H A D	basic.json	3 "Unit": "CPU-M-CF", 10 "Unit": "CPU-M-CF", 17 "Unit": "CPU-M-CF", 20 "BriefDescription": "Level-1 I-Cache Directory Write Count", 21 …scription": "This counter counts the total number of level-1 instruction-cache or unified-cache di… 24 "Unit": "CPU-M-CF", 27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", 28 …: "This counter counts the total number of cache penalty cycles for level-1 instruction cache or u… 31 "Unit": "CPU-M-CF", 34 "BriefDescription": "Level-1 D-Cache Directory Write Count", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z196/
H A D	basic.json	3 "Unit": "CPU-M-CF", 10 "Unit": "CPU-M-CF", 17 "Unit": "CPU-M-CF", 20 "BriefDescription": "Level-1 I-Cache Directory Write Count", 21 …scription": "This counter counts the total number of level-1 instruction-cache or unified-cache di… 24 "Unit": "CPU-M-CF", 27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", 28 …: "This counter counts the total number of cache penalty cycles for level-1 instruction cache or u… 31 "Unit": "CPU-M-CF", 34 "BriefDescription": "Level-1 D-Cache Directory Write Count", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_zec12/
H A D	basic.json	3 "Unit": "CPU-M-CF", 10 "Unit": "CPU-M-CF", 17 "Unit": "CPU-M-CF", 20 "BriefDescription": "Level-1 I-Cache Directory Write Count", 21 …scription": "This counter counts the total number of level-1 instruction-cache or unified-cache di… 24 "Unit": "CPU-M-CF", 27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", 28 …: "This counter counts the total number of cache penalty cycles for level-1 instruction cache or u… 31 "Unit": "CPU-M-CF", 34 "BriefDescription": "Level-1 D-Cache Directory Write Count", [all …]
/openbmc/linux/arch/arm64/boot/dts/amd/
H A D	amd-seattle-cpus.dtsi	`1 // SPDX-License-Identifier: GPL-2.0 5 #address-cells = <0x1>; 6 #size-cells = <0x0>; 8 cpu-map { 45 compatible = "arm,cortex-a57"; 47 enable-method = "psci"; 49 i-cache-size = <0xC000>; 50 i-cache-line-size = <64>; 51 i-cache-sets = <256>; 52 d-cache-size = <0x8000>; [all …]`
/openbmc/linux/arch/m68k/include/asm/
H A D	m53xxacr.h	1 /* SPDX-License-Identifier: GPL-2.0 / 5 m53xxacr.h -- ColdFire version 3 core cache support 17 * cache setup. They have a unified instruction and data cache, with 18 * configurable write-through or copy-back operation. 22 * Define the Cache Control register flags. 24 #define CACR_EC 0x80000000 /* Enable cache / 27 #define CACR_HLCK 0x08000000 / Half cache lock mode / 28 #define CACR_CINVA 0x01000000 / Invalidate cache / 30 #define CACR_DCM_WT 0x00000000 / Cacheable write-through / 31 #define CACR_DCM_CB 0x00000100 / Cacheable copy-back */ [all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A D	fsl-ls2080a.dtsi	`1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for Freescale Layerscape-2080A family SoC. 5 * Copyright 2014-2016 Freescale Semiconductor, Inc. 12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 13 #include "fsl-ls208xa.dtsi" 18 compatible = "arm,cortex-a57"; 21 cpu-idle-states = <&CPU_PW20>; 22 next-level-cache = <&cluster0_l2>; 23 #cooling-cells = <2>; 28 compatible = "arm,cortex-a57"; [all …]`
H A D	fsl-ls2088a.dtsi	`1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 3 * Device Tree Include file for Freescale Layerscape-2088A family SoC. 12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h> 13 #include "fsl-ls208xa.dtsi" 18 compatible = "arm,cortex-a72"; 21 cpu-idle-states = <&CPU_PW20>; 22 next-level-cache = <&cluster0_l2>; 23 #cooling-cells = <2>; 28 compatible = "arm,cortex-a72"; 31 cpu-idle-states = <&CPU_PW20>; [all …]`
/openbmc/linux/arch/arm64/boot/dts/ti/
H A D	k3-am654.dtsi	`1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ 8 #include "k3-am65.dtsi" 12 #address-cells = <1>; 13 #size-cells = <0>; 14 cpu-map { 37 compatible = "arm,cortex-a53"; 40 enable-method = "psci"; 41 i-cache-size = <0x8000>; 42 i-cache-line-size = <64>; [all …]`
/openbmc/linux/arch/arm/mm/
H A D	cache-v6.S	`1 /* SPDX-License-Identifier: GPL-2.0-only / 3 linux/arch/arm/mm/cache-v6.S 15 #include "proc-macros.S" 27 * Flush the whole I-cache. 29 * ARM1136 erratum 411920 - Invalidate Instruction Cache operation can fail. 34 * r0 - set to 0 35 * r1 - corrupted 42 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache 44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache [all …]`
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/
H A D	cache.json	3 "PublicDescription": "This event counts any instruction fetch which misses in the cache.", 15 …r store operation or page table walk access which looks up in the L1 data cache. In particular, an… 23 …on cache access or Level 0 Macro-op cache access. This event counts any instruction fetch which ac… 27 …t counts any write-back of data from the L1 data cache to L2 or L3. This counts both victim line e… 31 …from L1 which looks up in the L2 cache, and any write-back from the L1 to the L2. Snoops from outs… 35 …"PublicDescription": "L2 data cache refill. This event counts any cacheable transaction from L1 wh… 39 …"PublicDescription": "This event counts any write-back of data from the L2 cache to outside the co… 43 …ent counts any full cache line write into the L2 cache which does not cause a linefill, including … 57 …ent counts any full cache line write into the L3 cache which does not cause a linefill, including … 64 "BriefDescription": "Attributable Level 3 unified cache refill." [all …]
/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z16/
H A D	basic.json	3 "Unit": "CPU-M-CF", 10 "Unit": "CPU-M-CF", 17 "Unit": "CPU-M-CF", 20 "BriefDescription": "Level-1 I-Cache Directory Write Count", 21 …scription": "This counter counts the total number of level-1 instruction-cache or unified-cache di… 24 "Unit": "CPU-M-CF", 27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", 28 …: "This counter counts the total number of cache penalty cycles for level-1 instruction cache or u… 31 "Unit": "CPU-M-CF", 34 "BriefDescription": "Level-1 D-Cache Directory Write Count", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z14/
H A D	basic.json	3 "Unit": "CPU-M-CF", 10 "Unit": "CPU-M-CF", 17 "Unit": "CPU-M-CF", 20 "BriefDescription": "Level-1 I-Cache Directory Write Count", 21 …scription": "This counter counts the total number of level-1 instruction-cache or unified-cache di… 24 "Unit": "CPU-M-CF", 27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", 28 …: "This counter counts the total number of cache penalty cycles for level-1 instruction cache or u… 31 "Unit": "CPU-M-CF", 34 "BriefDescription": "Level-1 D-Cache Directory Write Count", [all …]
/openbmc/linux/tools/perf/pmu-events/arch/s390/cf_z15/
H A D	basic.json	3 "Unit": "CPU-M-CF", 10 "Unit": "CPU-M-CF", 17 "Unit": "CPU-M-CF", 20 "BriefDescription": "Level-1 I-Cache Directory Write Count", 21 …scription": "This counter counts the total number of level-1 instruction-cache or unified-cache di… 24 "Unit": "CPU-M-CF", 27 "BriefDescription": "Level-1 I-Cache Penalty Cycle Count", 28 …: "This counter counts the total number of cache penalty cycles for level-1 instruction cache or u… 31 "Unit": "CPU-M-CF", 34 "BriefDescription": "Level-1 D-Cache Directory Write Count", [all …]

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