1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2278c2cbdSGreg Ungerer /****************************************************************************/ 3278c2cbdSGreg Ungerer 4278c2cbdSGreg Ungerer /* 5278c2cbdSGreg Ungerer * m53xxacr.h -- ColdFire version 3 core cache support 6278c2cbdSGreg Ungerer * 7278c2cbdSGreg Ungerer * (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com> 8278c2cbdSGreg Ungerer */ 9278c2cbdSGreg Ungerer 10278c2cbdSGreg Ungerer /****************************************************************************/ 11278c2cbdSGreg Ungerer #ifndef m53xxacr_h 12278c2cbdSGreg Ungerer #define m53xxacr_h 13278c2cbdSGreg Ungerer /****************************************************************************/ 14278c2cbdSGreg Ungerer 15278c2cbdSGreg Ungerer /* 16278c2cbdSGreg Ungerer * All varients of the ColdFire using version 3 cores have a similar 17278c2cbdSGreg Ungerer * cache setup. They have a unified instruction and data cache, with 18278c2cbdSGreg Ungerer * configurable write-through or copy-back operation. 19278c2cbdSGreg Ungerer */ 20278c2cbdSGreg Ungerer 21278c2cbdSGreg Ungerer /* 22278c2cbdSGreg Ungerer * Define the Cache Control register flags. 23278c2cbdSGreg Ungerer */ 24278c2cbdSGreg Ungerer #define CACR_EC 0x80000000 /* Enable cache */ 25278c2cbdSGreg Ungerer #define CACR_ESB 0x20000000 /* Enable store buffer */ 26278c2cbdSGreg Ungerer #define CACR_DPI 0x10000000 /* Disable invalidation by CPUSHL */ 27278c2cbdSGreg Ungerer #define CACR_HLCK 0x08000000 /* Half cache lock mode */ 28278c2cbdSGreg Ungerer #define CACR_CINVA 0x01000000 /* Invalidate cache */ 29278c2cbdSGreg Ungerer #define CACR_DNFB 0x00000400 /* Inhibited fill buffer */ 30278c2cbdSGreg Ungerer #define CACR_DCM_WT 0x00000000 /* Cacheable write-through */ 31278c2cbdSGreg Ungerer #define CACR_DCM_CB 0x00000100 /* Cacheable copy-back */ 32278c2cbdSGreg Ungerer #define CACR_DCM_PRE 0x00000200 /* Cache inhibited, precise */ 33278c2cbdSGreg Ungerer #define CACR_DCM_IMPRE 0x00000300 /* Cache inhibited, imprecise */ 34278c2cbdSGreg Ungerer #define CACR_WPROTECT 0x00000020 /* Write protect*/ 35278c2cbdSGreg Ungerer #define CACR_EUSP 0x00000010 /* Eanble separate user a7 */ 36278c2cbdSGreg Ungerer 37278c2cbdSGreg Ungerer /* 38278c2cbdSGreg Ungerer * Define the Access Control register flags. 39278c2cbdSGreg Ungerer */ 40278c2cbdSGreg Ungerer #define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */ 41278c2cbdSGreg Ungerer #define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */ 42278c2cbdSGreg Ungerer #define ACR_ENABLE 0x00008000 /* Enable this ACR */ 43278c2cbdSGreg Ungerer #define ACR_USER 0x00000000 /* Allow only user accesses */ 44278c2cbdSGreg Ungerer #define ACR_SUPER 0x00002000 /* Allow supervisor access only */ 45278c2cbdSGreg Ungerer #define ACR_ANY 0x00004000 /* Allow any access type */ 46278c2cbdSGreg Ungerer #define ACR_CM_WT 0x00000000 /* Cacheable, write-through */ 47278c2cbdSGreg Ungerer #define ACR_CM_CB 0x00000020 /* Cacheable, copy-back */ 48278c2cbdSGreg Ungerer #define ACR_CM_PRE 0x00000040 /* Cache inhibited, precise */ 49278c2cbdSGreg Ungerer #define ACR_CM_IMPRE 0x00000060 /* Cache inhibited, imprecise */ 50278c2cbdSGreg Ungerer #define ACR_WPROTECT 0x00000004 /* Write protect region */ 51278c2cbdSGreg Ungerer 528ce877a8SGreg Ungerer /* 5307ffee59SGreg Ungerer * Define the cache type and arrangement (needed for pushes). 5407ffee59SGreg Ungerer */ 5507ffee59SGreg Ungerer #if defined(CONFIG_M5307) 5607ffee59SGreg Ungerer #define CACHE_SIZE 0x2000 /* 8k of unified cache */ 5707ffee59SGreg Ungerer #define ICACHE_SIZE CACHE_SIZE 5807ffee59SGreg Ungerer #define DCACHE_SIZE CACHE_SIZE 596eac4027SGreg Ungerer #elif defined(CONFIG_M53xx) 606eac4027SGreg Ungerer #define CACHE_SIZE 0x4000 /* 16k of unified cache */ 6107ffee59SGreg Ungerer #define ICACHE_SIZE CACHE_SIZE 6207ffee59SGreg Ungerer #define DCACHE_SIZE CACHE_SIZE 6307ffee59SGreg Ungerer #endif 6407ffee59SGreg Ungerer 6507ffee59SGreg Ungerer #define CACHE_LINE_SIZE 16 /* 16 byte line size */ 6607ffee59SGreg Ungerer #define CACHE_WAYS 4 /* 4 ways - set associative */ 6707ffee59SGreg Ungerer 6807ffee59SGreg Ungerer /* 698ce877a8SGreg Ungerer * Set the cache controller settings we will use. This default in the 708ce877a8SGreg Ungerer * CACR is cache inhibited, we use the ACR register to set cacheing 718ce877a8SGreg Ungerer * enabled on the regions we want (eg RAM). 728ce877a8SGreg Ungerer */ 734a5bae41SGreg Ungerer #if defined(CONFIG_CACHE_COPYBACK) 744a5bae41SGreg Ungerer #define CACHE_TYPE ACR_CM_CB 7507ffee59SGreg Ungerer #define CACHE_PUSH 764a5bae41SGreg Ungerer #else 774a5bae41SGreg Ungerer #define CACHE_TYPE ACR_CM_WT 784a5bae41SGreg Ungerer #endif 794a5bae41SGreg Ungerer 808ce877a8SGreg Ungerer #ifdef CONFIG_COLDFIRE_SW_A7 818ce877a8SGreg Ungerer #define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE) 828ce877a8SGreg Ungerer #else 838ce877a8SGreg Ungerer #define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE + CACR_EUSP) 848ce877a8SGreg Ungerer #endif 858ce877a8SGreg Ungerer 8607ffee59SGreg Ungerer /* 8707ffee59SGreg Ungerer * Unified cache means we will never need to flush for coherency of 8807ffee59SGreg Ungerer * instruction fetch. We will need to flush to maintain memory/DMA 8907ffee59SGreg Ungerer * coherency though in all cases. And for copyback caches we will need 9007ffee59SGreg Ungerer * to push cached data as well. 9107ffee59SGreg Ungerer */ 92*bdee0e79SGreg Ungerer #define CACHE_INIT (CACHE_MODE + CACR_CINVA - CACR_EC) 93*bdee0e79SGreg Ungerer #define CACHE_INVALIDATE (CACHE_MODE + CACR_CINVA) 94*bdee0e79SGreg Ungerer #define CACHE_INVALIDATED (CACHE_MODE + CACR_CINVA) 958ce877a8SGreg Ungerer 968ce877a8SGreg Ungerer #define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \ 978ce877a8SGreg Ungerer (0x000f0000) + \ 984a5bae41SGreg Ungerer (ACR_ENABLE + ACR_ANY + CACHE_TYPE)) 998ce877a8SGreg Ungerer #define ACR1_MODE 0 1008ce877a8SGreg Ungerer 101278c2cbdSGreg Ungerer /****************************************************************************/ 102278c2cbdSGreg Ungerer #endif /* m53xxsim_h */ 103