1*dc8ea920SConor Dooley# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2*dc8ea920SConor Dooley%YAML 1.2 3*dc8ea920SConor Dooley--- 4*dc8ea920SConor Dooley$id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml# 5*dc8ea920SConor Dooley$schema: http://devicetree.org/meta-schemas/core.yaml# 6*dc8ea920SConor Dooley 7*dc8ea920SConor Dooleytitle: UniPhier outer cache controller 8*dc8ea920SConor Dooley 9*dc8ea920SConor Dooleydescription: | 10*dc8ea920SConor Dooley UniPhier ARM 32-bit SoCs are integrated with a full-custom outer cache 11*dc8ea920SConor Dooley controller system. All of them have a level 2 cache controller, and some 12*dc8ea920SConor Dooley have a level 3 cache controller as well. 13*dc8ea920SConor Dooley 14*dc8ea920SConor Dooleymaintainers: 15*dc8ea920SConor Dooley - Masahiro Yamada <yamada.masahiro@socionext.com> 16*dc8ea920SConor Dooley 17*dc8ea920SConor Dooleyproperties: 18*dc8ea920SConor Dooley compatible: 19*dc8ea920SConor Dooley const: socionext,uniphier-system-cache 20*dc8ea920SConor Dooley 21*dc8ea920SConor Dooley reg: 22*dc8ea920SConor Dooley description: | 23*dc8ea920SConor Dooley should contain 3 regions: control register, revision register, 24*dc8ea920SConor Dooley operation register, in this order. 25*dc8ea920SConor Dooley maxItems: 3 26*dc8ea920SConor Dooley 27*dc8ea920SConor Dooley interrupts: 28*dc8ea920SConor Dooley description: | 29*dc8ea920SConor Dooley Interrupts can be used to notify the completion of cache operations. 30*dc8ea920SConor Dooley The number of interrupts should match to the number of CPU cores. 31*dc8ea920SConor Dooley The specified interrupts correspond to CPU0, CPU1, ... in this order. 32*dc8ea920SConor Dooley minItems: 1 33*dc8ea920SConor Dooley maxItems: 4 34*dc8ea920SConor Dooley 35*dc8ea920SConor Dooley cache-unified: true 36*dc8ea920SConor Dooley 37*dc8ea920SConor Dooley cache-size: true 38*dc8ea920SConor Dooley 39*dc8ea920SConor Dooley cache-sets: true 40*dc8ea920SConor Dooley 41*dc8ea920SConor Dooley cache-line-size: true 42*dc8ea920SConor Dooley 43*dc8ea920SConor Dooley cache-level: 44*dc8ea920SConor Dooley minimum: 2 45*dc8ea920SConor Dooley maximum: 3 46*dc8ea920SConor Dooley 47*dc8ea920SConor Dooley next-level-cache: true 48*dc8ea920SConor Dooley 49*dc8ea920SConor DooleyallOf: 50*dc8ea920SConor Dooley - $ref: /schemas/cache-controller.yaml# 51*dc8ea920SConor Dooley 52*dc8ea920SConor DooleyadditionalProperties: false 53*dc8ea920SConor Dooley 54*dc8ea920SConor Dooleyrequired: 55*dc8ea920SConor Dooley - compatible 56*dc8ea920SConor Dooley - reg 57*dc8ea920SConor Dooley - interrupts 58*dc8ea920SConor Dooley - cache-unified 59*dc8ea920SConor Dooley - cache-size 60*dc8ea920SConor Dooley - cache-sets 61*dc8ea920SConor Dooley - cache-line-size 62*dc8ea920SConor Dooley - cache-level 63*dc8ea920SConor Dooley 64*dc8ea920SConor Dooleyexamples: 65*dc8ea920SConor Dooley - | 66*dc8ea920SConor Dooley // System with L2. 67*dc8ea920SConor Dooley cache-controller@500c0000 { 68*dc8ea920SConor Dooley compatible = "socionext,uniphier-system-cache"; 69*dc8ea920SConor Dooley reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, <0x506c0000 0x400>; 70*dc8ea920SConor Dooley interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; 71*dc8ea920SConor Dooley cache-unified; 72*dc8ea920SConor Dooley cache-size = <0x140000>; 73*dc8ea920SConor Dooley cache-sets = <512>; 74*dc8ea920SConor Dooley cache-line-size = <128>; 75*dc8ea920SConor Dooley cache-level = <2>; 76*dc8ea920SConor Dooley }; 77*dc8ea920SConor Dooley - | 78*dc8ea920SConor Dooley // System with L2 and L3. 79*dc8ea920SConor Dooley // L2 should specify the next level cache by 'next-level-cache'. 80*dc8ea920SConor Dooley l2: cache-controller@500c0000 { 81*dc8ea920SConor Dooley compatible = "socionext,uniphier-system-cache"; 82*dc8ea920SConor Dooley reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, <0x506c0000 0x400>; 83*dc8ea920SConor Dooley interrupts = <0 190 4>, <0 191 4>; 84*dc8ea920SConor Dooley cache-unified; 85*dc8ea920SConor Dooley cache-size = <0x200000>; 86*dc8ea920SConor Dooley cache-sets = <512>; 87*dc8ea920SConor Dooley cache-line-size = <128>; 88*dc8ea920SConor Dooley cache-level = <2>; 89*dc8ea920SConor Dooley next-level-cache = <&l3>; 90*dc8ea920SConor Dooley }; 91*dc8ea920SConor Dooley 92*dc8ea920SConor Dooley l3: cache-controller@500c8000 { 93*dc8ea920SConor Dooley compatible = "socionext,uniphier-system-cache"; 94*dc8ea920SConor Dooley reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, <0x506c8000 0x400>; 95*dc8ea920SConor Dooley interrupts = <0 174 4>, <0 175 4>; 96*dc8ea920SConor Dooley cache-unified; 97*dc8ea920SConor Dooley cache-size = <0x200000>; 98*dc8ea920SConor Dooley cache-sets = <512>; 99*dc8ea920SConor Dooley cache-line-size = <256>; 100*dc8ea920SConor Dooley cache-level = <3>; 101*dc8ea920SConor Dooley }; 102