bindings/cache/andestech%2Cax45mp-cache.yaml

1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/cache/andestech,ax45mp-cache.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Andestech AX45MP L2 Cache Controller
11   - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
14   A level-2 cache (L2C) is used to improve the system performance by providing
15   a large amount of cache line entries and reasonable access delays. The L2C
16   is shared between cores, and a non-inclusive non-exclusive policy is used.
23           - andestech,ax45mp-cache
26     - compatible
31       - const: andestech,ax45mp-cache
32       - const: cache
40   cache-line-size:
43   cache-level:
46   cache-sets:
49   cache-size:
52   cache-unified: true
54   next-level-cache: true
59   - compatible
60   - reg
61   - interrupts
62   - cache-line-size
63   - cache-level
64   - cache-sets
65   - cache-size
66   - cache-unified
69   - |
70     #include <dt-bindings/interrupt-controller/irq.h>
72     cache-controller@13400000 {
73         compatible = "andestech,ax45mp-cache", "cache";
76         cache-line-size = <64>;
77         cache-level = <2>;
78         cache-sets = <1024>;
79         cache-size = <262144>;
80         cache-unified;