Lines Matching +full:cache +full:- +full:unified

1 /* SPDX-License-Identifier: GPL-2.0 */
5  * m53xxacr.h -- ColdFire version 3 core cache support
17  * cache setup. They have a unified instruction and data cache, with
18  * configurable write-through or copy-back operation.
22  * Define the Cache Control register flags.
24 #define CACR_EC		0x80000000	/* Enable cache */
27 #define CACR_HLCK	0x08000000	/* Half cache lock mode */
28 #define CACR_CINVA	0x01000000	/* Invalidate cache */
30 #define CACR_DCM_WT	0x00000000	/* Cacheable write-through */
31 #define CACR_DCM_CB	0x00000100	/* Cacheable copy-back */
32 #define CACR_DCM_PRE	0x00000200	/* Cache inhibited, precise */
33 #define CACR_DCM_IMPRE	0x00000300	/* Cache inhibited, imprecise */
46 #define ACR_CM_WT	0x00000000	/* Cacheable, write-through */
47 #define ACR_CM_CB	0x00000020	/* Cacheable, copy-back */
48 #define ACR_CM_PRE	0x00000040	/* Cache inhibited, precise */
49 #define ACR_CM_IMPRE	0x00000060	/* Cache inhibited, imprecise */
53  * Define the cache type and arrangement (needed for pushes).
56 #define	CACHE_SIZE	0x2000		/* 8k of unified cache */
60 #define	CACHE_SIZE	0x4000		/* 16k of unified cache */
66 #define	CACHE_WAYS	4		/* 4 ways - set associative */
69  * Set the cache controller settings we will use. This default in the
70  * CACR is cache inhibited, we use the ACR register to set cacheing
87  * Unified cache means we will never need to flush for coherency of
92 #define CACHE_INIT        (CACHE_MODE + CACR_CINVA - CACR_EC)