1*6a2f0b2dSArd Biesheuvel// SPDX-License-Identifier: GPL-2.0 2*6a2f0b2dSArd Biesheuvel 3*6a2f0b2dSArd Biesheuvel/ { 4*6a2f0b2dSArd Biesheuvel cpus { 5*6a2f0b2dSArd Biesheuvel #address-cells = <0x1>; 6*6a2f0b2dSArd Biesheuvel #size-cells = <0x0>; 7*6a2f0b2dSArd Biesheuvel 8*6a2f0b2dSArd Biesheuvel cpu-map { 9*6a2f0b2dSArd Biesheuvel cluster0 { 10*6a2f0b2dSArd Biesheuvel core0 { 11*6a2f0b2dSArd Biesheuvel cpu = <&CPU0>; 12*6a2f0b2dSArd Biesheuvel }; 13*6a2f0b2dSArd Biesheuvel core1 { 14*6a2f0b2dSArd Biesheuvel cpu = <&CPU1>; 15*6a2f0b2dSArd Biesheuvel }; 16*6a2f0b2dSArd Biesheuvel }; 17*6a2f0b2dSArd Biesheuvel cluster1 { 18*6a2f0b2dSArd Biesheuvel core0 { 19*6a2f0b2dSArd Biesheuvel cpu = <&CPU2>; 20*6a2f0b2dSArd Biesheuvel }; 21*6a2f0b2dSArd Biesheuvel core1 { 22*6a2f0b2dSArd Biesheuvel cpu = <&CPU3>; 23*6a2f0b2dSArd Biesheuvel }; 24*6a2f0b2dSArd Biesheuvel }; 25*6a2f0b2dSArd Biesheuvel cluster2 { 26*6a2f0b2dSArd Biesheuvel core0 { 27*6a2f0b2dSArd Biesheuvel cpu = <&CPU4>; 28*6a2f0b2dSArd Biesheuvel }; 29*6a2f0b2dSArd Biesheuvel core1 { 30*6a2f0b2dSArd Biesheuvel cpu = <&CPU5>; 31*6a2f0b2dSArd Biesheuvel }; 32*6a2f0b2dSArd Biesheuvel }; 33*6a2f0b2dSArd Biesheuvel cluster3 { 34*6a2f0b2dSArd Biesheuvel core0 { 35*6a2f0b2dSArd Biesheuvel cpu = <&CPU6>; 36*6a2f0b2dSArd Biesheuvel }; 37*6a2f0b2dSArd Biesheuvel core1 { 38*6a2f0b2dSArd Biesheuvel cpu = <&CPU7>; 39*6a2f0b2dSArd Biesheuvel }; 40*6a2f0b2dSArd Biesheuvel }; 41*6a2f0b2dSArd Biesheuvel }; 42*6a2f0b2dSArd Biesheuvel 43*6a2f0b2dSArd Biesheuvel CPU0: cpu@0 { 44*6a2f0b2dSArd Biesheuvel device_type = "cpu"; 45*6a2f0b2dSArd Biesheuvel compatible = "arm,cortex-a57"; 46*6a2f0b2dSArd Biesheuvel reg = <0x0>; 47*6a2f0b2dSArd Biesheuvel enable-method = "psci"; 48*6a2f0b2dSArd Biesheuvel 49*6a2f0b2dSArd Biesheuvel i-cache-size = <0xC000>; 50*6a2f0b2dSArd Biesheuvel i-cache-line-size = <64>; 51*6a2f0b2dSArd Biesheuvel i-cache-sets = <256>; 52*6a2f0b2dSArd Biesheuvel d-cache-size = <0x8000>; 53*6a2f0b2dSArd Biesheuvel d-cache-line-size = <64>; 54*6a2f0b2dSArd Biesheuvel d-cache-sets = <256>; 55*6a2f0b2dSArd Biesheuvel l2-cache = <&L2_0>; 56*6a2f0b2dSArd Biesheuvel 57*6a2f0b2dSArd Biesheuvel }; 58*6a2f0b2dSArd Biesheuvel 59*6a2f0b2dSArd Biesheuvel CPU1: cpu@1 { 60*6a2f0b2dSArd Biesheuvel device_type = "cpu"; 61*6a2f0b2dSArd Biesheuvel compatible = "arm,cortex-a57"; 62*6a2f0b2dSArd Biesheuvel reg = <0x1>; 63*6a2f0b2dSArd Biesheuvel enable-method = "psci"; 64*6a2f0b2dSArd Biesheuvel 65*6a2f0b2dSArd Biesheuvel i-cache-size = <0xC000>; 66*6a2f0b2dSArd Biesheuvel i-cache-line-size = <64>; 67*6a2f0b2dSArd Biesheuvel i-cache-sets = <256>; 68*6a2f0b2dSArd Biesheuvel d-cache-size = <0x8000>; 69*6a2f0b2dSArd Biesheuvel d-cache-line-size = <64>; 70*6a2f0b2dSArd Biesheuvel d-cache-sets = <256>; 71*6a2f0b2dSArd Biesheuvel l2-cache = <&L2_0>; 72*6a2f0b2dSArd Biesheuvel }; 73*6a2f0b2dSArd Biesheuvel 74*6a2f0b2dSArd Biesheuvel CPU2: cpu@100 { 75*6a2f0b2dSArd Biesheuvel device_type = "cpu"; 76*6a2f0b2dSArd Biesheuvel compatible = "arm,cortex-a57"; 77*6a2f0b2dSArd Biesheuvel reg = <0x100>; 78*6a2f0b2dSArd Biesheuvel enable-method = "psci"; 79*6a2f0b2dSArd Biesheuvel 80*6a2f0b2dSArd Biesheuvel i-cache-size = <0xC000>; 81*6a2f0b2dSArd Biesheuvel i-cache-line-size = <64>; 82*6a2f0b2dSArd Biesheuvel i-cache-sets = <256>; 83*6a2f0b2dSArd Biesheuvel d-cache-size = <0x8000>; 84*6a2f0b2dSArd Biesheuvel d-cache-line-size = <64>; 85*6a2f0b2dSArd Biesheuvel d-cache-sets = <256>; 86*6a2f0b2dSArd Biesheuvel l2-cache = <&L2_1>; 87*6a2f0b2dSArd Biesheuvel }; 88*6a2f0b2dSArd Biesheuvel 89*6a2f0b2dSArd Biesheuvel CPU3: cpu@101 { 90*6a2f0b2dSArd Biesheuvel device_type = "cpu"; 91*6a2f0b2dSArd Biesheuvel compatible = "arm,cortex-a57"; 92*6a2f0b2dSArd Biesheuvel reg = <0x101>; 93*6a2f0b2dSArd Biesheuvel enable-method = "psci"; 94*6a2f0b2dSArd Biesheuvel 95*6a2f0b2dSArd Biesheuvel i-cache-size = <0xC000>; 96*6a2f0b2dSArd Biesheuvel i-cache-line-size = <64>; 97*6a2f0b2dSArd Biesheuvel i-cache-sets = <256>; 98*6a2f0b2dSArd Biesheuvel d-cache-size = <0x8000>; 99*6a2f0b2dSArd Biesheuvel d-cache-line-size = <64>; 100*6a2f0b2dSArd Biesheuvel d-cache-sets = <256>; 101*6a2f0b2dSArd Biesheuvel l2-cache = <&L2_1>; 102*6a2f0b2dSArd Biesheuvel }; 103*6a2f0b2dSArd Biesheuvel 104*6a2f0b2dSArd Biesheuvel CPU4: cpu@200 { 105*6a2f0b2dSArd Biesheuvel device_type = "cpu"; 106*6a2f0b2dSArd Biesheuvel compatible = "arm,cortex-a57"; 107*6a2f0b2dSArd Biesheuvel reg = <0x200>; 108*6a2f0b2dSArd Biesheuvel enable-method = "psci"; 109*6a2f0b2dSArd Biesheuvel 110*6a2f0b2dSArd Biesheuvel i-cache-size = <0xC000>; 111*6a2f0b2dSArd Biesheuvel i-cache-line-size = <64>; 112*6a2f0b2dSArd Biesheuvel i-cache-sets = <256>; 113*6a2f0b2dSArd Biesheuvel d-cache-size = <0x8000>; 114*6a2f0b2dSArd Biesheuvel d-cache-line-size = <64>; 115*6a2f0b2dSArd Biesheuvel d-cache-sets = <256>; 116*6a2f0b2dSArd Biesheuvel l2-cache = <&L2_2>; 117*6a2f0b2dSArd Biesheuvel }; 118*6a2f0b2dSArd Biesheuvel 119*6a2f0b2dSArd Biesheuvel CPU5: cpu@201 { 120*6a2f0b2dSArd Biesheuvel device_type = "cpu"; 121*6a2f0b2dSArd Biesheuvel compatible = "arm,cortex-a57"; 122*6a2f0b2dSArd Biesheuvel reg = <0x201>; 123*6a2f0b2dSArd Biesheuvel enable-method = "psci"; 124*6a2f0b2dSArd Biesheuvel 125*6a2f0b2dSArd Biesheuvel i-cache-size = <0xC000>; 126*6a2f0b2dSArd Biesheuvel i-cache-line-size = <64>; 127*6a2f0b2dSArd Biesheuvel i-cache-sets = <256>; 128*6a2f0b2dSArd Biesheuvel d-cache-size = <0x8000>; 129*6a2f0b2dSArd Biesheuvel d-cache-line-size = <64>; 130*6a2f0b2dSArd Biesheuvel d-cache-sets = <256>; 131*6a2f0b2dSArd Biesheuvel l2-cache = <&L2_2>; 132*6a2f0b2dSArd Biesheuvel }; 133*6a2f0b2dSArd Biesheuvel 134*6a2f0b2dSArd Biesheuvel CPU6: cpu@300 { 135*6a2f0b2dSArd Biesheuvel device_type = "cpu"; 136*6a2f0b2dSArd Biesheuvel compatible = "arm,cortex-a57"; 137*6a2f0b2dSArd Biesheuvel reg = <0x300>; 138*6a2f0b2dSArd Biesheuvel enable-method = "psci"; 139*6a2f0b2dSArd Biesheuvel 140*6a2f0b2dSArd Biesheuvel i-cache-size = <0xC000>; 141*6a2f0b2dSArd Biesheuvel i-cache-line-size = <64>; 142*6a2f0b2dSArd Biesheuvel i-cache-sets = <256>; 143*6a2f0b2dSArd Biesheuvel d-cache-size = <0x8000>; 144*6a2f0b2dSArd Biesheuvel d-cache-line-size = <64>; 145*6a2f0b2dSArd Biesheuvel d-cache-sets = <256>; 146*6a2f0b2dSArd Biesheuvel l2-cache = <&L2_3>; 147*6a2f0b2dSArd Biesheuvel }; 148*6a2f0b2dSArd Biesheuvel 149*6a2f0b2dSArd Biesheuvel CPU7: cpu@301 { 150*6a2f0b2dSArd Biesheuvel device_type = "cpu"; 151*6a2f0b2dSArd Biesheuvel compatible = "arm,cortex-a57"; 152*6a2f0b2dSArd Biesheuvel reg = <0x301>; 153*6a2f0b2dSArd Biesheuvel enable-method = "psci"; 154*6a2f0b2dSArd Biesheuvel 155*6a2f0b2dSArd Biesheuvel i-cache-size = <0xC000>; 156*6a2f0b2dSArd Biesheuvel i-cache-line-size = <64>; 157*6a2f0b2dSArd Biesheuvel i-cache-sets = <256>; 158*6a2f0b2dSArd Biesheuvel d-cache-size = <0x8000>; 159*6a2f0b2dSArd Biesheuvel d-cache-line-size = <64>; 160*6a2f0b2dSArd Biesheuvel d-cache-sets = <256>; 161*6a2f0b2dSArd Biesheuvel l2-cache = <&L2_3>; 162*6a2f0b2dSArd Biesheuvel }; 163*6a2f0b2dSArd Biesheuvel }; 164*6a2f0b2dSArd Biesheuvel 165*6a2f0b2dSArd Biesheuvel L2_0: l2-cache0 { 166*6a2f0b2dSArd Biesheuvel cache-size = <0x100000>; 167*6a2f0b2dSArd Biesheuvel cache-line-size = <64>; 168*6a2f0b2dSArd Biesheuvel cache-sets = <1024>; 169*6a2f0b2dSArd Biesheuvel cache-unified; 170*6a2f0b2dSArd Biesheuvel next-level-cache = <&L3>; 171*6a2f0b2dSArd Biesheuvel }; 172*6a2f0b2dSArd Biesheuvel 173*6a2f0b2dSArd Biesheuvel L2_1: l2-cache1 { 174*6a2f0b2dSArd Biesheuvel cache-size = <0x100000>; 175*6a2f0b2dSArd Biesheuvel cache-line-size = <64>; 176*6a2f0b2dSArd Biesheuvel cache-sets = <1024>; 177*6a2f0b2dSArd Biesheuvel cache-unified; 178*6a2f0b2dSArd Biesheuvel next-level-cache = <&L3>; 179*6a2f0b2dSArd Biesheuvel }; 180*6a2f0b2dSArd Biesheuvel 181*6a2f0b2dSArd Biesheuvel L2_2: l2-cache2 { 182*6a2f0b2dSArd Biesheuvel cache-size = <0x100000>; 183*6a2f0b2dSArd Biesheuvel cache-line-size = <64>; 184*6a2f0b2dSArd Biesheuvel cache-sets = <1024>; 185*6a2f0b2dSArd Biesheuvel cache-unified; 186*6a2f0b2dSArd Biesheuvel next-level-cache = <&L3>; 187*6a2f0b2dSArd Biesheuvel }; 188*6a2f0b2dSArd Biesheuvel 189*6a2f0b2dSArd Biesheuvel L2_3: l2-cache3 { 190*6a2f0b2dSArd Biesheuvel cache-size = <0x100000>; 191*6a2f0b2dSArd Biesheuvel cache-line-size = <64>; 192*6a2f0b2dSArd Biesheuvel cache-sets = <1024>; 193*6a2f0b2dSArd Biesheuvel cache-unified; 194*6a2f0b2dSArd Biesheuvel next-level-cache = <&L3>; 195*6a2f0b2dSArd Biesheuvel }; 196*6a2f0b2dSArd Biesheuvel 197*6a2f0b2dSArd Biesheuvel L3: l3-cache { 198*6a2f0b2dSArd Biesheuvel cache-level = <3>; 199*6a2f0b2dSArd Biesheuvel cache-size = <0x800000>; 200*6a2f0b2dSArd Biesheuvel cache-line-size = <64>; 201*6a2f0b2dSArd Biesheuvel cache-sets = <8192>; 202*6a2f0b2dSArd Biesheuvel cache-unified; 203*6a2f0b2dSArd Biesheuvel }; 204*6a2f0b2dSArd Biesheuvel 205*6a2f0b2dSArd Biesheuvel pmu { 206*6a2f0b2dSArd Biesheuvel compatible = "arm,cortex-a57-pmu"; 207*6a2f0b2dSArd Biesheuvel interrupts = <0x0 0x7 0x4>, 208*6a2f0b2dSArd Biesheuvel <0x0 0x8 0x4>, 209*6a2f0b2dSArd Biesheuvel <0x0 0x9 0x4>, 210*6a2f0b2dSArd Biesheuvel <0x0 0xa 0x4>, 211*6a2f0b2dSArd Biesheuvel <0x0 0xb 0x4>, 212*6a2f0b2dSArd Biesheuvel <0x0 0xc 0x4>, 213*6a2f0b2dSArd Biesheuvel <0x0 0xd 0x4>, 214*6a2f0b2dSArd Biesheuvel <0x0 0xe 0x4>; 215*6a2f0b2dSArd Biesheuvel interrupt-affinity = <&CPU0>, 216*6a2f0b2dSArd Biesheuvel <&CPU1>, 217*6a2f0b2dSArd Biesheuvel <&CPU2>, 218*6a2f0b2dSArd Biesheuvel <&CPU3>, 219*6a2f0b2dSArd Biesheuvel <&CPU4>, 220*6a2f0b2dSArd Biesheuvel <&CPU5>, 221*6a2f0b2dSArd Biesheuvel <&CPU6>, 222*6a2f0b2dSArd Biesheuvel <&CPU7>; 223*6a2f0b2dSArd Biesheuvel }; 224*6a2f0b2dSArd Biesheuvel}; 225