10d0e5eceSThomas Richter[
20d0e5eceSThomas Richter	{
30d0e5eceSThomas Richter		"Unit": "CPU-M-CF",
40d0e5eceSThomas Richter		"EventCode": "0",
50d0e5eceSThomas Richter		"EventName": "CPU_CYCLES",
6*d1833463SThomas Richter		"BriefDescription": "Cycle Count",
7*d1833463SThomas Richter		"PublicDescription": "This counter counts the total number of CPU cycles, excluding the number of cycles while the CPU is in the wait state."
80d0e5eceSThomas Richter	},
90d0e5eceSThomas Richter	{
100d0e5eceSThomas Richter		"Unit": "CPU-M-CF",
110d0e5eceSThomas Richter		"EventCode": "1",
120d0e5eceSThomas Richter		"EventName": "INSTRUCTIONS",
13*d1833463SThomas Richter		"BriefDescription": "Instruction Count",
14*d1833463SThomas Richter		"PublicDescription": "This counter counts the total number of instructions executed by the CPU."
150d0e5eceSThomas Richter	},
160d0e5eceSThomas Richter	{
170d0e5eceSThomas Richter		"Unit": "CPU-M-CF",
180d0e5eceSThomas Richter		"EventCode": "2",
190d0e5eceSThomas Richter		"EventName": "L1I_DIR_WRITES",
20*d1833463SThomas Richter		"BriefDescription": "Level-1 I-Cache Directory Write Count",
21*d1833463SThomas Richter		"PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes."
220d0e5eceSThomas Richter	},
230d0e5eceSThomas Richter	{
240d0e5eceSThomas Richter		"Unit": "CPU-M-CF",
250d0e5eceSThomas Richter		"EventCode": "3",
260d0e5eceSThomas Richter		"EventName": "L1I_PENALTY_CYCLES",
27*d1833463SThomas Richter		"BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
28*d1833463SThomas Richter		"PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 instruction cache or unified cache."
290d0e5eceSThomas Richter	},
300d0e5eceSThomas Richter	{
310d0e5eceSThomas Richter		"Unit": "CPU-M-CF",
320d0e5eceSThomas Richter		"EventCode": "4",
330d0e5eceSThomas Richter		"EventName": "L1D_DIR_WRITES",
34*d1833463SThomas Richter		"BriefDescription": "Level-1 D-Cache Directory Write Count",
35*d1833463SThomas Richter		"PublicDescription": "This counter counts the total number of level-1 data-cache directory writes."
360d0e5eceSThomas Richter	},
370d0e5eceSThomas Richter	{
380d0e5eceSThomas Richter		"Unit": "CPU-M-CF",
390d0e5eceSThomas Richter		"EventCode": "5",
400d0e5eceSThomas Richter		"EventName": "L1D_PENALTY_CYCLES",
41*d1833463SThomas Richter		"BriefDescription": "Level-1 D-Cache Penalty Cycle Count",
42*d1833463SThomas Richter		"PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 data cache."
430d0e5eceSThomas Richter	},
440d0e5eceSThomas Richter	{
450d0e5eceSThomas Richter		"Unit": "CPU-M-CF",
460d0e5eceSThomas Richter		"EventCode": "32",
470d0e5eceSThomas Richter		"EventName": "PROBLEM_STATE_CPU_CYCLES",
48*d1833463SThomas Richter		"BriefDescription": "Problem-State Cycle Count",
49*d1833463SThomas Richter		"PublicDescription": "This counter counts the total number of CPU cycles when the CPU is in the problem state, excluding the number of cycles while the CPU is in the wait state."
500d0e5eceSThomas Richter	},
510d0e5eceSThomas Richter	{
520d0e5eceSThomas Richter		"Unit": "CPU-M-CF",
530d0e5eceSThomas Richter		"EventCode": "33",
540d0e5eceSThomas Richter		"EventName": "PROBLEM_STATE_INSTRUCTIONS",
55*d1833463SThomas Richter		"BriefDescription": "Problem-State Instruction Count",
56*d1833463SThomas Richter		"PublicDescription": "This counter counts the total number of instructions executed by the CPU while in the problem state."
5708f3e087SJames Clark	}
580d0e5eceSThomas Richter]
59