arm/mm/cache-v6.S

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  *  linux/arch/arm/mm/cache-v6.S
15 #include "proc-macros.S"
27  *	Flush the whole I-cache.
29  *	ARM1136 erratum 411920 - Invalidate Instruction Cache operation can fail.
34  *	r0 - set to 0
35  *	r1 - corrupted
42 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate entire I-cache
43 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate entire I-cache
44 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate entire I-cache
45 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate entire I-cache
51 	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I-cache
59  *	Flush the entire cache.
66 	mcr	p15, 0, r0, c7, c14, 0		@ D cache clean+invalidate
68 	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
73 	mcr	p15, 0, r0, c7, c15, 0		@ Cache clean+invalidate
82  *	- mm    - mm_struct describing address space
92  *	- start - start address (may not be aligned)
93  *	- end   - end address (exclusive, may not be aligned)
94  *	- flags	- vm_area_struct flags describing address space
97  *	- we have a VIPT cache.
109  *	- start   - virtual start address of region
110  *	- end     - virtual end address of region
113  *	- the Icache does not read data from the write buffer
125  *	- start   - virtual start address of region
126  *	- end     - virtual end address of region
129  *	- the Icache does not read data from the write buffer
134 	bic	r0, r0, #CACHE_LINE_SIZE - 1
145 	mcr	p15, 0, r0, c7, c5, 0		@ I+BTB cache invalidate
155  * Fault handling for the cache operation above. If the virtual address in r0
156  * isn't mapped, fail with -EFAULT.
159 	mov	r0, #-EFAULT
171  *	- addr	- kernel address
172  *	- size	- region size
176 	bic	r0, r0, #D_CACHE_LINE_SIZE - 1
181 	mcr	p15, 0, r0, c7, c15, 1		@ clean & invalidate unified line
196  *	Invalidate the data cache within the specified region; we will
198  *	purge old data in the cache.
200  *	- start   - virtual start address of region
201  *	- end     - virtual end address of region
208 	tst	r0, #D_CACHE_LINE_SIZE - 1
209 	bic	r0, r0, #D_CACHE_LINE_SIZE - 1
213 	mcrne	p15, 0, r0, c7, c11, 1		@ clean unified line
215 	tst	r1, #D_CACHE_LINE_SIZE - 1
217 	ldrbne	r2, [r1, #-1]			@ read for ownership
218 	strbne	r2, [r1, #-1]			@ write for ownership
220 	bic	r1, r1, #D_CACHE_LINE_SIZE - 1
224 	mcrne	p15, 0, r1, c7, c15, 1		@ clean & invalidate unified line
230 	mcr	p15, 0, r0, c7, c7, 1		@ invalidate unified line
245  *	- start   - virtual start address of region
246  *	- end     - virtual end address of region
249 	bic	r0, r0, #D_CACHE_LINE_SIZE - 1
257 	mcr	p15, 0, r0, c7, c11, 1		@ clean unified line
268  *	- start   - virtual start address of region
269  *	- end     - virtual end address of region
276 	bic	r0, r0, #D_CACHE_LINE_SIZE - 1
296  *	- start	- kernel virtual start address
297  *	- size	- size of region
298  *	- dir	- DMA direction
315  *	- start	- kernel virtual start address
316  *	- size	- size of region
317  *	- dir	- DMA direction
333 	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)