1109d59b9SThomas Richter[
2109d59b9SThomas Richter	{
39bacbcedSThomas Richter		"Unit": "CPU-M-CF",
4109d59b9SThomas Richter		"EventCode": "0",
5109d59b9SThomas Richter		"EventName": "CPU_CYCLES",
6*d786bdf2SThomas Richter		"BriefDescription": "Cycle Count",
7*d786bdf2SThomas Richter		"PublicDescription": "This counter counts the total number of CPU cycles, excluding the number of cycles while the CPU is in the wait state."
8109d59b9SThomas Richter	},
9109d59b9SThomas Richter	{
109bacbcedSThomas Richter		"Unit": "CPU-M-CF",
11109d59b9SThomas Richter		"EventCode": "1",
12109d59b9SThomas Richter		"EventName": "INSTRUCTIONS",
13*d786bdf2SThomas Richter		"BriefDescription": "Instruction Count",
14*d786bdf2SThomas Richter		"PublicDescription": "This counter counts the total number of instructions executed by the CPU."
15109d59b9SThomas Richter	},
16109d59b9SThomas Richter	{
179bacbcedSThomas Richter		"Unit": "CPU-M-CF",
18109d59b9SThomas Richter		"EventCode": "2",
19109d59b9SThomas Richter		"EventName": "L1I_DIR_WRITES",
20*d786bdf2SThomas Richter		"BriefDescription": "Level-1 I-Cache Directory Write Count",
21*d786bdf2SThomas Richter		"PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes."
22109d59b9SThomas Richter	},
23109d59b9SThomas Richter	{
249bacbcedSThomas Richter		"Unit": "CPU-M-CF",
25109d59b9SThomas Richter		"EventCode": "3",
26109d59b9SThomas Richter		"EventName": "L1I_PENALTY_CYCLES",
27*d786bdf2SThomas Richter		"BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
28*d786bdf2SThomas Richter		"PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 instruction cache or unified cache."
29109d59b9SThomas Richter	},
30109d59b9SThomas Richter	{
319bacbcedSThomas Richter		"Unit": "CPU-M-CF",
32109d59b9SThomas Richter		"EventCode": "4",
33109d59b9SThomas Richter		"EventName": "L1D_DIR_WRITES",
34*d786bdf2SThomas Richter		"BriefDescription": "Level-1 D-Cache Directory Write Count",
35*d786bdf2SThomas Richter		"PublicDescription": "This counter counts the total number of level-1 data-cache directory writes."
36109d59b9SThomas Richter	},
37109d59b9SThomas Richter	{
389bacbcedSThomas Richter		"Unit": "CPU-M-CF",
39109d59b9SThomas Richter		"EventCode": "5",
40109d59b9SThomas Richter		"EventName": "L1D_PENALTY_CYCLES",
41*d786bdf2SThomas Richter		"BriefDescription": "Level-1 D-Cache Penalty Cycle Count",
42*d786bdf2SThomas Richter		"PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 data cache."
43109d59b9SThomas Richter	},
44109d59b9SThomas Richter	{
459bacbcedSThomas Richter		"Unit": "CPU-M-CF",
46109d59b9SThomas Richter		"EventCode": "32",
47109d59b9SThomas Richter		"EventName": "PROBLEM_STATE_CPU_CYCLES",
48*d786bdf2SThomas Richter		"BriefDescription": "Problem-State Cycle Count",
49*d786bdf2SThomas Richter		"PublicDescription": "This counter counts the total number of CPU cycles when the CPU is in the problem state, excluding the number of cycles while the CPU is in the wait state."
50109d59b9SThomas Richter	},
51109d59b9SThomas Richter	{
529bacbcedSThomas Richter		"Unit": "CPU-M-CF",
53109d59b9SThomas Richter		"EventCode": "33",
54109d59b9SThomas Richter		"EventName": "PROBLEM_STATE_INSTRUCTIONS",
55*d786bdf2SThomas Richter		"BriefDescription": "Problem-State Instruction Count",
56*d786bdf2SThomas Richter		"PublicDescription": "This counter counts the total number of instructions executed by the CPU while in the problem state."
5708f3e087SJames Clark	}
58109d59b9SThomas Richter]
59