| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | rk3399-ddr.h | 7 * DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for
11 /* DDR3-800 (5-5-5) */
13 /* DDR3-800 (6-6-6) */
15 /* DDR3-1066 (6-6-6) */
17 /* DDR3-1066 (7-7-7) */
19 /* DDR3-1066 (8-8-8) */
21 /* DDR3-1333 (7-7-7) */
23 /* DDR3-1333 (8-8-8) */
25 /* DDR3-1333 (9-9-9) */
27 /* DDR3-1333 (10-10-10) */
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| /openbmc/u-boot/board/sunxi/ |
| H A D | dram_timings_sun4i.h | 4 # if CONFIG_DRAM_CLK <= 360 /* DDR3-1066F @360MHz, timings: 6-5-5-14 */
10 # elif CONFIG_DRAM_CLK <= 384 /* DDR3-1066F @384MHz, timings: 6-6-6-15 */
16 # elif CONFIG_DRAM_CLK <= 396 /* DDR3-1066F @396MHz, timings: 6-6-6-15 */
22 # elif CONFIG_DRAM_CLK <= 408 /* DDR3-1066F @408MHz, timings: 7-6-6-16 */
28 # elif CONFIG_DRAM_CLK <= 432 /* DDR3-1066F @432MHz, timings: 7-6-6-17 */
34 # elif CONFIG_DRAM_CLK <= 456 /* DDR3-1066F @456MHz, timings: 7-6-6-18 */
40 # elif CONFIG_DRAM_CLK <= 468 /* DDR3-1066F @468MHz, timings: 7-7-7-18 */
46 # elif CONFIG_DRAM_CLK <= 480 /* DDR3-1066F @480MHz, timings: 7-7-7-18 */
52 # elif CONFIG_DRAM_CLK <= 504 /* DDR3-1066F @504MHz, timings: 7-7-7-19 */
58 # elif CONFIG_DRAM_CLK <= 528 /* DDR3-1066F @528MHz, timings: 7-7-7-20 */
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| /openbmc/u-boot/board/siemens/draco/ |
| H A D | board.c | 74 printf("Set default DDR3 settings\n"); in set_default_ddr3_timings()
75 settings.ddr3 = ddr3_default; in set_default_ddr3_timings()
82 printf("device:\t\t%s\n", settings.ddr3.manu_name); in print_ddr3_timings()
83 printf("marking:\t%s\n", settings.ddr3.manu_marking); in print_ddr3_timings()
164 /* Read Siemens eeprom data (DDR3) */ in read_eeprom()
166 (uchar *)&settings.ddr3, sizeof(struct ddr3_data))) { in read_eeprom()
167 …d not read the EEPROM; something fundamentally wrong on the I2C bus.\nUse default DDR3 timings\n"); in read_eeprom()
175 if (ddr3_default.magic == settings.ddr3.magic && in read_eeprom()
176 ddr3_default.version == settings.ddr3.version) { in read_eeprom()
177 printf("Using DDR3 settings from EEPROM\n"); in read_eeprom()
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| H A D | board.h | 19 settings.ddr3.x, /* EEPROM Value */ \
21 settings.ddr3.x-ddr3_default.x /* Difference */
29 /* From file: draco/ddr3-data-universal-default@303MHz-i0-ES3.txt */
57 struct ddr3_data ddr3; member
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| /openbmc/u-boot/drivers/ddr/fsl/ |
| H A D | ddr3_dimm_params.c | 7 * from ddr3 spd, please refer to the spec
77 * ddr_compute_dimm_parameters for DDR3 SPD
95 printf("DIMM %u: is not a DDR3 SPD.\n", dimm_number); in ddr_compute_dimm_parameters()
131 /* These are the types defined by the JEDEC DDR3 SPD spec */ in ddr_compute_dimm_parameters()
184 * but DDR3 spec has nature BL8 and BC4, in ddr_compute_dimm_parameters()
209 * tck_min=15 MTB (1.875ns) ->DDR3-1066 in ddr_compute_dimm_parameters()
210 * =12 MTB (1.5ns) ->DDR3-1333 in ddr_compute_dimm_parameters()
211 * =10 MTB (1.25ns) ->DDR3-1600 in ddr_compute_dimm_parameters()
227 * DDR3-800D 100 MTB (12.5ns) in ddr_compute_dimm_parameters()
228 * DDR3-1066F 105 MTB (13.125ns) in ddr_compute_dimm_parameters()
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| H A D | Kconfig | 93 Enable Freescale DDR3 controller for PowerPC SoCs.
99 Enable Freescale DDR3 controller for ARM SoCs.
131 bool "Freescale DDR3 controller"
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| /openbmc/u-boot/drivers/ddr/marvell/a38x/ |
| H A D | ddr3_training_db.c | 65 /* DDR3-800D */
67 /* DDR3-800E */
69 /* DDR3-1066E */
71 /* DDR3-1066F */
73 /* DDR3-1066G */
75 /* DDR3-1333F* */
77 /* DDR3-1333G */
79 /* DDR3-1333H */
81 /* DDR3-1333J* */
83 /* DDR3-1600G* */},
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| H A D | ddr3_init.c | 9 static char *ddr_type = "DDR3";
20 * Name: ddr3_init - Main DDR3 Init function
21 * Desc: This routine initialize the DDR3 MC and runs HW training.
69 printf("DDR3 Post Init - FAILED 0x%x\n", status); in ddr3_init()
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| /openbmc/u-boot/drivers/ddr/marvell/axp/ |
| H A D | ddr3_pbs.c | 71 * Args: dram_info ddr3 training information struct
102 DEBUG_PBS_S("DDR3 - PBS TX - Starting PBS TX procedure\n"); in ddr3_pbs_tx()
113 DEBUG_PBS_S("DDR3 - PBS RX - SW Override Enabled\n"); in ddr3_pbs_tx()
120 DEBUG_PBS_C("DDR3 - PBS TX - Working with pattern - ", in ddr3_pbs_tx()
166 DEBUG_PBS_S("DDR3 - PBS Tx - ECC Mux Enabled\n"); in ddr3_pbs_tx()
168 DEBUG_PBS_S("DDR3 - PBS Tx - ECC Mux Disabled\n"); in ddr3_pbs_tx()
191 DEBUG_PBS_S("DDR3 - PBS Tx - Pbs Rep Loop is "); in ddr3_pbs_tx()
198 DEBUG_PBS_S("DDR3 - PBS Tx - Set all PBS values to MIN\n"); in ddr3_pbs_tx()
215 DEBUG_PBS_S("DDR3 - PBS Tx - ADLL shift right one phase before fail\n"); in ddr3_pbs_tx()
223 DEBUG_PBS_S("DDR3 - PBS Tx - perform PBS for each bit\n"); in ddr3_pbs_tx()
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| H A D | ddr3_hw_training.c | 64 puts("DDR3 Training Sequence - Ver 5.7."); in ddr3_print_version()
90 DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 1\n"); in ddr3_hw_training()
176 * Not all frequency modes support the ddr3 training sequence in ddr3_hw_training()
179 * inside the ddr3 training sequence without running the training in ddr3_hw_training()
184 DEBUG_MAIN_S("DDR3 Training Sequence - Run with PBS.\n"); in ddr3_hw_training()
186 DEBUG_MAIN_S("DDR3 Training Sequence - Run without PBS.\n"); in ddr3_hw_training()
198 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Dfs High2Low)\n"); in ddr3_hw_training()
207 DEBUG_MAIN_S("DDR3 Training Sequence - Registered DIMM Low WL - SKIP\n"); in ddr3_hw_training()
214 DEBUG_MAIN_S("DDR3 Training Sequence - DEBUG - 2\n"); in ddr3_hw_training()
233 DEBUG_MAIN_S("DDR3 Training Sequence - FAILED (Write Leveling Sw)\n"); in ddr3_hw_training()
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| H A D | ddr3_dqs.c | 135 DEBUG_DQS_S("DDR3 - DQS Centralization RX - Starting procedure\n"); in ddr3_dqs_centralization_rx()
144 DEBUG_DQS_S("DDR3 - DQS Centralization RX - SW Override Enabled\n"); in ddr3_dqs_centralization_rx()
152 DEBUG_DQS_FULL_C("DDR3 - DQS Centralization RX - CS - ", in ddr3_dqs_centralization_rx()
165 DEBUG_DQS_FULL_S("DDR3 - DQS Centralization RX - ECC Mux Enabled\n"); in ddr3_dqs_centralization_rx()
167 DEBUG_DQS_FULL_S("DDR3 - DQS Centralization RX - ECC Mux Disabled\n"); in ddr3_dqs_centralization_rx()
169 DEBUG_DQS_FULL_S("DDR3 - DQS Centralization RX - Find all limits\n"); in ddr3_dqs_centralization_rx()
176 DEBUG_DQS_FULL_S("DDR3 - DQS Centralization RX - Start calculating center\n"); in ddr3_dqs_centralization_rx()
217 DEBUG_DQS_S("DDR3 - DQS Centralization TX - Starting procedure\n"); in ddr3_dqs_centralization_tx()
226 DEBUG_DQS_S("DDR3 - DQS Centralization TX - SW Override Enabled\n"); in ddr3_dqs_centralization_tx()
234 DEBUG_DQS_FULL_C("DDR3 - DQS Centralization TX - CS - ", in ddr3_dqs_centralization_tx()
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| H A D | ddr3_write_leveling.c | 71 DEBUG_WL_S("DDR3 - Write Leveling - Starting HW WL procedure\n"); in ddr3_write_leveling_hw()
134 DEBUG_WL_S("DDR3 - Write Leveling - Write Leveling Cs - "); in ddr3_write_leveling_hw()
143 DEBUG_WL_S("DDR3 - Write Leveling - PUP: "); in ddr3_write_leveling_hw()
168 DEBUG_WL_S("DDR3 - Write Leveling - HW WL Ended Successfully\n"); in ddr3_write_leveling_hw()
172 DEBUG_WL_S("DDR3 - Write Leveling - HW WL Error\n"); in ddr3_write_leveling_hw()
196 DEBUG_WL_S("DDR3 - Write Leveling Hi-Freq Supplement - Starting\n"); in ddr3_wl_supplement()
224 DEBUG_WL_S("DDR3 - Write Leveling Hi-Freq Supplement - SW Override Enabled\n"); in ddr3_wl_supplement()
416 DEBUG_WL_C("DDR3 - Write Leveling Hi-Freq Supplement - didn't work for Cs - ", in ddr3_wl_supplement()
459 DEBUG_WL_S("DDR3 - Write Leveling Hi-Freq Supplement - Ended Successfully\n"); in ddr3_wl_supplement()
478 DEBUG_WL_S("DDR3 - Write Leveling - Starting HW WL procedure\n"); in ddr3_write_leveling_hw_reg_dimm()
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| H A D | ddr3_spd.c | 169 u32 min_write_recovery_time; /* DDR3/2 only */
170 u32 min_write_to_read_cmd_delay; /* DDR3/2 only */
171 u32 min_read_to_prech_cmd_delay; /* DDR3/2 only */
173 u32 min_refresh_recovery; /* DDR3/2 only */
255 /* Check if DDR3 */ in ddr3_spd_init()
260 /* No byte for error check in DDR3 SPD, use DDR2 convention */ in ddr3_spd_init()
329 * DDR3 device uiDensity val are: (device capacity/8) * in ddr3_spd_init()
332 /* Jedec SPD DDR3 - page 7, Save spd_data in Mb - 2048=2GB */ in ddr3_spd_init()
366 /* No byte for refresh interval in DDR3 SPD, use DDR2 convention */ in ddr3_spd_init()
387 /* DDR3 include 2 byte of CAS support */ in ddr3_spd_init()
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| H A D | ddr3_read_leveling.c | 66 DEBUG_RL_S("DDR3 - Read Leveling - Starting HW RL procedure\n"); in ddr3_read_leveling_hw()
127 DEBUG_RL_C("DDR3 - Read Leveling - Results for CS - ", in ddr3_read_leveling_hw()
136 DEBUG_RL_S("DDR3 - Read Leveling - PUP: "); in ddr3_read_leveling_hw()
157 DEBUG_RL_C("DDR3 - Read Leveling - Read Sample Delay: ", in ddr3_read_leveling_hw()
159 DEBUG_RL_C("DDR3 - Read Leveling - Read Ready Delay: ", in ddr3_read_leveling_hw()
161 DEBUG_RL_S("DDR3 - Read Leveling - HW RL Ended Successfully\n"); in ddr3_read_leveling_hw()
166 DEBUG_RL_S("DDR3 - Read Leveling - HW RL Error\n"); in ddr3_read_leveling_hw()
185 DEBUG_RL_S("DDR3 - Read Leveling - Starting SW RL procedure\n"); in ddr3_read_leveling_sw()
203 DEBUG_RL_C("DDR3 - Read Leveling - CS - ", (u32) cs, 1); in ddr3_read_leveling_sw()
214 DEBUG_RL_S("DDR3 - Read Leveling - ECC Mux Enabled\n"); in ddr3_read_leveling_sw()
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| H A D | ddr3_init.c | 161 DEBUG_INIT_FULL_S("DDR3 Training Sequence - Switching XBAR Window to FastPath Window\n"); in ddr3_restore_and_set_final_windows()
268 * Name: ddr3_init - Main DDR3 Init function
269 * Desc: This routine initialize the DDR3 MC and runs HW training.
283 DEBUG_INIT_S("DDR3 Training Error: Bad sample at reset"); in ddr3_init()
285 DEBUG_INIT_S("DDR3 Training Error: Bad DIMM setup"); in ddr3_init()
287 DEBUG_INIT_S("DDR3 Training Error: Max CS limit"); in ddr3_init()
289 DEBUG_INIT_S("DDR3 Training Error: Max enable CS limit"); in ddr3_init()
291 DEBUG_INIT_S("DDR3 Training Error: Bad R-DIMM setup"); in ddr3_init()
293 DEBUG_INIT_S("DDR3 Training Error: TWSI failure"); in ddr3_init()
295 DEBUG_INIT_S("DDR3 Training Error: DIMM type no match"); in ddr3_init()
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| /openbmc/u-boot/board/freescale/mx6memcal/ |
| H A D | Kconfig | 88 Select the type of DDR (DDR3 or LPDDR2) used on your design
90 config DDR3 config in mx6memcal specifics""choicec87005010304
91 bool "DDR3"
93 Select this if your board design uses DDR3.
107 depends on DDR3
111 depends on DDR3
115 depends on DDR3
119 depends on DDR3
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| /openbmc/u-boot/arch/arm/mach-sunxi/ |
| H A D | Kconfig | 372 bool "DDR3 1333"
402 Set the dram type, 3: DDR3, 7: LPDDR3
416 (for DDR3-1600) are 312 to 792.
486 Select the timings of the DDR3 chips.
494 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
496 Use the timings of the standard JEDEC DDR3-1066F speed bin for
497 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
498 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
499 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
500 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
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| /openbmc/u-boot/board/ti/ks2_evm/ |
| H A D | ddr3_k2e.c | 3 * Keystone2: DDR3 initialization
11 #include <asm/arch/ddr3.h>
29 printf("DDR3 speed %d\n", spd_cb.ddrspdclock); in ddr3_init()
35 /* Reset DDR3 PHY after PLL enabled */ in ddr3_init()
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| H A D | ddr3_k2l.c | 3 * Keystone2: DDR3 initialization
11 #include <asm/arch/ddr3.h>
22 /* Reset DDR3 PHY after PLL enabled */ in ddr3_init()
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| H A D | ddr3_k2g.c | 3 * K2G: DDR3 initialization
11 #include <asm/arch/ddr3.h>
15 /* K2G GP EVM DDR3 Configuration */
116 /* K2G ICE evm DDR3 Configuration */
169 /* Reset DDR3 PHY after PLL enabled */ in ddr3_init()
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| /openbmc/u-boot/arch/arm/mach-rockchip/ |
| H A D | Kconfig | 12 including NEON and GPU, Mali-400 graphics, several DDR3 options
21 including NEON and GPU, Mali-400 graphics, several DDR3 options
56 including NEON and GPU, Mali-400 graphics, several DDR3 options
71 video interfaces supporting HDMI and eDP, several DDR3 options
91 video interfaces supporting HDMI and eDP, several DDR3 options
111 output processor supporting LVDS/HDMI/eDP, several DDR3 options and
145 video interfaces supporting HDMI and eDP, several DDR3 options
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | rockchip,rk3399-dmc.yaml | 52 DDR3 cl-trp-trcd type. It must be set according to "Speed Bin" in DDR3
53 datasheet; DO NOT use a smaller "Speed Bin" than specified for the DDR3
108 Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
109 than DRAM_DLL_DISB_FREQ, DDR3 DLL will be bypassed.
130 When the DRAM type is DDR3, this parameter defines the ODT disable
138 When the DRAM type is DDR3, this parameter defines the DRAM side drive
146 When the DRAM type is DDR3, this parameter defines the DRAM side ODT
154 When the DRAM type is DDR3, this parameter defines the phy side CA line
162 When the DRAM type is DDR3, this parameter defines the PHY side DQ line
170 When the DRAM type is DDR3, this parameter defines the PHY side ODT
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| /openbmc/u-boot/arch/arm/mach-keystone/include/mach/ |
| H A D | clock-k2hk.h | 38 #define DDR3_PLL_200(x) {DDR3##x##_PLL, 4, 1, 2}
39 #define DDR3_PLL_400(x) {DDR3##x##_PLL, 16, 1, 4}
40 #define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2}
41 #define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6}
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| /openbmc/u-boot/arch/arm/mach-keystone/ |
| H A D | ddr3.c | 3 * Keystone2: DDR3 initialization
12 #include <asm/arch/ddr3.h>
116 /* Check the DDR3 controller ID reg if the controllers in ddr3_ecc_support_rmw()
158 puts("\nClear entire DDR3 memory to enable ECC\n"); in ddr3_reset_data()
189 /* DDR3 size in segments (4KB seg size) */ in ddr3_reset_data()
320 /* mapping DDR3 ECC system interrupt from CIC2 to GIC */ in ddr3_init_ecc()
338 puts("DDR3 ECC write error interrupted\n"); in ddr3_check_ecc_int()
341 puts("DDR3 ECC 2-bit error interrupted\n"); in ddr3_check_ecc_int()
388 * Check for PGSR0 error bits of DDR3 PHY. in ddr3_err_reset_workaround()
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| /openbmc/u-boot/arch/mips/mach-mscc/ |
| H A D | Kconfig | 66 bool "Hynix H5TQ4G63MFR-PBC (4Gbit, DDR3-800, 256Mbitx16)"
72 bool "Hynix H5TQ1G63BFA (1Gbit DDR3, x16)"
75 bool "Micron MT41J128M16HA-15E:D (2Gbit DDR3, x16)"
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